proc_mux: avoid redundant mux cells for full_case switches with a dominant arm value

[likeamahoney]

Problem

When proc_rmdead removes an exhausted implicit default branch it marks the switch full_case. proc_mux then masks all covered signal bits to Sx before the mux-generation loop. If most arms assign the same value, every arm still produces a concrete value ≠ Sx and gets its own $eq+$mux pair - even the identical ones.

While experimenting with the Verilog code of the open-source tv80 processor, I noticed that this behavior can lead to a large number of redundant cells. After minimizing the example (see attached file - tv80_reduced.txt), the generated netlist contained almost two orders of magnitude more cells than necessary (see comparison in files with and without the patch - tv80redstat_with_patch.txt and tv80redstat_wo_patch.txt). And both designs are semantically equivalent after evaluation. On the original tv80_mcode module the effect is smaller, but the optimization still reduces the cell count by around 5-8% (see comparison in files with and without the patch tv80stat_wo_patch.txt and tv80stat_with_patch.txt).

For cell stats comparison I used such pipeline:

read_verilog test.sv; proc; opt; stat -hierarchy -tech cmos;

Fix

After the full_case_bits to Sx mask, scan all arms' direct actions and find the majority value for each signal bit. If one value appears in more than half the arms, use it as the initial result seed instead of Sx. The existing gen_mux early-return (when == else - skip) then silently elides cells for every arm that matches the dominant value.

[whitequark]

This is a very interesting solution to a problem I've tried to fix before (without success).