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VLSIDA
gf180mcu-project-template
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Bump submodules to newer versions
CI
#17:
Commit
66f290a
pushed by
mguthaus
3h 57m 28s
3v3-libraries
3v3-libraries
3h 57m 28s
View workflow file
fix: ignore fill/tap/decap cells during LVS to avoid netgen hang
CI
#16:
Commit
2bd2813
pushed by
mguthaus
4h 22m 4s
3v3-libraries
3v3-libraries
4h 22m 4s
View workflow file
Update to have a ring of area IOs.
CI
#15:
Commit
be1b30e
pushed by
mguthaus
3h 35m 43s
area-io-pad
area-io-pad
3h 35m 43s
View workflow file
fix: make gf180mcu_ws_io__area pass through librelane-nodrc
CI
#14:
Commit
eebdabc
pushed by
mguthaus
58m 21s
area-io-pad
area-io-pad
58m 21s
View workflow file
feat: add gf180mcu_ws_io__area, a bare wire-bondable area IO pad
CI
#13:
Commit
7a90363
pushed by
mguthaus
3m 29s
area-io-pad
area-io-pad
3m 29s
View workflow file
fix: use adder.pnl.v for GL simulation
CI
#12:
Commit
bf2e118
pushed by
mguthaus
3h 30m 40s
adder-hierarchy
adder-hierarchy
3h 30m 40s
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ci: harden the adder block before chip implementation
CI
#11:
Commit
564605c
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mguthaus
2h 39m 27s
adder-hierarchy
adder-hierarchy
2h 39m 27s
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feat: connect adder PDN via SRAM-style M3 pin technique
CI
#10:
Commit
0e47f39
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mguthaus
2m 59s
adder-hierarchy
adder-hierarchy
2m 59s
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fix: init SRAM submodule in install-3v3-scl target
CI
#9:
Commit
ba4f3be
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3h 56m 27s
3v3-libraries
3v3-libraries
3h 56m 27s
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fix: install 3.3V SCL in CI before build and simulation
CI
#8:
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c139356
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3h 53m 25s
3v3-libraries
3v3-libraries
3h 53m 25s
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chore: move spice generation to src/, update CLAUDE.md and Makefile
CI
#7:
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a4dac10
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mguthaus
6h 5m 8s
adpll
adpll
6h 5m 8s
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chore: update flake to librelane 3.0 (#57)
CI
#6:
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8bd0f6f
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3h 27m 36s
main
main
3h 27m 36s
View workflow file
fix: add --scl flag and patched config.tcl for 3.3V SCL support
CI
#5:
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44b2316
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2m 42s
3v3-libraries
3v3-libraries
2m 42s
View workflow file
fix: add synchronizer on fb_clk for bang-bang PFD metastability
CI
#4:
Commit
dd49ab8
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11h 49m 55s
main
main
11h 49m 55s
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fix: frequency acquisition with gray-coded counter and realistic delays
CI
#3:
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ea7e6ce
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mguthaus
2m 35s
main
main
2m 35s
View workflow file
docs: add CLAUDE.md with project context and build instructions
CI
#2:
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b1aa617
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mguthaus
16m 19s
main
main
16m 19s
View workflow file
feat: add all-digital PLL (ADPLL) with ring oscillator DCO
CI
#1:
Commit
3779a92
pushed by
mguthaus
6h 5m 12s
main
main
6h 5m 12s
View workflow file
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