C-extended fetch stage and instruction reader module#252
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SiddharthShroff-dotcom wants to merge 17 commits into
Open
C-extended fetch stage and instruction reader module#252SiddharthShroff-dotcom wants to merge 17 commits into
SiddharthShroff-dotcom wants to merge 17 commits into
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Implemented initial RVC fetch support with compressed instruction handling, decompression path integration, same-word buffering, and split instruction handling. Main aligned, compressed, branch-target, and split-at-PC-0x02 cases are passing locally. Stall/flush interaction and later split-boundary cases still need follow-up. Requires C decompressor module from Andrew.
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🔧 DE1-SoC Synthesis Report Summary Diff
Comparing synthesis results from main branch vs. this PR |
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| // TODO: probably can just get rid of those altogether | ||
| wire unused = &{ex_to_if.pc_old, ex_to_if.imm_ext}; | ||
| //assign imem__address = pc_cur; |
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for the changes in fetch here -- would you be able to move them into a fetch_compressed module (feel free to pick a different name) and conditionally instantiate it here similarly to how we do this for example with B extension decoder:
risc-v/src/modules/Instruction_Decode/Instruction_Decode.sv
Lines 141 to 154 in 2a95e8f
Probably also need to add C extension into makefile so that we have UTOSS_RISCV_ENABLE_C_EXT defined, but we can do that during integration
| , .reset(reset) | ||
| , .stall_f(stall_f) | ||
| , .flush_f(flush_f) | ||
| , .imem__address(imem__address) |
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We are probably going to get a "multiple drivers" error here, since this is being driven unconditionally during regular fetch operation
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| `ifdef UTOSS_RISCV_ENABLE_C_EXT |
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Can you update both the top-level Makefile and the de1-soc's envs/de1-soc/quartus/scripts/synthesize.tcl script to make sure UTOSS_RISCV_ENABLE_C_EXT gets defined when we include "C" in the UTOSS_RISCV_CONFIG; you'll also need to update ci.yaml too to include "C" in the build matrix.
This is kinda loaded so lmk if you have any questions.
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Implemented initial RVC fetch support in the fetch stage and instruction reader.
Main changes:
Added mixed 16-bit/32-bit instruction handling.
Added same-word buffering for compressed instructions.
Added split-instruction handling for 32-bit instructions crossing a 32-bit word boundary.
Integrated compressed instruction decompression before decode.
Updated fetch next-PC behavior to support PC+2 and PC+4 sequencing.
Locally tested passing cases include aligned 32-bit fetch, two compressed instructions in one word, compressed-to-split fetch, back-to-back split handling, branch targets to compressed/split instructions, and compressed PC+2 behavior.
Known follow-up work: stall/flush interaction and later split-boundary edge cases still need further testing/debugging.