hooked up B ext and started testing

Makefile

@@ -21,7 +21,7 @@ RISCOF_CONFIG        := $(RISCOF_DIR)/config.ini
 
 UTOSS_RISCV_CONFIG ?= RV32I
 
-UTOSS_RISCV_VERILATOR_DEFINES := $(if $(findstring B,$(UTOSS_RISCV_CONFIG)),-DUTOSS_RISCV_ENABLE_B_EXT)
+UTOSS_RISCV_VERILATOR_DEFINES := $(if $(findstring Zb,$(UTOSS_RISCV_CONFIG)),-DUTOSS_RISCV_ENABLE_B_EXT) #changed from B -> Zb
 UTOSS_RISCV_RISCOF_VERILATOR_DEFINES := -DUTOSS_PIPELINE_LOGGER
 
 # ===========================
@@ -177,4 +177,4 @@ svlint_tb:
 .PHONY: all build_top run_top build_tb run_tb new_tb \
         svlint svlint_tb \
         riscof_build_dut riscof_validateyaml riscof_clone_archtest \
-        riscof_generate_testlist riscof_run
+        riscof_generate_testlist riscof_run

riscof/sail_cSim/riscof_sail_cSim.py

@@ -121,4 +121,4 @@ def runTests(self, testList, cgf_file=None):
             execute+=coverage_cmd
 
             make.add_target(execute)
-        make.execute_all(self.work_dir)
+        make.execute_all(self.work_dir)

riscof/utoss_riscv/riscof_utoss_riscv.py

@@ -272,4 +272,4 @@ def runTests(self, testList):
 #      # if target runs are not required then we simply exit as this point after running all
 #      # the makefile targets.
 #      if not self.target_run:
-#          raise SystemExit
+#          raise SystemExit

riscof/utoss_riscv/utoss_riscv_isa.yaml

@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32I
+  ISA: RV32IZbb
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]
@@ -26,4 +26,3 @@ hart0:
                 - extensions[25:0] bitmask [0x0000100, 0x0000000]
               wr_illegal:
                 - Unchanged
-

src/ext/b/decoder.sv

@@ -21,6 +21,9 @@ module ext__b__decoder
   localparam bit [6:0] FUNCT7_ZBB__SEXT = 7'b0110000;
   localparam bit [6:0] FUNCT7_ZBB__ZEXT = 7'b0000100;
 
+  localparam bit [6:0] FUNCT7_ZBB__CTZ  = 7'b0110001; //NEW
+  localparam bit [6:0] FUNCT7_ZBB__CPOP = 7'b0110010; //NEW
+
   always_comb
     case (opcode)
       7'b0110011:
@@ -59,22 +62,35 @@ module ext__b__decoder
           default: b_alu_control = B_ALU_CTRL__NONE;
 
         endcase
-      7'b0010011:
+      7'b0010011: //NEW modified block to fix the clz test error
         case (funct7)
           FUNCT7_ZBB__SEXT:
             case (funct3)
               3'b001:
                 case (rs2)
                   5'b00100:  b_alu_control = B_ALU_CTRL__SEXTB;
                   5'b00101:  b_alu_control = B_ALU_CTRL__SEXTH;
-                  default: b_alu_control = B_ALU_CTRL__NONE;
+                  5'b00000:  b_alu_control = B_ALU_CTRL__CLZ;
+                  default:   b_alu_control = B_ALU_CTRL__NONE;
                 endcase
               default: b_alu_control = B_ALU_CTRL__NONE;
             endcase
-          default: b_alu_control = B_ALU_CTRL__NONE;
 
+          FUNCT7_ZBB__CTZ: // 0110001
+            case (funct3)
+              3'b001: b_alu_control = B_ALU_CTRL__CTZ;
+              default: b_alu_control = B_ALU_CTRL__NONE;
+            endcase
+
+          FUNCT7_ZBB__CPOP: // 0110010
+            case (funct3)
+              3'b001: b_alu_control = B_ALU_CTRL__CPOP;
+              default: b_alu_control = B_ALU_CTRL__NONE;
+            endcase
+
+          default: b_alu_control = B_ALU_CTRL__NONE;
         endcase
       default: b_alu_control = B_ALU_CTRL__NONE;
-    endcase
+ endcase
 
 endmodule

src/ext/b/zbb.sv

@@ -16,23 +16,26 @@ module zbb(
   localparam int COUNT_WIDTH = $clog2(XLEN + 1);
 
   function automatic logic [COUNT_WIDTH - 1:0] get_clz(input logic [XLEN - 1:0] val);
-    get_clz = XLEN;
+    get_clz = COUNT_WIDTH'(XLEN);
     for (int i=0; i < XLEN; i++) begin
-      if (val[i]) get_clz = XLEN - 1 - i;
+      if (val[i]) get_clz = COUNT_WIDTH'(XLEN - 1 - i);
     end
   endfunction
 
   function automatic logic [COUNT_WIDTH - 1:0] get_ctz(input logic [XLEN - 1:0] val);
-    get_ctz = XLEN;
-    for (int i=XLEN - 1; i >= 0; i--) begin
-      if (val[i]) get_ctz = i;
+    get_ctz = COUNT_WIDTH'(XLEN);
+    for (int i=0; i < XLEN; i++) begin
+      if (val[i]) begin
+        get_ctz = COUNT_WIDTH'(i);
+        break;
+      end
     end
   endfunction
 
   function automatic logic [COUNT_WIDTH - 1:0] get_cpop(input logic [XLEN - 1:0] val);
     get_cpop = 0;
     for (int i=0; i < XLEN; i++) begin
-      if (val[i]) get_cpop++;
+      if (val[i]) get_cpop = get_cpop + 1'b1;
     end
   endfunction
 

src/interfaces/id_to_ex_if.svh

@@ -16,6 +16,7 @@ typedef struct packed {
   logic         mem_write;
   logic         reg_write;
   alu_control_t alu_control;
+  ext__b__types::b_alu_control_t b_alu_control; //NEW
   logic [2:0]   funct3;
   data_t        rd1;
   data_t        rd2;

src/modules/Instruction_Decode/Instruction_Decode.sv

@@ -11,6 +11,9 @@
   , output reg [4:0] rd
   , output reg [4:0] rs1
   , output reg [4:0] rs2
+  `ifdef UTOSS_RISCV_ENABLE_B_EXT
+  , output ext__b__types::b_alu_control_t b_alu_control //NEW
+  `endif
   );
 
   alu_op_t alu_op;
@@ -93,6 +96,7 @@
 
         rd = instr[11:7];
         rs1 = instr[19:15];
+        rs2 = instr[24:20];
 
       end
 
@@ -138,10 +142,9 @@
     , .alu_op(alu_op)
     , .alu_control(ALUControl)
     );
+
+
 `ifdef UTOSS_RISCV_ENABLE_B_EXT
-/* verilator lint_off UNUSEDSIGNAL */
-  ext__b__types::b_alu_control_t b_alu_control;
-/* verilator lint_on UNUSEDSIGNAL */
   ext__b__decoder u_ext__b__decoder
     ( .funct3        ( funct3        )
     , .funct7        ( funct7        )
@@ -150,7 +153,9 @@
     , .rs2           ( rs2           )
     , .b_alu_control ( b_alu_control )
     );
-
 `endif
 
 endmodule
+// verilator lint_off UNUSEDSIGNAL 
+
+// verilator lint_on UNUSEDSIGNAL 

src/stages/decode_stage.sv

@@ -30,6 +30,10 @@ module decode_stage
   alu_src_b_t      cfsm__alu_src_b;
 
   alu_control_t    alu_control;
+  `ifdef UTOSS_RISCV_ENABLE_B_EXT
+  ext__b__types::b_alu_control_t b_alu_control; //NEW
+  `endif
+
 
   opcode_t opcode;
   imm_t    imm_ext;
@@ -67,6 +71,9 @@ module decode_stage
     , .rd              ( rd               )
     , .rs1             ( rs1              )
     , .rs2             ( rs2              )
+    `ifdef UTOSS_RISCV_ENABLE_B_EXT
+    , .b_alu_control   ( b_alu_control    ) //NEW
+    `endif
     );
 
   registerFile RegFile
@@ -105,6 +112,9 @@ module decode_stage
   assign id_to_ex.mem_write      = cfsm__mem_write;
   assign id_to_ex.reg_write      = cfsm__reg_write;
   assign id_to_ex.alu_control    = alu_control;
+  `ifdef UTOSS_RISCV_ENABLE_B_EXT
+    assign id_to_ex.b_alu_control = b_alu_control;
+  `endif
   assign id_to_ex.funct3         = funct3;
   assign id_to_ex.rd1            = rd1_safe;
   assign id_to_ex.rd2            = rd2_safe;
@@ -114,5 +124,6 @@ module decode_stage
   assign id_to_ex.imm_ext        = imm_ext;
   assign id_to_ex.pc_cur         = if_to_id.pc_cur;
   assign id_to_ex.pc_plus_4      = if_to_id.pc_plus_4;
+
 
 endmodule

src/stages/execute_stage.sv

@@ -24,6 +24,12 @@
   data_t alu_result;
   logic zero_flag;
 
+  `ifdef UTOSS_RISCV_ENABLE_B_EXT
+  data_t zbb_result; //NEW
+  logic  zbb_zero_flag; //NEW
+  `endif
+
+
   // ALU computation
 
   always_comb
@@ -56,14 +62,45 @@
       default:            alu_input_b = 'x;
     endcase
 
+  logic [`PROCESSOR_BITNESS-1:0] alu_result_base;
+  logic zero_flag_base;
   ALU alu
     ( .a              ( alu_input_a         )
     , .b              ( alu_input_b         )
     , .alu_control    ( id_to_ex.alu_control )
-    , .out            ( alu_result          )
-    , .zeroE          ( zero_flag           )
+    , .out            ( alu_result_base          )
+    , .zeroE          ( zero_flag_base           ) //added bases for local
+    );
+
+  `ifdef UTOSS_RISCV_ENABLE_B_EXT
+  always_comb begin
+    if (id_to_ex.b_alu_control != ext__b__types::B_ALU_CTRL__NONE) begin
+        alu_result = zbb_result;
+        zero_flag  = zbb_zero_flag;
+    end else begin
+        alu_result = alu_result_base;
+        zero_flag  = zero_flag_base;
+    end
+  end
+  `else
+  assign alu_result = alu_result_base;
+  assign zero_flag  = zero_flag_base;
+  `endif
+
+  `ifdef UTOSS_RISCV_ENABLE_B_EXT
+  zbb u_zbb
+    ( .a              ( alu_input_a            )
+    , .b              ( alu_input_b            )
+    , .b_alu_control  ( id_to_ex.b_alu_control )
+    , .out            ( zbb_result             )
+    , .zeroE          ( zbb_zero_flag          )
     );
+  `endif
+
+
 
+
+  //instantiate ZBB here, put in a single ALU
   // branching logic
 
   typedef enum logic [2:0]