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1. RISC-V-CPU RISC-V-CPU Public

   Creating a 5 stage pipe-lined processor on FPGAs using the RISC V instruction set architecture. Implementing the design using Verilog. This project is part of My 3rd Year project at The University …

   C

2. qemu qemu Public

   Qemu fork with the additions from the Zalasr specification. The Zalasr is the RISC-V Atomic Store-release and Load-acquire extension, which is currently frozen

   C

3. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   Assembly

4. nekko-buildstream nekko-buildstream Public

   Forked from nekkoai/nekko-buildstream

   AInekko BuildStream project aimed at producing containers for Open Source ML libraries.

   Python

5. yahtzee yahtzee Public

   Yahtzee Roguelite

   Rust

6. core-et-erbium core-et-erbium Public

   Forked from openhwgroup/core-et-erbium

   CORE-ET Silicon Platform erbium

   Verilog