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Fix bit manipulation overflow, VCD ID overflow, and corner tile detection #14

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Fix bit manipulation overflow, VCD ID overflow, and corner tile detection #14

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6 changes: 3 additions & 3 deletions crates/aegis-ip/src/tile_bits.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -94,15 +94,15 @@ pub fn set_bit(bits: &mut [u8], offset: usize) {
/// Clear bits at a given offset and width.
pub fn clear_bits(bits: &mut [u8], offset: usize, width: usize) {
for i in 0..width {
bits[(offset + i) / 8] &= !(1 << ((offset + i) % 8));
bits[(offset + i) / 8] &= !(1u8 << ((offset + i) % 8));
}
}

/// Write a value into the bitstream at a given bit offset and width.
pub fn write_bits(bits: &mut [u8], offset: usize, value: u64, width: usize) {
clear_bits(bits, offset, width);
for i in 0..width {
if value & (1 << i) != 0 {
if value & (1u64 << i) != 0 {
set_bit(bits, offset + i);
}
}
Expand All @@ -115,7 +115,7 @@ pub fn read_bits(bits: &[u8], offset: usize, width: usize) -> u64 {
let byte_idx = (offset + i) / 8;
let bit_idx = (offset + i) % 8;
if byte_idx < bits.len() && bits[byte_idx] & (1 << bit_idx) != 0 {
val |= 1 << i;
val |= 1u64 << i;
}
}
val
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6 changes: 5 additions & 1 deletion crates/aegis-sim/src/lib.rs
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Expand Up @@ -345,7 +345,11 @@ impl VcdWriter {

pub fn add_signal(&mut self, name: &str) -> char {
let id = self.next_id;
self.next_id = (self.next_id as u8 + 1) as char;
if id < '~' {
self.next_id = (self.next_id as u8 + 1) as char;
} else {
panic!("VcdWriter: too many signals for single-character VCD IDs");
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@RossComputerGuy RossComputerGuy Apr 9, 2026

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Should return an error, please use thiserror to define a new error type.

}
self.buf
.push_str(&format!("$var wire 1 {id} {name} $end\n"));
self.signals.push((name.to_string(), id));
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9 changes: 6 additions & 3 deletions nextpnr-aegis/aegis.cc
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Expand Up @@ -238,7 +238,7 @@ struct AegisImpl : ViaductAPI {
tw.track_w.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("W%d", t)),
ctx->id("ROUTING"), x, y));
}
} else if (x != y) {
} else if (!(x == 0 && y == 0) && !(x == W - 1 && y == 0) && !(x == 0 && y == H - 1) && !(x == W - 1 && y == H - 1)) {
// IO tile wires
for (int z = 0; z < 2; z++) {
tw.pad.push_back(ctx->addWire(h.xy_id(x, y, ctx->idf("PAD%d", z)),
Expand Down Expand Up @@ -269,7 +269,9 @@ struct AegisImpl : ViaductAPI {
for (int y = 0; y < H; y++) {
for (int x = 0; x < W; x++) {
if (is_io(x, y)) {
if (x == y)
// Skip corner tiles — they have no IO pads
if ((x == 0 && y == 0) || (x == W - 1 && y == 0) ||
(x == 0 && y == H - 1) || (x == W - 1 && y == H - 1))
continue;
add_io_bels(x, y);
} else {
Expand Down Expand Up @@ -320,7 +322,8 @@ struct AegisImpl : ViaductAPI {
for (int y = 0; y < H; y++) {
for (int x = 0; x < W; x++) {
if (is_io(x, y)) {
if (x != y)
if (!((x == 0 && y == 0) || (x == W - 1 && y == 0) ||
(x == 0 && y == H - 1) || (x == W - 1 && y == H - 1)))
add_io_pips(x, y);
} else {
add_logic_pips(x, y);
Expand Down
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