Fix incorrect IO tile corner detection in nextpnr-aegis

[hobostay]

Summary

The corner detection logic in nextpnr-aegis/aegis.cc used x != y / x == y to identify which IO tiles should have wires, BELs, and pips. This condition only excludes the diagonal corners (0,0) and (W-1,H-1), while incorrectly treating corners (W-1,0) and (0,H-1) as valid IO tiles.

Bug

For a grid of W×H (including IO ring), the four corners are:

• (0, 0) — excluded by x == y ✓
• (W-1, 0) — W-1 != 0, so incorrectly gets IO resources ✗
• (0, H-1) — 0 != H-1, so incorrectly gets IO resources ✗
• (W-1, H-1) — excluded by x == y ✓

This causes the nextpnr model to create IO BELs at two corners that don't correspond to actual IO pads in the FPGA hardware (as modeled by the Rust simulator). The placer could then assign IO cells to these non-existent pad positions, producing a bitstream that doesn't work on the device.

Fix

Add an is_corner() helper that correctly checks all four grid corners:

bool is_corner(int x, int y) const {
    return (x == 0 || x == W - 1) && (y == 0 || y == H - 1);
}

Replace the three occurrences of the incorrect condition in init_wires, init_bels, and init_pips.

Test plan

• Verify that for a 4×4 fabric (6×6 grid), only the 16 edge IO tiles (not corners) have IO BELs
• Run existing nextpnr tests if available
• Compare IO tile count against the Rust simulator's io_pad_pos construction

🤖 Generated with Claude Code