Aarch64 IR backend#931
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Adds an AArch64 codegen backend that plugs into the new IR pipeline
(jit.c -> jit_regs.c -> jit_aarch64.c), mirroring the role of
jit_x86_64.c. Targets Linux AAPCS64 (with the hooks needed for Apple
ARM64 ABI: X16/X17 reserved, 16-byte stack-arg packing).
Backend surface:
hl_jit_init_regs AAPCS64 register classes (X0..X15 scratch
minus X16/X17, X19..X28 persist; V0..V7
scratch+arg, V8..V15 persist, V16..V31 scratch)
hl_codegen_init module preamble: null-access stubs, c2hl/hl2c
trampolines
hl_codegen_function IR einstr stream -> AArch64 machine code
hl_codegen_flush_consts ADRP+LDR patching for the per-module pool
(distinguishes LDR Xt/Dt/St for correct imm12
scaling)
hl_codegen_final BL relocations, jump-table absolute fixups
Encoding layer (jit_aarch64_emit.c/h) supplies the instruction encoders
shared with the trampolines.
regs_config gains a stack_arg_size field so the IR's stack-argument
accounting agrees with the backend's 16-byte-per-push convention
required by AAPCS64 stack alignment.
module.c: on AArch64, walk the X29 frame-pointer chain in
module_capture_stack instead of the heuristic stack scanner. The
scanner produces false-positive frames from callee-saved STP X19,X20
spills that look like (stack_addr, code_addr) pairs.
Build: CMake selects src/jit_aarch64.c when the target processor is
aarch64/arm64; the Makefile gains an ARCH=arm64 branch.
Validated against unit.hl with all tests passing.
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Correct PR here: #932