VectorOps: Simplify 256-bit VAddV#5745
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| addv(SubRegSize.Vector, VTMP2.Q(), Vector.Q()); | ||
| addv(SubRegSize.Vector, VTMP1.Q(), VTMP1.Q()); | ||
| add(SubRegSize.Vector, Dst.Q(), VTMP1.Q(), VTMP2.Q()); | ||
| uaddv(SubRegSize.Vector, Dst.D(), Mask, Vector.Z()); |
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I don't think this exactly matches behaviour. Looks like this always zero extends smaller elements to be 64-bit, so overflow for something like 16-bit additions could return garbage in the upper 48-bits instead of truncating to a 16-bit scalar.
Which most operations immediately feed in to a VExtractToGPR so it can't see that, but something like PSADBWOpImpl isn't so it would be visible there.
Might want a unittest for the few instructions that /can/ overflow, and maybe a bool in the IR operation to force an element size mask for operations that need it? ptrue should be able to generate the mask, which will add a ptrue + mov pair if masking is absolutely required?
Didn't read the manual close enough on the first read award.
Sonicadvance1
approved these changes
Jul 15, 2026
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Didn't read the manual close enough on the first read when I dropped this in award.