From d179509de3919dc088b2aff25596aa60a94fa0a6 Mon Sep 17 00:00:00 2001 From: szy Date: Tue, 2 Jun 2026 09:32:40 +0800 Subject: [PATCH 01/50] initfs ok --- .../page_table_entry/src/arch/loongarch64.rs | 3 +- .../vms/linux-loongarch64-qemu-smp1.dts | 174 +++++++++++++ .../vms/linux-loongarch64-qemu-smp1.toml | 70 ++++++ .../loongarch/gintc-hwi-passthrough-freeze.md | 222 +++++++++++++++++ .../implementation-gaps-and-roadmap.md | 148 +++++++++++ os/axvisor/doc/loongarch/interrupt-wakeup.md | 125 ++++++++++ .../loongarch/linux-direct-boot-analysis.md | 122 +++++++++ os/axvisor/doc/loongarch/rootfs-virtio-blk.md | 75 ++++++ os/axvisor/doc/loongarch/stage2-tlb-refill.md | 37 +++ os/axvisor/scripts/quick-start.sh | 113 ++++++++- .../loongarch64-unknown-none-softfloat.json | 1 + os/axvisor/src/fdt/mod.rs | 6 +- os/axvisor/src/fdt/vm_fdt/writer.rs | 14 +- .../ax-plat-loongarch64-qemu-virt/Cargo.toml | 1 + .../src/console.rs | 4 +- .../src/irq/eiointc.rs | 4 + .../ax-plat-loongarch64-qemu-virt/src/lib.rs | 4 +- scripts/axbuild/src/context/mod.rs | 15 +- scripts/axbuild/src/context/tests/arceos.rs | 20 ++ virtualization/axvcpu/src/exit.rs | 37 +++ virtualization/axvcpu/src/vcpu.rs | 24 ++ .../loongarch_vcpu/src/context_frame.rs | 14 +- virtualization/loongarch_vcpu/src/exception.S | 232 +++++++++++++----- .../loongarch_vcpu/src/registers.rs | 44 +++- 24 files changed, 1411 insertions(+), 98 deletions(-) create mode 100644 os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.dts create mode 100644 os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.toml create mode 100644 os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md create mode 100644 os/axvisor/doc/loongarch/implementation-gaps-and-roadmap.md create mode 100644 os/axvisor/doc/loongarch/interrupt-wakeup.md create mode 100644 os/axvisor/doc/loongarch/linux-direct-boot-analysis.md create mode 100644 os/axvisor/doc/loongarch/rootfs-virtio-blk.md create mode 100644 os/axvisor/doc/loongarch/stage2-tlb-refill.md create mode 120000 os/axvisor/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json diff --git a/memory/page_table_entry/src/arch/loongarch64.rs b/memory/page_table_entry/src/arch/loongarch64.rs index 3e80cf359d..22475c54dd 100644 --- a/memory/page_table_entry/src/arch/loongarch64.rs +++ b/memory/page_table_entry/src/arch/loongarch64.rs @@ -157,7 +157,8 @@ impl GenericPTE for LA64PTE { } fn set_paddr(&mut self, paddr: PhysAddr) { - self.0 = (self.0 & !Self::PHYS_ADDR_MASK) | (paddr.as_usize() as u64 & Self::PHYS_ADDR_MASK) + self.0 = + (self.0 & !Self::PHYS_ADDR_MASK) | (paddr.as_usize() as u64 & Self::PHYS_ADDR_MASK); } fn set_flags(&mut self, flags: MappingFlags, is_huge: bool) { diff --git a/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.dts b/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.dts new file mode 100644 index 0000000000..fe674e74b1 --- /dev/null +++ b/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.dts @@ -0,0 +1,174 @@ +/dts-v1/; + +/ { + #size-cells = <0x02>; + #address-cells = <0x02>; + compatible = "linux,dummy-loongson3"; + + platform-bus@16000000 { + interrupt-parent = <0x8003>; + ranges = <0x00 0x00 0x16000000 0x2000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "qemu,platform\0simple-bus"; + }; + + poweroff { + value = <0x34>; + offset = <0x00>; + regmap = <0x8005>; + compatible = "syscon-poweroff"; + }; + + reboot { + value = <0x42>; + offset = <0x02>; + regmap = <0x8005>; + compatible = "syscon-reboot"; + }; + + ged@100e001c { + phandle = <0x8005>; + reg-io-width = <0x01>; + reg-shift = <0x00>; + reg = <0x00 0x100e001c 0x00 0x03>; + compatible = "syscon"; + }; + + rtc@100d0100 { + interrupt-parent = <0x8003>; + interrupts = <0x06 0x04>; + reg = <0x00 0x100d0100 0x00 0x100>; + compatible = "loongson,ls7a-rtc"; + }; + + serial@1fe001e0 { + interrupt-parent = <0x8003>; + interrupts = <0x02 0x04>; + clock-frequency = <0x5f5e100>; + reg = <0x00 0x1fe001e0 0x00 0x100>; + compatible = "ns16550a"; + }; + + serial@1fe002e0 { + status = "disabled"; + interrupt-parent = <0x8003>; + interrupts = <0x03 0x04>; + clock-frequency = <0x5f5e100>; + reg = <0x00 0x1fe002e0 0x00 0x100>; + compatible = "ns16550a"; + }; + + serial@1fe003e0 { + status = "disabled"; + interrupt-parent = <0x8003>; + interrupts = <0x04 0x04>; + clock-frequency = <0x5f5e100>; + reg = <0x00 0x1fe003e0 0x00 0x100>; + compatible = "ns16550a"; + }; + + serial@1fe004e0 { + status = "disabled"; + interrupt-parent = <0x8003>; + interrupts = <0x05 0x04>; + clock-frequency = <0x5f5e100>; + reg = <0x00 0x1fe004e0 0x00 0x100>; + compatible = "ns16550a"; + }; + + pcie@20000000 { + status = "disabled"; + interrupt-map-mask = <0x1800 0x00 0x00 0x07>; + interrupt-map = <0x00 0x00 0x00 0x01 0x8003 0x10 0x00 0x00 0x00 0x02 0x8003 0x11 0x00 0x00 0x00 0x03 0x8003 0x12 0x00 0x00 0x00 0x04 0x8003 0x13 0x800 0x00 0x00 0x01 0x8003 0x11 0x800 0x00 0x00 0x02 0x8003 0x12 0x800 0x00 0x00 0x03 0x8003 0x13 0x800 0x00 0x00 0x04 0x8003 0x10 0x1000 0x00 0x00 0x01 0x8003 0x12 0x1000 0x00 0x00 0x02 0x8003 0x13 0x1000 0x00 0x00 0x03 0x8003 0x10 0x1000 0x00 0x00 0x04 0x8003 0x11 0x1800 0x00 0x00 0x01 0x8003 0x13 0x1800 0x00 0x00 0x02 0x8003 0x10 0x1800 0x00 0x00 0x03 0x8003 0x11 0x1800 0x00 0x00 0x04 0x8003 0x12>; + msi-map = <0x00 0x8004 0x00 0x10000>; + ranges = <0x1000000 0x00 0x4000 0x00 0x18004000 0x00 0xc000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000>; + reg = <0x00 0x20000000 0x00 0x8000000>; + dma-coherent; + bus-range = <0x00 0x7f>; + linux,pci-domain = <0x00>; + #size-cells = <0x02>; + #address-cells = <0x03>; + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + }; + + msi@2ff00000 { + loongson,msi-num-vecs = <0xe0>; + loongson,msi-base-vec = <0x20>; + interrupt-parent = <0x8002>; + interrupt-controller; + reg = <0x00 0x2ff00000 0x00 0x08>; + compatible = "loongson,pch-msi-1.0"; + phandle = <0x8004>; + }; + + platic@10000000 { + loongson,pic-base-vec = <0x00>; + interrupt-parent = <0x8002>; + #interrupt-cells = <0x02>; + interrupt-controller; + reg = <0x00 0x10000000 0x00 0x400>; + compatible = "loongson,pch-pic-1.0"; + phandle = <0x8003>; + }; + + eiointc@1400 { + reg = <0x00 0x1400 0x00 0x800>; + interrupts = <0x03>; + interrupt-parent = <0x8001>; + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "loongson,ls2k2000-eiointc"; + phandle = <0x8002>; + }; + + cpuic { + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "loongson,cpu-interrupt-controller"; + phandle = <0x8001>; + }; + + flash@1c000000 { + bank-width = <0x04>; + reg = <0x00 0x1c000000 0x00 0x1000000 0x00 0x1d000000 0x00 0x1000000>; + compatible = "cfi-flash"; + }; + + fw_cfg@1e020000 { + dma-coherent; + reg = <0x00 0x1e020000 0x00 0x18>; + compatible = "qemu,fw-cfg-mmio"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x08000000>; + }; + + cpus { + #size-cells = <0x00>; + #address-cells = <0x01>; + + cpu-map { + socket0 { + core0 { + cpu = <0x8000>; + }; + }; + }; + + cpu@0 { + phandle = <0x8000>; + reg = <0x00>; + compatible = "loongarch,Loongson-3A5000"; + device_type = "cpu"; + }; + }; + + chosen { + bootargs = "console=ttyS0 root=/dev/ram rw rdinit=/init"; + stdout-path = "/serial@1fe001e0"; + }; +}; diff --git a/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.toml b/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.toml new file mode 100644 index 0000000000..956e8cf6bf --- /dev/null +++ b/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.toml @@ -0,0 +1,70 @@ +# Vm base info configs +# +[base] +# Guest vm id. +id = 1 +# Guest vm name. +name = "linux-loongarch64-qemu" +# Virtualization type. +vm_type = 1 +# The number of virtual CPUs. +cpu_num = 1 +# Guest vm physical cpu ids. +phys_cpu_ids = [0] + +# +# Vm kernel configs +# +[kernel] +# The entry point is replaced by the LoongArch ELF loader when vmlinux.elf is used. +entry_point = 0x0020_0000 +# The location of image: "memory" | "fs". +image_location = "fs" +# The file path of the kernel image. +kernel_path = "/guest/linux/qemu-loongarch64" +# The ELF LOAD paddr is used by the LoongArch loader; this is a fallback for flat images. +kernel_load_addr = 0x0020_0000 +# The file path of the device tree blob (DTB). +dtb_path = "/guest/linux/linux-loongarch64-qemu-smp1.dtb" +# The load address of the device tree blob (DTB). +dtb_load_addr = 0x0010_0000 +# The file path of the ramdisk image. +ramdisk_path = "/guest/linux/initramfs.cpio.gz" +# The load address of the ramdisk image. +ramdisk_load_addr = 0x0700_0000 +# Kernel command line. +cmdline = "root=/dev/ram rw console=ttyS0 earlycon=uart,mmio,0x1fe001e0 init=/init nokaslr pci=off initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" + +# Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`). +# For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`, 2 means `MAP_RESERVED`. +memory_regions = [ + [0x0008_0000, 0x0018_0000, 0x7, 0], # Low bootinfo/DTB RAM 512K-2M MAP_ALLOC + [0x0020_0000, 0x03e0_0000, 0x7, 0], # System RAM 2-64M MAP_ALLOC + [0x0400_0000, 0x0200_0000, 0x7, 0], # System RAM 64-96M MAP_ALLOC + [0x0600_0000, 0x0200_0000, 0x7, 0], # System RAM 96-128M MAP_ALLOC +] + +# +# Device specifications +# +[devices] +# The interrupt mode. +interrupt_mode = "passthrough" + +# Pass-through devices. +passthrough_devices = [ + ["/"], +] + +# Passthrough addresses. +# Base-GPA Length. +passthrough_addresses = [ +] + +# Devices that are not desired to be passed through to the guest +excluded_devices = [ +] + +# Emu_devices. +emu_devices = [ +] diff --git a/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md b/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md new file mode 100644 index 0000000000..6c062bd015 --- /dev/null +++ b/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md @@ -0,0 +1,222 @@ +# LoongArch64 LVZ: GINTC HWI Passthrough 导致 Guest UART 控制台卡死 + +## 现象 + +在 Axvisor (LoongArch64 QEMU-LVZ) 上以 passthrough 模式运行 Linux guest 时， +guest 控制台在执行若干命令后会**完全冻结**——不再响应任何输入输出，但 guest 内核本身并未崩溃。 + +**复现条件**： +- VM 配置：`passthrough_devices = [["/"]]`，`interrupt_mode = "passthrough"` +- 在 guest 内启动高频 shell 循环（如 `while true; do echo "..."; usleep 500000; done`） +- 同时手动输入命令 +- 通常在执行数十条命令后触发冻结 + +## 根因 + +`gintc_set_hwi_passthrough(0xff)` 在**每次 VM entry** 时被调用 +（调用链：`vcpu_run()` → `vm.run_vcpu()` → `vcpu.bind()` → `enable_guest_mode()`）， +该函数写 GINTC 寄存器时，其内部逻辑会清除 **HWIS（HWI Status）** 中的 pending 位， +导致在此间隙到达的 UART 中断被静默丢弃。 + +### GINTC 寄存器结构 (CSR 0x52) + +| 位域 | 名称 | 含义 | +|------|------|------| +| [7:0] | HWIS | HWI 中断 pending 状态（只读/写 1 清除） | +| [15:8] | HWIP | HWI passthrough 使能掩码 | +| [23:16] | HWIC | 写 1 清除对应 HWIS 位 | + +`gintc_set_hwi_passthrough()` 的**原始实现**同时写入了 HWIC=0xFF： + +```rust +// 原始代码（有 bug） +pub(crate) unsafe fn gintc_set_hwi_passthrough(mask: usize) { + let mut gintc = read_gintc(); + gintc &= !GINTC_HWIP_MASK; + gintc &= !GINTC_HWIC_MASK; // ← 准备写入 HWIC + gintc |= (mask << GINTC_HWIP_SHIFT) & GINTC_HWIP_MASK; + gintc |= (mask << GINTC_HWIC_SHIFT) & GINTC_HWIC_MASK; // ← HWIC=0xFF，清除所有 HWIS！ + write_gintc(gintc); +} +``` + +写入 HWIC 位会清除对应的 HWIS pending 位。当 HWIC=0xFF 时，所有 8 条 HWI 线的 pending 状态被一次性清除。 + +### 触发时序 + +``` + Guest 运行中 Host 处理 VM exit Guest 重新进入 + ────────────── ───────────────────── ───────────────── + 1. Timer 中断 ──→ 2. VM exit (timer) + 3. 处理 timer exit + (此时 guest IE=0) + 4. UART 中断到达 + → LVZ 拦截，记录在 + GINTC HWIS 中 + (pending) + 5. bind() → enable_guest_mode() + → gintc_set_hwi_passthrough(0xff) + → 写 GINTC，HWIC=0xFF + → HWIS pending 位被清除！ + 6. Guest 恢复运行 + 但 UART 中断已丢失 + Shell 阻塞在 UART I/O + → 进入 idle 循环 +``` + +步骤 5 是关键：每次 VM entry 都重置 GINTC，清除了步骤 4 中 pending 的 UART 中断。 + +### 为什么高频操作更容易触发 + +Timer VM exit 大约每 ~500μs 发生一次。UART 中断频率与 shell 输出成正比。 +命令越频繁，UART 中断越密集，在 timer VM exit 的处理窗口中 +命中"guest IE=0 且 UART 中断到达"的竞态窗口的概率越大。 +一旦某个 UART 中断被丢弃，guest 的串口驱动就会卡在等待中断唤醒的状态， +后续的 UART 中断也可能因为同样的竞态被反复丢弃。 + +## 证据 + +### 1. 心跳调试：vcpu 循环持续运行但 guest 卡在 idle + +在 vcpu loop 中加入每 500 次 VM exit 打印 guest 状态的心跳： + +``` +DBG heartbeat VM[1] VCpu[0] exit#14500 sepc=0x9000000000cbdd8c crmd=0xb4 + ectl=0x71c1d estat=0x800 era=0x9000000000cbdd8c +DBG heartbeat VM[1] VCpu[0] exit#15000 sepc=0x9000000000cbdd8c crmd=0xb4 + ectl=0x71c1d estat=0x800 era=0x9000000000cbdd8c +... +（冻结后心跳仍在输出，sepc/era 固定不变） +``` + +- `era=0x9000000000cbdd8c` = guest idle 循环地址（WFI/idle） +- `crmd=0xb4` = guest 中断已开启 (IE=1) +- `estat` 只有 timer 位 (0x800) 和 0 之间切换，**从未出现 HWI 位** +- 心跳持续输出 → vcpu 循环正常，问题在 guest 侧 + +### 2. GINTC 寄存器值确认 HWIS=0 + +修正 CSR 编号后读取 GINTC (CSR 0x52)： + +``` +DBG #500 gintc=0x0000ff00 est=0x800 ... (正常时) +DBG #4000 gintc=0x0000ff00 est=0x0 ... (卡住时) +``` + +- `gintc=0x0000ff00`：HWIP=0xFF（passthrough 全开），**HWIS=0x00**（无 pending HWI） +- 零 HWI VM exit — 从未出现非 timer 的 IRQ exit 日志 + +这说明 UART 中断在 EIOINTC/PCH-PIC 层面到达了，但在 GINTC 层面被丢弃。 + +### 3. 定期 HWI 注入可恢复 guest + +在 vcpu loop 中每 50 次 exit 注入一次 HWI2（UART 中断线）后： + +``` +[37] 00:00:36 ---------------------------------------- +ls +bin etc linuxrc root sys +[38] 00:00:37 ---------------------------------------- +pwd +/ +[39] 00:00:38 ---------------------------------------- +（命令正常响应，不再卡死） +``` + +通过 `pulse_hwi(2)` 向 guest 注入模拟的 UART 中断后，guest 恢复正常。 +这证实了 **guest 的中断处理逻辑本身没问题，问题在于中断信号在 GINTC 层面丢失**。 + +### 4. 禁用大页后问题消失（二次确认） + +该 bug 还与大页支持代码交互：大页 PTE 中 `LEVEL` 字段（bits[14:13]） +与 `PHYS_ADDR_MASK`（bits[47:12]）重叠，导致 `lddir`/`ldpte` 硬件页表遍历 +时物理地址被破坏。大页映射启用后 TLB refill 更频繁，放大了 GINTC 竞态窗口， +使卡死更快出现。但即使禁用大页，仅靠高频命令仍可触发，只是概率更低。 + +## 修复 + +### 修复 1：GINTC passthrough 只配置一次 + +将 `gintc_set_hwi_passthrough(0xff)` 从 `enable_guest_mode()` +（每次 VM entry 调用）移到 `init_hv()`（仅 vcpu setup 时调用一次）。 + +**文件**：`components/loongarch_vcpu/src/vcpu.rs` + +```rust +// init_hv() — 只调用一次 +fn init_hv(&mut self, config: LoongArchVCpuSetupConfig) { + self.init_vm_context(config); + #[cfg(target_arch = "loongarch64")] + unsafe { + crate::registers::gintc_set_hwi_passthrough(0xff); + } +} + +// enable_guest_mode() — 不再调用 gintc_set_hwi_passthrough +unsafe fn enable_guest_mode(&self) { + // ... 其他 GID/TGID/PGM/GCFG 配置 ... + // gintc_set_hwi_passthrough 已移除 + prmd::set_pie(true); +} +``` + +**文件**：`components/loongarch_vcpu/src/registers.rs` + +同时修复 `gintc_set_hwi_passthrough()` 本身，不再写入 HWIC 位： + +```rust +pub(crate) unsafe fn gintc_set_hwi_passthrough(mask: usize) { + let mut gintc = read_gintc(); + gintc &= !GINTC_HWIP_MASK; + // 不再写 HWIC：写 HWIC 会清除 HWIS pending 位 + gintc |= (mask << GINTC_HWIP_SHIFT) & GINTC_HWIP_MASK; + write_gintc(gintc); +} +``` + +### 修复 2：大页 PTE 不存储 LEVEL 到物理地址位域 + +**文件**：`components/page_table_multiarch/page_table_entry/src/arch/loongarch64.rs` +**文件**：`components/axaddrspace/src/npt/arch/loongarch64.rs` + +LoongArch 大页 PTE 只设置 `GH` 位标识大页，不存储 LEVEL 到内存 PTE 中。 +`lddir` 硬件遍历页表时根据当前遍历层级自动识别大页，无需软件在 PTE 中记录 level。 + +```rust +// 大页 PTE 只设 GH，不写 LEVEL +fn new_page_with_level(paddr: PhysAddr, flags: MappingFlags, level: usize) -> Self { + Self::new_page(paddr, flags, level > 0) // level > 0 时设 GH 位 +} +``` + +## 原理：LoongArch LVZ 中断路径 + +``` + 外设 (UART) → PCH-PIC → EIOINTC → CPU 中断控制器 → CPU + ↕ + GINTC (LVZ) + ↓ + HWIP 使能 → passthrough 直达 guest + HWIS 记录 pending 状态 + HWIC 写 1 清除 pending +``` + +在 passthrough 模式下（HWIP=0xFF），外部硬件中断不引起 VM exit， +直接注入 guest。但如果 timer 中断导致 VM exit（`gcfg_set_toti(false)`）， +则在 host 处理期间到达的 HWI 会被 LVZ 暂存到 GINTC HWIS 中。 +问题在于 host 在恢复 guest 前重写 GINTC 时把 HWIS 清掉了。 + +## 经验教训 + +1. **不要在每次 VM entry 时重写中断控制器配置**。静态配置（如 passthrough mask） + 只需初始化一次，重复写入会带来意外的副作用。 + +2. **GINTC 的 HWIC 是 write-to-clear 语义**。写 HWIC 位会清除对应的 HWIS pending 位， + 这是 LoongArch LVZ 架构的设计，但容易被忽视。 + +3. **调试方法**：通过心跳日志区分"vcpu 循环停止"和"vcpu 循环运行但 guest 卡死"， + 是定位虚拟化 bug 的关键第一步。前者指向 host/hypervisor 问题，后者指向 guest 侧问题。 + +4. **多个 bug 可以交互放大**：GINTC 丢失中断本身是一个低概率竞态， + 但大页映射引入的 TLB refill 异常增加了 VM exit 频率和内存映射错误， + 使卡死更容易复现。 diff --git a/os/axvisor/doc/loongarch/implementation-gaps-and-roadmap.md b/os/axvisor/doc/loongarch/implementation-gaps-and-roadmap.md new file mode 100644 index 0000000000..0d05d7aac2 --- /dev/null +++ b/os/axvisor/doc/loongarch/implementation-gaps-and-roadmap.md @@ -0,0 +1,148 @@ +# LoongArch 外部中断默认直通问题 + +LoongArch 当前在 `feature = "hypervisor"` 下，对 EIOINTC claim 出来的外部 IRQ 没有判断归属，而是默认认为外部 IRQ 都应该交给 guest interrupt controller。host 只完成物理中断控制器层面的 claim/complete，不执行设备级中断处理。 + +这意味着当前实现隐含了一个前提：**hypervisor 模式下所有 EIOINTC 外设中断都属于 guest**。这个前提只适合“外设全部直通给 guest，host 不拥有外设驱动”的 bring-up 场景；一旦 host 也需要处理某些设备，或存在多个 VM，这个模型就不够。 + +## 当前代码行为 + +外部中断进入 host 后，CPU 侧最初看到的是 EIOINTC 入口线： + +```rust +IrqType::Io +``` + +随后 host 调用： + +```rust +eiointc::claim_irq() +``` + +从 EIOINTC 读取真实外部 IRQ 号，并转换成： + +```rust +IrqType::Ex(ex_irq) +``` + +在非 hypervisor 模式下，host 会查自己的 handler table： + +```rust +if !IRQ_HANDLER_TABLE.handle(ex_irq) { + debug!("Unhandled IRQ {irq:?}"); +} +``` + +但在 hypervisor 模式下，host 不处理这个外部 IRQ： + +```rust +trace!("Leaving passthrough external IRQ {ex_irq} to guest interrupt controller"); +``` + +最后无论是否是 hypervisor 模式，host 都会执行： + +```rust +eiointc::complete_irq(ex_irq); +``` + +这里的 `complete_irq()` 只是告诉物理 EIOINTC：这次 claim 出来的 IRQ 已经完成控制器层面的处理，可以继续投递后续中断。它不表示 guest 已经处理完设备，也不表示设备中断源已经被清除。 + +## 问题本质 + +当前代码没有回答这个问题： + +```text +这个外部 IRQ 到底属于谁？ +``` + +它直接把所有 `IrqType::Ex(ex_irq)` 都当成 guest passthrough IRQ。 + +实际 hypervisor 里通常需要区分： + +```text +IRQ n -> host +IRQ n -> VM0 +IRQ n -> VM1 +IRQ n -> masked / reserved +``` + +如果没有 IRQ ownership/routing 表，就无法可靠支持： + +- host 自己使用串口、磁盘、网卡或管理设备； +- 多 VM 共享同一个物理中断控制器； +- 部分设备 emulation，部分设备 passthrough； +- legacy IRQ、MSI、timer、IPI 等不同中断来源的不同处理策略。 + +## 为什么当前暂时能工作 + +当前 LoongArch bring-up 场景主要依赖 passthrough interrupt： + +```rust +gintc_set_hwi_passthrough(0xff); +``` + +这表示 guest HWI 线被配置为 passthrough。对于“外设都给 guest”的单 VM 场景，host 看到外部 IRQ 后不做设备处理，只 complete 物理 EIOINTC，是可以解释得通的。 + +典型流程是： + +```text +外设触发 IRQ + -> EIOINTC 置 pending + -> host trap 到外部中断 + -> host claim 得到 ex_irq + -> host 不调用自己的 IRQ handler + -> guest interrupt controller / HWI passthrough 负责让 guest 看到中断 + -> host complete EIOINTC +``` + +这个流程依赖一个条件：这个 IRQ 的设备语义确实由 guest 负责处理。 + +## 风险 + +如果某个外部 IRQ 实际应该由 host 处理，当前代码会跳过 host handler，导致 host 永远不处理该设备中断。 + +如果未来支持多个 VM，当前代码也无法判断这个 IRQ 应该注入哪个 VM、哪个 vCPU。 + +如果设备是 level-triggered，host complete EIOINTC 时 guest 可能还没有清设备中断源。之后是否重新触发依赖硬件和中断控制器语义，需要单独验证。 + +如果设备是 edge-triggered 或 MSI，需要确认 host 过早 complete 是否存在事件丢失风险。 + +## 与其他架构的差异 + +RISC-V 当前也有类似简化，但代码里已经明确留下 TODO： + +```rust +// TODO: judge irq's ownership before handling (axvisor or any vm). +``` + +也就是说 RISC-V 当前也知道未来需要判断 IRQ 属于 axvisor 还是某个 VM。 + +AArch64 更偏向通过 passthrough SPI / vGIC 配置来描述 guest 拥有哪些中断，不是简单把所有外部 IRQ 都无条件视为 guest IRQ。 + +LoongArch 当前缺少类似的 ownership 判断，因此问题更集中地体现在 `IrqType::Ex(ex_irq)` 分支。 + +## 后续方向 + +需要引入 LoongArch IRQ ownership/routing 机制。外部 IRQ 处理应从： + +```text +所有 Ex IRQ 默认 guest +``` + +演进为： + +```text +claim physical IRQ + -> 查询 IRQ owner + -> owner 是 host：调用 IRQ_HANDLER_TABLE.handle(ex_irq) + -> owner 是 guest：注入 guest 或依赖 passthrough HWI + -> owner 不明确：mask 或 warn + -> 按控制器语义 complete physical IRQ +``` + +同时需要明确： + +- `complete_irq()` 与 guest 设备处理完成之间没有强同步关系； +- passthrough HWI 和 software injection 的适用边界； +- `Ex(ex_irq)` 到 guest vector/HWI 线的映射； +- 多 VM、多 vCPU 下 IRQ 注入目标； +- level-triggered、edge-triggered、MSI 的 complete/ack 时序。 diff --git a/os/axvisor/doc/loongarch/interrupt-wakeup.md b/os/axvisor/doc/loongarch/interrupt-wakeup.md new file mode 100644 index 0000000000..69e1b718c1 --- /dev/null +++ b/os/axvisor/doc/loongarch/interrupt-wakeup.md @@ -0,0 +1,125 @@ +# LoongArch Interrupt And Wakeup + +本文记录 LoongArch guest 外部中断注入与 vCPU 唤醒闭环的问题。IRQ injection 和 idle wakeup 需要放在一起看，因为 guest 等待设备或 timer 时，最终依赖的是同一条链路： + +```text +host receives timer / IPI / external IRQ + -> hypervisor marks or injects guest virtual interrupt + -> notify blocked vCPU task + -> vCPU resumes guest execution +``` + +## 当前状态 + +LoongArch 当前已经能处理部分 guest timer 和异常路径，但完整的事件驱动唤醒闭环尚未完成。 + +RISC-V 平台会注册 virtual IRQ injector： + +```rust +register_virtual_irq_injector(crate::hal::arch::inject_interrupt) +``` + +LoongArch 当前对应初始化仍为空： + +```rust +pub(super) fn init_platform_irq_injector() {} +``` + +同时，LoongArch guest `idle` 当前使用短轮询处理： + +```rust +AxVCpuExitReason::Idle => { + trace!("VM[{vm_id}] run VCpu[{vcpu_id}] Idle"); + super::timer::check_events(); + busy_wait(Duration::from_micros(50)); +} +``` + +这不是最终模型，而是 bring-up 阶段为了避免 guest 睡死的临时策略。 + +## 为什么 IRQ 和 idle 是同一个问题 + +标准虚拟化模型通常是： + +```text +guest idle/halt + -> vCPU task block + -> virtual timer / external interrupt / IPI arrives + -> hypervisor injects or marks virtual interrupt pending + -> notify blocked vCPU task + -> vCPU resumes guest execution +``` + +如果只有 IRQ injection，没有 notify blocked vCPU，guest 可能仍然睡着。 + +如果只有 idle wait，没有可靠 IRQ/timer notify，guest 可能在第一次 idle 后永久睡眠。 + +所以 LoongArch 后续需要补的是完整闭环，而不是单独补一个 IRQ handler 或单独改 `Idle` 分支。 + +## 当前短轮询的原因 + +如果把 `Idle` 直接改成： + +```rust +wait(vm_id) +``` + +vCPU task 会进入 wait queue。当前 LoongArch 还没有完整实现： + +```text +timer / IRQ arrives + -> inject virtual interrupt + -> notify target vCPU +``` + +因此 guest 可能在 idle 后无法醒来。 + +当前短轮询路径是： + +```text +Idle exit + -> check pending VMM timer events + -> busy wait 50us + -> re-enter guest +``` + +它能降低 guest idle loop 高频 VM exit 的开销，同时避免唤醒链路不完整导致 vCPU 睡死。 + +## 需要明确的中断语义 + +LoongArch 平台中断在 hypervisor 场景下需要明确： + +- 哪些中断由 host Axvisor 消费； +- 哪些中断应该交给 guest； +- claim/complete 的时机由 host 负责还是 guest 负责； +- PCH PIC、EIOINTC、PCI legacy IRQ/MSI 如何映射到 guest interrupt； +- pending interrupt 如何唤醒 blocked vCPU。 + +这些语义会影响： + +- guest timer； +- virtio-blk I/O 完成中断； +- PCI passthrough interrupt； +- guest idle 后等待设备中断； +- 多 vCPU IPI 或跨 CPU wakeup。 + +## 当前限制 + +- `busy_wait(Duration::from_micros(50))` 仍会消耗 host CPU。 +- 50us 是经验值，不是根据最近 timer deadline 动态计算。 +- `notify_vcpu_timer_expired()` 当前仍未实现。 +- LoongArch `init_platform_irq_injector()` 当前为空。 +- 外部中断到 guest virtual interrupt pending 的平台闭环尚未完成。 +- 中断注入后唤醒 blocked vCPU 的闭环尚未完成。 + +## 后续工作 + +1. 实现 LoongArch `init_platform_irq_injector()`。 +2. 明确 host IRQ handler 中 passthrough IRQ 的 claim/complete 策略。 +3. 实现外部 IRQ 到 `vcpu.inject_interrupt()` 或架构 pending interrupt 的路径。 +4. 为 VMM timer 增加查询最近 deadline 的接口。 +5. 实现 `notify_vcpu_timer_expired(vm_id, vcpu_id)`。 +6. timer、IPI、外部设备中断注入后通知目标 vCPU。 +7. 在 `Idle` 分支中先检查 pending virtual interrupt。 +8. 唤醒链路稳定后，把短轮询改成事件驱动 wait。 +9. 用 virtio-blk I/O 完成中断验证整条链路。 diff --git a/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md b/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md new file mode 100644 index 0000000000..18c99fdd34 --- /dev/null +++ b/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md @@ -0,0 +1,122 @@ +# LoongArch Linux Direct Boot + +本文只记录 LoongArch Linux direct boot 问题：Axvisor 不经过 guest UEFI/bootloader，直接把 Linux kernel、cmdline、DTB/initrd 信息放到 guest 可见的位置，然后跳到 Linux entry。 + +## 这个文件是什么 + +`linux-direct-boot-analysis.md` 用来说明 LoongArch Linux 的启动协议和 Axvisor 当前怎么模拟该启动环境。 + +它不跟踪 virtio-blk rootfs、IRQ 注入、idle 唤醒或 stage-2 TLB refill。这些问题分别放在独立文档中。 + +## 当前启动链路 + +当前 LoongArch Linux quick-start 的 direct boot 链路是： + +```text +VM TOML + -> ImageLoader 加载 LoongArch ELF kernel + -> 加载 DTB 和 initramfs + -> setup_bootinfo 构造 LoongArch Linux bootinfo + -> 设置 guest boot_args + -> vCPU 进入 Linux entry +``` + +关键代码位置： + +- `os/axvisor/src/vmm/images/mod.rs` +- `components/loongarch_vcpu/src/vcpu.rs` +- `components/axvm/src/config.rs` +- `components/axvm/src/vm.rs` + +## Kernel 格式 + +LoongArch loader 当前先尝试 ELF： + +```rust +loongarch_elf::try_load(...) +``` + +如果是 LoongArch ELF，就按 `PT_LOAD` segment 加载，并用 ELF entry 更新： + +```rust +config.cpu_config.bsp_entry = info.entry; +config.cpu_config.ap_entry = info.entry; +``` + +如果不是 ELF，则 fallback 为 raw image，按 `kernel_load_gpa` 直接拷贝。 + +当前 quick-start 使用的是 LoongArch ELF kernel。 + +## Boot 参数 + +LoongArch Linux 当前通过 boot args 接收 direct boot 信息： + +```text +a0 = 1 +a1 = cmdline GPA +a2 = EFI system table GPA +``` + +Axvisor 中对应设置为： + +```rust +config.cpu_config.boot_args = [1, CMDLINE_GPA, SYSTAB_GPA]; +``` + +其中 `setup_bootinfo()` 会构造： + +- cmdline buffer； +- EFI vendor string； +- EFI system table； +- EFI config table； +- EFI memory map； +- initrd table； +- optional DTB pointer。 + +## Cmdline 原则 + +`kernel.cmdline` 必须来自 VM 配置文件。loader 不应该自动生成或追加 `console=`、`root=`、`init=` 等参数。 + +当前原则： + +- `kernel.cmdline` 缺失时直接报错； +- 缺少 `console=` 只 warning； +- 缺少 `init=` / `rdinit=` 只 warning； +- rootfs 方式由配置决定。 + +这样可以确保使用者能从配置文件明确知道 guest 是如何启动的。 + +## 与 ARM/RISC-V 的区别 + +AArch64 Linux direct boot 通常是： + +```text +x0 = DTB physical address +entry = raw Image entry +``` + +RISC-V Linux direct boot 通常是： + +```text +a0 = hart id +a1 = DTB physical address +entry = raw Image entry +``` + +LoongArch 这里不是简单传一个 DTB 地址，而是需要模拟 EFI-style bootinfo： + +```text +a0 = efi_boot flag +a1 = cmdline +a2 = EFI system table +``` + +因此不能直接复用 ARM 的 raw Image + `x0=dtb` 方法。 + +## 需要继续确认 + +1. EFI memory map 的 memory type 是否足够准确。 +2. DTB config table GUID 和 Linux LoongArch 实际读取路径是否完全匹配。 +3. 多内存段、多 vCPU、较大 initrd 时 bootinfo 边界是否正确。 +4. raw image fallback 是否需要更严格校验 entry/load address。 +5. `kernel.cmdline` 缺失时报错是否覆盖所有 direct boot 入口。 diff --git a/os/axvisor/doc/loongarch/rootfs-virtio-blk.md b/os/axvisor/doc/loongarch/rootfs-virtio-blk.md new file mode 100644 index 0000000000..5b296363c4 --- /dev/null +++ b/os/axvisor/doc/loongarch/rootfs-virtio-blk.md @@ -0,0 +1,75 @@ +# LoongArch Rootfs And Virtio Block + +本文只记录 LoongArch Linux guest rootfs 方式，以及为什么当前 quick-start 先使用 initramfs 而不是 virtio-blk 磁盘 rootfs。 + +## 当前方式 + +当前 LoongArch Linux quick-start 使用 ramdisk/initramfs 作为 guest rootfs： + +```toml +ramdisk_path = "/guest/linux/initramfs.cpio.gz" +ramdisk_load_addr = 0x0700_0000 +cmdline = "root=/dev/ram rw console=ttyS0 ... init=/init ... pci=off ..." +``` + +启动路径是： + +```text +Axvisor 加载 initramfs 到 guest 内存 + -> LoongArch bootinfo 传递 initrd base/size + -> Linux 解包内存中的 initramfs + -> 执行 /init +``` + +这条路径不依赖 guest 块设备。 + +## 磁盘 rootfs 需要的链路 + +如果改成磁盘 rootfs，典型 cmdline 是： + +```text +root=/dev/vda rw console=ttyS0 +``` + +guest 需要走完整设备链路： + +```text +Linux virtio-blk driver + -> PCI/virtio device discovery + -> virtqueue setup + -> disk I/O + -> device interrupt + -> hypervisor injects guest IRQ + -> guest handles completion + -> mount /dev/vda +``` + +当前 LoongArch quick-start 没有把这条链路作为可靠启动路径。 + +## 当前绕开的内容 + +使用 initramfs 主要绕开： + +- guest PCI 枚举； +- virtio-blk device discovery； +- virtqueue I/O； +- virtio-blk 完成中断； +- 外部设备中断注入 guest； +- guest idle 后等待设备中断唤醒。 + +QEMU runtime 配置里可以挂载： + +```toml +"virtio-blk-pci,drive=disk0" +``` + +但当前 guest cmdline 使用 `root=/dev/ram` 并带有 `pci=off`，因此 Linux guest 启动 rootfs 时不会依赖 `/dev/vda`。 + +## 后续工作 + +1. 去掉 `pci=off`，确认 guest 能枚举 PCI host bridge。 +2. 确认 virtio-blk 设备能在 guest 中出现为 `/dev/vda`。 +3. 使用只读 rootfs 验证基本读 I/O。 +4. 验证 legacy IRQ/MSI 的注入和完成路径。 +5. 确认 guest idle 时，virtio-blk 完成中断能唤醒 vCPU。 +6. 将 cmdline 切换到 `root=/dev/vda rw`。 diff --git a/os/axvisor/doc/loongarch/stage2-tlb-refill.md b/os/axvisor/doc/loongarch/stage2-tlb-refill.md new file mode 100644 index 0000000000..82aea6da0a --- /dev/null +++ b/os/axvisor/doc/loongarch/stage2-tlb-refill.md @@ -0,0 +1,37 @@ +# LoongArch Stage-2 TLB Refill + +本文只记录 LoongArch stage-2 映射和 TLB refill 的特殊处理。 + +## 当前实现 + +通用 nested page fault 路径会先补二阶段页表映射。大多数架构在页表更新后，可以依赖硬件下一次访问重新 page walk。 + +LoongArch 当前额外实现了架构 hook： + +```rust +self.fill_stage2_tlb(gpa, hpa, access_flags); +Ok(true) +``` + +也就是在 nested page fault 已经解析出 `gpa -> hpa` 后，主动填充 LoongArch stage-2 TLB/refill 相关项。 + +## 为什么需要 + +当前 LoongArch LVZ/stage2 路径不能完全依赖“更新二阶段页表后硬件自动重新 page walk”这个假设。某些缺页路径上，如果只更新 `address_space` 里的二阶段页表，guest 再次进入后仍可能继续触发 TLB refill 或转换异常。 + +因此 LoongArch 需要在 VM exit 处理后主动补一条 stage-2 TLB entry，让 guest 能继续访问。 + +## 与其他架构区别 + +- x86 EPT：通常由硬件 EPT walker 根据更新后的 EPT 继续翻译。 +- ARM Stage-2：通常由硬件 stage-2 walker 继续翻译。 +- RISC-V G-stage：通常由硬件 G-stage walker 继续翻译。 +- LoongArch：当前实现需要在部分路径上手动填充 stage-2 TLB/refill 项。 + +## 后续工作 + +1. 确认 READ/WRITE/EXECUTE 权限都能正确填充。 +2. 确认 huge page level 软件标记位不会污染物理地址。 +3. 确认 guest direct-map VA 到 GPA 的转换覆盖 Linux 常见地址区间。 +4. 确认映射权限变化或解除映射时是否需要失效旧 TLB 项。 +5. 用 Linux boot、initramfs 访问、用户态执行、设备 MMIO 访问分别验证。 diff --git a/os/axvisor/scripts/quick-start.sh b/os/axvisor/scripts/quick-start.sh index 07b1e66b77..0b6d9f48cb 100755 --- a/os/axvisor/scripts/quick-start.sh +++ b/os/axvisor/scripts/quick-start.sh @@ -95,6 +95,7 @@ Launch Options (for run/start commands): -a, --arceos Launch single ArceOS guest (default) QEMU LoongArch64: --axvisor Launch AxVisor shell smoke (default) + -l, --linux Launch single Linux guest QEMU x86_64: -n, --nimbos Launch single NimbOS guest (default) -l, --linux Launch single Linux guest @@ -125,6 +126,7 @@ Examples: # QEMU LoongArch64 $0 qemu-loongarch64 start --axvisor # One-step: prepare + launch AxVisor shell + $0 qemu-loongarch64 start --linux # One-step: prepare + launch Linux $0 qemu-loongarch64 start # Same as above (default axvisor) # QEMU x86_64 @@ -164,11 +166,19 @@ EOF } run_axvisor_qemu() { - run_cmd cargo xtask qemu "$@" + local axvisor_dir + local workspace_root + axvisor_dir="$(pwd)" + workspace_root="$(cd ../.. && pwd)" + run_cmd bash -c 'cd "$1" && shift && cargo xtask axvisor qemu "$@"' _ "$workspace_root" "$@" } run_axvisor_uboot() { - run_cmd cargo xtask uboot "$@" + local axvisor_dir + local workspace_root + axvisor_dir="$(pwd)" + workspace_root="$(cd ../.. && pwd)" + run_cmd bash -c 'cd "$1" && shift && cargo xtask axvisor uboot "$@"' _ "$workspace_root" "$@" } ensure_ostool() { @@ -289,16 +299,47 @@ run_qemu_riscv64_arceos() { setup_qemu_loongarch64() { info "=== QEMU LoongArch64 Preparation ===" - run_cmd mkdir -p tmp/configs + run_cmd mkdir -p tmp/{configs,images/qemu_loongarch64_linux} info "Preparing board config file..." run_cmd cp configs/board/qemu-loongarch64.toml tmp/configs/ + info "Preparing Linux guest config file..." + run_cmd cp configs/vms/linux-loongarch64-qemu-smp1.toml tmp/configs/ + run_cmd cp configs/vms/linux-loongarch64-qemu-smp1.dts tmp/configs/ + + local guest_dir="${AXVISOR_LOONGARCH64_GUEST_DIR:-$(cd ../../.. && pwd)/axvisor-guest/IMAGES/qemu/loongarch64/linux}" + if [ -f "$guest_dir/qemu-loongarch64" ] && [ -f "$guest_dir/initramfs.cpio.gz" ]; then + info "Using LoongArch Linux guest artifacts from: $guest_dir" + run_cmd cp "$guest_dir/qemu-loongarch64" tmp/images/qemu_loongarch64_linux/ + run_cmd cp "$guest_dir/initramfs.cpio.gz" tmp/images/qemu_loongarch64_linux/ + if [ -f "$guest_dir/rootfs.img" ]; then + run_cmd cp "$guest_dir/rootfs.img" tmp/images/qemu_loongarch64_linux/ + fi + else + warn "LoongArch Linux guest artifacts not found in: $guest_dir" + warn "Build them first in axvisor-guest, or set AXVISOR_LOONGARCH64_GUEST_DIR." + fi + + if ! command -v dtc &> /dev/null; then + error "dtc is required to build linux-loongarch64-qemu-smp1.dtb" + exit 1 + fi + run_cmd dtc -I dts -O dtb -o tmp/configs/linux-loongarch64-qemu-smp1.dtb tmp/configs/linux-loongarch64-qemu-smp1.dts + run_cmd cp tmp/configs/linux-loongarch64-qemu-smp1.dtb tmp/images/qemu_loongarch64_linux/ + + run_cmd sed -i 's|^image_location = "fs"|image_location = "memory"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml + run_cmd sed -i 's|^kernel_path = .*|kernel_path = "../images/qemu_loongarch64_linux/qemu-loongarch64"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml + run_cmd sed -i 's|^dtb_path = .*|dtb_path = "linux-loongarch64-qemu-smp1.dtb"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml + run_cmd sed -i 's|^ramdisk_path = .*|ramdisk_path = "../images/qemu_loongarch64_linux/initramfs.cpio.gz"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml + info "Preparing QEMU config file..." run_cmd cp configs/qemu/qemu-loongarch64.toml tmp/configs/qemu-loongarch64-runtime.toml if [[ -n "${AXBUILD_QEMU_SYSTEM_LOONGARCH64:-}" ]]; then info "Using explicit LoongArch QEMU override: ${AXBUILD_QEMU_SYSTEM_LOONGARCH64}" + elif [[ -x "$HOME/qemu-lvz-ci-install/bin/qemu-system-loongarch64" ]]; then + info "Detected CI-pinned QEMU-LVZ at $HOME/qemu-lvz-ci-install/bin/qemu-system-loongarch64" elif [[ -x "$HOME/QEMU-LVZ/build/qemu-system-loongarch64" ]]; then info "Detected QEMU-LVZ at $HOME/QEMU-LVZ/build/qemu-system-loongarch64" elif [[ -x "$HOME/qemu-lvz/build/qemu-system-loongarch64" ]]; then @@ -319,6 +360,60 @@ run_qemu_loongarch64_axvisor() { --qemu-config "$(pwd)/tmp/configs/qemu-loongarch64-runtime.toml" } +loongarch64_qemu_binary() { + if [[ -n "${AXBUILD_QEMU_SYSTEM_LOONGARCH64:-}" ]]; then + printf '%s\n' "${AXBUILD_QEMU_SYSTEM_LOONGARCH64}" + elif [[ -x "$HOME/qemu-lvz-ci-install/bin/qemu-system-loongarch64" ]]; then + printf '%s\n' "$HOME/qemu-lvz-ci-install/bin/qemu-system-loongarch64" + elif [[ -x "$HOME/QEMU-LVZ/build/qemu-system-loongarch64" ]]; then + printf '%s\n' "$HOME/QEMU-LVZ/build/qemu-system-loongarch64" + elif [[ -x "$HOME/qemu-lvz/build/qemu-system-loongarch64" ]]; then + printf '%s\n' "$HOME/qemu-lvz/build/qemu-system-loongarch64" + else + return 1 + fi +} + +run_axvisor_qemu_with_loongarch64_qemu() { + local qemu_bin + local qemu_dir + qemu_bin="$(loongarch64_qemu_binary)" || { + error "QEMU-LVZ qemu-system-loongarch64 not found. Set AXBUILD_QEMU_SYSTEM_LOONGARCH64 or install QEMU-LVZ." + exit 1 + } + qemu_dir="$(dirname "$qemu_bin")" + info "Using LoongArch QEMU: $qemu_bin" + PATH="$qemu_dir:$PATH" run_axvisor_qemu "$@" +} + +ensure_loongarch64_host_rootfs() { + local workspace_root="$1" + local rootfs="$workspace_root/tmp/axbuild/rootfs/rootfs-loongarch64-alpine.img" + if [[ -f "$rootfs" ]]; then + return 0 + fi + + info "Creating minimal AxVisor host rootfs: $rootfs" + run_cmd mkdir -p "$(dirname "$rootfs")" + run_cmd dd if=/dev/zero of="$rootfs" bs=1M count=1024 status=none + run_cmd mkfs.ext4 -q -F "$rootfs" +} + +run_qemu_loongarch64_linux() { + info "=== Launching QEMU LoongArch64 Linux Guest ===" + setup_qemu_loongarch64 + + local workspace_root + workspace_root="$(cd ../.. && pwd)" + + ensure_loongarch64_host_rootfs "$workspace_root" + + run_axvisor_qemu_with_loongarch64_qemu \ + --config "$(pwd)/tmp/configs/qemu-loongarch64.toml" \ + --qemu-config "$(pwd)/tmp/configs/qemu-loongarch64-runtime.toml" \ + --vmconfigs "$(pwd)/tmp/configs/linux-loongarch64-qemu-smp1.toml" +} + # ============================================================================ # QEMU x86_64 Architecture Setup # ============================================================================ @@ -1003,14 +1098,7 @@ cmd_run_qemu_loongarch64() { run_qemu_loongarch64_axvisor ;; -l|--linux) - error "Unsupported combination: QEMU LoongArch64 quick start does not launch a Linux guest yet" - echo "" - echo "QEMU LoongArch64 quick start currently supports the following mode:" - echo " - AxVisor shell smoke (use --axvisor)" - echo "" - echo "To launch a Linux guest, please use:" - echo " $0 qemu-aarch64 start --linux" - exit 1 + run_qemu_loongarch64_linux ;; -a|--arceos) error "Unsupported combination: QEMU LoongArch64 quick start does not launch an ArceOS guest yet" @@ -1042,6 +1130,7 @@ cmd_run_qemu_loongarch64() { echo "" echo "QEMU LoongArch64 platform supports the following options:" echo " --axvisor Launch AxVisor shell smoke" + echo " -l, --linux Launch Linux guest" exit 1 ;; esac @@ -1050,7 +1139,7 @@ cmd_run_qemu_loongarch64() { cmd_start_qemu_loongarch64() { local mode="$1" case "$mode" in - --axvisor|"") + --axvisor|-l|--linux|"") ;; *) cmd_run_qemu_loongarch64 "$mode" diff --git a/os/axvisor/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json b/os/axvisor/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json new file mode 120000 index 0000000000..8df5a0686a --- /dev/null +++ b/os/axvisor/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json @@ -0,0 +1 @@ +/home/szy/work/hypervisor/uefi/no_uefi/tgoskits_glm/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json \ No newline at end of file diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index 16e51cb2ee..448a67e30c 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -29,7 +29,11 @@ use ax_errno::{AxResult, ax_err_type}; use ax_kspin::SpinNoIrq as Mutex; use ax_lazyinit::LazyInit; // pub use print::print_fdt; -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "loongarch64", + target_arch = "riscv64" +))] pub use create::update_fdt; pub use device::build_all_node_paths; use fdt_parser::Fdt; diff --git a/os/axvisor/src/fdt/vm_fdt/writer.rs b/os/axvisor/src/fdt/vm_fdt/writer.rs index d17fd04d0d..61bed82063 100644 --- a/os/axvisor/src/fdt/vm_fdt/writer.rs +++ b/os/axvisor/src/fdt/vm_fdt/writer.rs @@ -438,7 +438,12 @@ impl FdtWriter { } /// Write a string property. - #[cfg(any(target_arch = "aarch64", target_arch = "riscv64", test))] + #[cfg(any( + target_arch = "aarch64", + target_arch = "loongarch64", + target_arch = "riscv64", + test + ))] pub fn property_string(&mut self, name: &str, val: &str) -> Result<()> { let cstr_value = CString::new(val).map_err(|_| Error::InvalidString)?; self.property(name, cstr_value.to_bytes_with_nul()) @@ -468,7 +473,12 @@ impl FdtWriter { } /// Write a property containing an array of 32-bit unsigned integers. - #[cfg(any(target_arch = "aarch64", target_arch = "riscv64", test))] + #[cfg(any( + target_arch = "aarch64", + target_arch = "loongarch64", + target_arch = "riscv64", + test + ))] pub fn property_array_u32(&mut self, name: &str, cells: &[u32]) -> Result<()> { let mut arr = Vec::with_capacity(size_of_val(cells)); for &c in cells { diff --git a/platforms/ax-plat-loongarch64-qemu-virt/Cargo.toml b/platforms/ax-plat-loongarch64-qemu-virt/Cargo.toml index eae34e9611..eabe83ed44 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/Cargo.toml +++ b/platforms/ax-plat-loongarch64-qemu-virt/Cargo.toml @@ -11,6 +11,7 @@ license = "Apache-2.0" [features] fp-simd = ["ax-cpu/fp-simd"] +hypervisor = ["irq", "smp"] irq = ["ax-plat/irq"] paging = [] rtc = ["dep:chrono"] diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/console.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/console.rs index 3347c717e2..cac655416e 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/console.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/console.rs @@ -12,7 +12,7 @@ use crate::config::{devices::UART_PADDR, plat::PHYS_VIRT_OFFSET}; static UART: LazyInit>> = LazyInit::new(); const CSR_GSTAT: u16 = 0x50; -const GSTAT_PGM: usize = 1 << 1; +const GSTAT_PVM: usize = 1 << 1; fn uart_config(input_irq_enabled: bool) -> Config { Config { @@ -31,7 +31,7 @@ fn in_guest_mode() -> bool { unsafe { core::arch::asm!("csrrd {}, {}", out(reg) gstat, const CSR_GSTAT); } - (gstat & GSTAT_PGM) != 0 + (gstat & GSTAT_PVM) != 0 } pub(crate) fn init_early() { diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs index 26d2c9a11f..5e3bad9630 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs @@ -78,6 +78,10 @@ pub fn claim_irq() -> Option { } None } +/// Write back the ISR bit to acknowledge (clear) the interrupt. +/// Must be called after claim_irq() to allow the EIOINTC to deliver +/// subsequent interrupts. Required in both native and hypervisor +/// modes. pub fn complete_irq(irq: usize) { let (offset, bit) = split_bit(irq); iocsr_write_d(EIOINTC_REG_ISR + offset, bit); diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/lib.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/lib.rs index 5487f3d547..dc058cf3f9 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/lib.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/lib.rs @@ -28,8 +28,10 @@ mod boot; mod console; mod drivers; mod init; -#[cfg(feature = "irq")] +#[cfg(all(feature = "irq", not(feature = "hypervisor")))] mod irq; +#[cfg(feature = "hypervisor")] +pub mod irq; mod mem; #[cfg(feature = "smp")] mod mp; diff --git a/scripts/axbuild/src/context/mod.rs b/scripts/axbuild/src/context/mod.rs index a1959ed55f..965ed6223d 100644 --- a/scripts/axbuild/src/context/mod.rs +++ b/scripts/axbuild/src/context/mod.rs @@ -22,6 +22,8 @@ use ostool::{ }, }; +use crate::support::process::ProcessExt; + mod arch; mod resolve; mod snapshot; @@ -182,6 +184,7 @@ impl AppContext { qemu, debug: self.debug, dtb_dump: false, + show_output: true, })), ) .await; @@ -554,13 +557,21 @@ fn loongarch_qemu_dir_candidates(workspace_root: &Path) -> Vec { let mut candidates = Vec::new(); if let Some(home) = env::var_os("HOME").map(PathBuf::from) { - for suffix in ["QEMU-LVZ/build", "qemu-lvz/build"] { + for suffix in [ + "qemu-lvz-ci-install/bin", + "QEMU-LVZ/build", + "qemu-lvz/build", + ] { candidates.push(home.join(suffix)); } } for ancestor in workspace_root.ancestors() { - for suffix in ["QEMU-LVZ/build", "qemu-lvz/build"] { + for suffix in [ + "qemu-lvz-ci-install/bin", + "QEMU-LVZ/build", + "qemu-lvz/build", + ] { candidates.push(ancestor.join(suffix)); } } diff --git a/scripts/axbuild/src/context/tests/arceos.rs b/scripts/axbuild/src/context/tests/arceos.rs index 6a5e5621b4..f7f1cde494 100644 --- a/scripts/axbuild/src/context/tests/arceos.rs +++ b/scripts/axbuild/src/context/tests/arceos.rs @@ -240,6 +240,26 @@ fn find_loongarch_qemu_dir_checks_home_before_workspace_ancestors() { ); } +#[test] +fn find_loongarch_qemu_dir_prefers_ci_pinned_home_install() { + let _lock = ENV_LOCK.lock().unwrap(); + let home = tempdir().unwrap(); + let root = tempdir().unwrap(); + let ci_qemu_dir = home.path().join("qemu-lvz-ci-install/bin"); + let legacy_qemu_dir = home.path().join("QEMU-LVZ/build"); + + fs::create_dir_all(&ci_qemu_dir).unwrap(); + fs::create_dir_all(&legacy_qemu_dir).unwrap(); + fs::write(ci_qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); + fs::write(legacy_qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); + + let _qemu_dir = TempEnvVar::unset("AXBUILD_QEMU_DIR"); + let _qemu_bin = TempEnvVar::unset("AXBUILD_QEMU_SYSTEM_LOONGARCH64"); + let _home = TempEnvVar::set("HOME", home.path()); + + assert_eq!(find_loongarch_qemu_dir(root.path()), Some(ci_qemu_dir)); +} + #[test] fn prepare_request_cli_target_drops_stale_arceos_runtime_paths() { let root = tempdir().unwrap(); diff --git a/virtualization/axvcpu/src/exit.rs b/virtualization/axvcpu/src/exit.rs index 18d9f6adba..3014a8f4d5 100644 --- a/virtualization/axvcpu/src/exit.rs +++ b/virtualization/axvcpu/src/exit.rs @@ -180,12 +180,49 @@ pub enum AxVCpuExitReason { access_flags: MappingFlags, }, + /// A guest memory access needs to be completed by the VM layer. + /// + /// Some architecture-specific instructions can trap before the guest has + /// installed its own exception vectors. The VCPU decodes the instruction, + /// while the VM owns the stage-2 address space needed to perform the access. + GuestMemoryRead { + /// Guest physical address being read from. + addr: GuestPhysAddr, + /// Width/size of the memory access. + width: AccessWidth, + /// Index of the guest register that will receive the read value. + reg: usize, + /// Whether to sign-extend the read value to fill the register. + signed_ext: bool, + }, + + /// A guest memory write needs to be completed by the VM layer. + GuestMemoryWrite { + /// Guest physical address being written to. + addr: GuestPhysAddr, + /// Width/size of the memory access. + width: AccessWidth, + /// Data being written to the memory location. + data: u64, + }, + + /// The VCPU needs the VM layer to fetch a guest instruction before it can + /// complete architecture-specific instruction emulation. + GuestInstructionFetch { + /// Guest physical address of the instruction. + addr: GuestPhysAddr, + }, + /// The guest VCpu has executed a halt instruction and is now idle. /// /// This typically occurs when the guest OS has no work to do and is /// waiting for interrupts or other events to wake it up. Halt, + /// The guest VCpu reached an idle instruction that should yield host time + /// without blocking the vCPU task indefinitely. + Idle, + /// Request to bring up a secondary CPU core. /// /// This exit reason is used during the multi-core VM boot process when diff --git a/virtualization/axvcpu/src/vcpu.rs b/virtualization/axvcpu/src/vcpu.rs index 70e92e9e13..c1a5843acb 100644 --- a/virtualization/axvcpu/src/vcpu.rs +++ b/virtualization/axvcpu/src/vcpu.rs @@ -328,6 +328,30 @@ impl AxVCpu { pub fn set_return_value(&self, val: usize) { self.get_arch_vcpu().set_return_value(val); } + + /// Handles an already-resolved nested page mapping in architecture-specific hardware state. + pub fn handle_nested_page_mapping( + &self, + gpa: GuestPhysAddr, + hpa: HostPhysAddr, + access_flags: axaddrspace::MappingFlags, + page_size: ax_page_table_multiarch::PageSize, + pair_mapping: Option<(HostPhysAddr, axaddrspace::MappingFlags)>, + ) -> AxResult { + self.get_arch_vcpu().handle_nested_page_mapping( + gpa, + hpa, + access_flags, + page_size, + pair_mapping, + ) + } + + /// Completes architecture-specific instruction emulation after fetching + /// the instruction bytes from guest memory. + pub fn handle_fetched_guest_instruction(&self, ins: u32) -> AxResult> { + self.get_arch_vcpu().handle_fetched_guest_instruction(ins) + } } #[ax_percpu::def_percpu] diff --git a/virtualization/loongarch_vcpu/src/context_frame.rs b/virtualization/loongarch_vcpu/src/context_frame.rs index 011d0c78c6..6e4898afb5 100644 --- a/virtualization/loongarch_vcpu/src/context_frame.rs +++ b/virtualization/loongarch_vcpu/src/context_frame.rs @@ -111,6 +111,10 @@ pub struct LoongArchContextFrame { pub host_badi: usize, pub host_tlbrbadv: usize, pub host_tlbrera: usize, + pub guest_pc: usize, + pub entry_host_era: usize, + pub entry_guest_era: usize, + pub entry_gstat: usize, } impl LoongArchContextFrame { @@ -122,6 +126,10 @@ impl LoongArchContextFrame { self.x[5] = val; } + pub fn set_a2(&mut self, val: usize) { + self.x[6] = val; + } + pub fn set_gpr(&mut self, index: usize, val: usize) { match index { 0 => {} @@ -212,6 +220,10 @@ impl fmt::Display for LoongArchContextFrame { writeln!(f, "host_badv: {:016x}", self.host_badv)?; writeln!(f, "host_badi: {:016x}", self.host_badi)?; writeln!(f, "host_tlbrbadv: {:016x}", self.host_tlbrbadv)?; - write!(f, "host_tlbrera: {:016x}", self.host_tlbrera) + writeln!(f, "host_tlbrera: {:016x}", self.host_tlbrera)?; + writeln!(f, "guest_pc: {:016x}", self.guest_pc)?; + writeln!(f, "entry_host_era: {:016x}", self.entry_host_era)?; + writeln!(f, "entry_guest_era: {:016x}", self.entry_guest_era)?; + write!(f, "entry_gstat: {:016x}", self.entry_gstat) } } diff --git a/virtualization/loongarch_vcpu/src/exception.S b/virtualization/loongarch_vcpu/src/exception.S index 7956894d7c..45d5e6ddc2 100644 --- a/virtualization/loongarch_vcpu/src/exception.S +++ b/virtualization/loongarch_vcpu/src/exception.S @@ -1,10 +1,32 @@ .section .text +.equ CSR_GSTAT, 0x50 +.equ CSR_GTLBC, 0x15 +.equ CSR_CRMD, 0x0 +.equ CSR_PRMD, 0x1 +.equ CSR_ECFG, 0x4 +.equ CSR_SAVE0, 0x30 +.equ CSR_SAVE1, 0x31 +.equ CSR_PGD, 0x1b +.equ CSR_TLBRERA, 0x8a +.equ CSR_TLBRSAVE, 0x8b +.equ CSR_TLBRELO0, 0x8c +.equ CSR_TLBRELO1, 0x8d +.equ CSR_TLBREHI, 0x8e +.equ CSR_TLBRPRMD, 0x8f +.equ CSR_GSTAT_PVM, 0x2 +.equ CSR_PRMD_PIE, 0x4 +.equ CSR_TLBRPRMD_PGM, 0x8 +.equ CSR_GTLBC_TGID, 0xff0000 +.equ CSR_GTLBC_TGID0, 0x0 +.equ CSR_TIMER_IE, 0x800 +.equ CSR_CRMD_IE, 0x4 + .macro SAVE_GUEST_REGS st.d $r0, $sp, 0 st.d $r1, $sp, 8 st.d $r2, $sp, 16 - csrrd $t0, 0x502 + csrrd $t0, CSR_SAVE0 st.d $t0, $sp, 24 st.d $r4, $sp, 32 st.d $r5, $sp, 40 @@ -14,7 +36,8 @@ st.d $r9, $sp, 72 st.d $r10, $sp, 80 st.d $r11, $sp, 88 - st.d $r12, $sp, 96 + csrrd $t0, CSR_TLBRSAVE + st.d $t0, $sp, 96 st.d $r13, $sp, 104 st.d $r14, $sp, 112 st.d $r15, $sp, 120 @@ -172,9 +195,51 @@ st.d $t0, $sp, 784 .endm +.macro ENTER_HOST_MODE + li.d $t0, CSR_GSTAT_PVM + csrxchg $zero, $t0, CSR_GSTAT + csrrd $t1, CSR_TLBRPRMD + li.d $t0, -9 + and $t1, $t1, $t0 + csrwr $t1, CSR_TLBRPRMD + csrrd $t1, CSR_GTLBC + li.d $t0, CSR_GTLBC_TGID + andn $t1, $t1, $t0 + csrwr $t1, CSR_GTLBC +.endm + +.macro DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 + csrwr $t1, CSR_SAVE1 + csrrd $t0, CSR_ECFG + li.d $t1, CSR_TIMER_IE + andn $t0, $t0, $t1 + csrwr $t0, CSR_ECFG + csrrd $t1, CSR_SAVE1 +.endm + +.macro PREPARE_GUEST_ENTRY + li.d $t0, CSR_CRMD_IE + csrxchg $zero, $t0, CSR_CRMD + + li.d $t0, CSR_PRMD_PIE + csrwr $t0, CSR_PRMD + + csrrd $t1, CSR_TLBRERA + li.d $t0, -2 + and $t1, $t1, $t0 + csrwr $t1, CSR_TLBRERA + + csrrd $t1, CSR_GTLBC + li.d $t0, CSR_GTLBC_TGID + andn $t1, $t1, $t0 + ori $t1, $t1, CSR_GTLBC_TGID0 + csrwr $t1, CSR_GTLBC + +.endm + .macro RESTORE_GUEST_REGS ld.d $t0, $sp, 24 - csrwr $t0, 0x502 + csrwr $t0, CSR_SAVE0 ld.d $t0, $sp, 256 csrwr $t0, 0x6 @@ -188,7 +253,11 @@ gcsrwr $t0, 0x3 ld.d $t0, $sp, 296 gcsrwr $t0, 0x4 + gcsrrd $t1, 0x5 + li.d $t2, 0x0fff + and $t1, $t1, $t2 ld.d $t0, $sp, 304 + or $t0, $t0, $t1 gcsrwr $t0, 0x5 ld.d $t0, $sp, 312 gcsrwr $t0, 0x6 @@ -266,8 +335,12 @@ gcsrwr $t0, 0x40 ld.d $t0, $sp, 608 gcsrwr $t0, 0x41 - ld.d $t0, $sp, 616 - gcsrwr $t0, 0x42 + /* + * Do not restore GCSR_TVAL. QEMU-LVZ treats TVAL as the remaining + * ticks snapshot while guest mode is paused; writing it back on every + * VM entry re-bases a relative timer and keeps pushing the guest timer + * deadline into the future. + */ ld.d $t0, $sp, 624 gcsrwr $t0, 0x43 ld.d $t0, $sp, 632 @@ -299,6 +372,27 @@ ld.d $t0, $sp, 736 gcsrwr $t0, 0x183 + ld.d $t0, $sp, 256 + csrwr $t0, 0x6 + csrrd $t1, CSR_TLBRERA + li.d $t0, -2 + and $t1, $t1, $t0 + csrwr $t1, CSR_TLBRERA + csrrd $t1, CSR_TLBRPRMD + li.d $t0, -9 + and $t1, $t1, $t0 + csrwr $t1, CSR_TLBRPRMD + + li.d $t0, CSR_GSTAT_PVM + csrxchg $t0, $t0, CSR_GSTAT + + csrrd $t0, 0x6 + st.d $t0, $sp, 800 + gcsrrd $t0, 0x6 + st.d $t0, $sp, 808 + csrrd $t0, CSR_GSTAT + st.d $t0, $sp, 816 + ld.d $r1, $sp, 8 ld.d $r2, $sp, 16 ld.d $r4, $sp, 32 @@ -330,15 +424,16 @@ ld.d $r30, $sp, 240 ld.d $r31, $sp, 248 ld.d $r0, $sp, 0 - csrwr $sp, 0x502 + csrrd $sp, CSR_SAVE0 .endm .global _run_guest _run_guest: move $t1, $ra - addi.d $t0, $a0, 792 + addi.d $t0, $a0, 832 csrwr $t0, 0x33 move $sp, $a0 + PREPARE_GUEST_ENTRY RESTORE_GUEST_REGS ertn jr $t1 @@ -347,83 +442,86 @@ _run_guest: _guest_exit: b vmexit_trampoline -.section .vectors, "ax" -.align 12 +.balign 4096 +.global _guest_tlb_refill_vector +_guest_tlb_refill_vector: + csrwr $t0, CSR_TLBRSAVE + csrrd $t0, CSR_PGD + + lddir $t0, $t0, 3 + beqz $t0, .Lguest_stage2_tlb_invalid + + lddir $t0, $t0, 2 + beqz $t0, .Lguest_stage2_tlb_invalid + + lddir $t0, $t0, 1 + beqz $t0, .Lguest_stage2_tlb_invalid + + ldpte $t0, 0 + ldpte $t0, 1 + tlbfill + csrrd $t0, CSR_TLBRSAVE + ertn + +.Lguest_stage2_tlb_invalid: + csrrd $t0, CSR_TLBRSAVE + csrwr $t0, CSR_TLBRSAVE + DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 + csrwr $sp, CSR_SAVE0 + csrrd $sp, 0x33 + addi.d $sp, $sp, -832 + SAVE_GUEST_REGS + ENTER_HOST_MODE + li.d $a0, 0 + b _guest_exit + +.section .text.vectors, "ax" +.balign 0x10000 .global _exception_vectors _exception_vectors: - .org 0x0 - b _irq_handler_vector - .org 0x80 - b _sync_handler_vector - .org 0x100 - b _sync_handler_vector - .org 0x180 - b _sync_handler_vector - .org 0x200 - b _sync_handler_vector - .org 0x280 - b _sync_handler_vector - .org 0x400 - b _sync_handler_vector - .org 0x480 - b _sync_handler_vector - .org 0x500 - b _sync_handler_vector - .org 0x580 - b _sync_handler_vector - .org 0x600 - b _sync_handler_vector - .org 0x680 - b _sync_handler_vector - .org 0x700 - b _sync_handler_vector - .org 0x780 - b _sync_handler_vector - .org 0x800 - b _sync_handler_vector - .org 0x880 - b _sync_handler_vector - .org 0x900 - b _sync_handler_vector - .org 0x980 - b _sync_handler_vector - .org 0xa00 - b _sync_handler_vector - .org 0xa80 - b _sync_handler_vector - .org 0xb00 - b _hvc_handler_vector - .org 0xb80 - b _sync_handler_vector - .org 0xc00 - b _sync_handler_vector - .org 0xc80 - b _sync_handler_vector - .org 0xd00 - b _sync_handler_vector - .org 0xd80 - b _sync_handler_vector + .set __vec_slot, 0 + .rept 512 + .org __vec_slot * 0x80 + .if __vec_slot == 0 + b _irq_handler_vector + .elseif __vec_slot >= 64 + b _irq_handler_vector + .else + b _sync_handler_vector + .endif + .set __vec_slot, __vec_slot + 1 + .endr + .org 0x10000 _irq_handler_vector: - csrwr $sp, 0x502 + csrwr $t0, CSR_TLBRSAVE + DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 + csrwr $sp, CSR_SAVE0 csrrd $sp, 0x33 - addi.d $sp, $sp, -792 + addi.d $sp, $sp, -832 SAVE_GUEST_REGS + ENTER_HOST_MODE li.d $a0, 1 b _guest_exit _sync_handler_vector: - csrwr $sp, 0x502 + csrwr $t0, CSR_TLBRSAVE + DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 + csrwr $sp, CSR_SAVE0 csrrd $sp, 0x33 - addi.d $sp, $sp, -792 + addi.d $sp, $sp, -832 SAVE_GUEST_REGS + ENTER_HOST_MODE li.d $a0, 0 b _guest_exit _hvc_handler_vector: - csrwr $sp, 0x502 + csrwr $t0, CSR_TLBRSAVE + DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 + csrwr $sp, CSR_SAVE0 csrrd $sp, 0x33 - addi.d $sp, $sp, -792 + addi.d $sp, $sp, -832 SAVE_GUEST_REGS + ENTER_HOST_MODE li.d $a0, 0 b _guest_exit diff --git a/virtualization/loongarch_vcpu/src/registers.rs b/virtualization/loongarch_vcpu/src/registers.rs index df9baa4448..10f2f123ba 100644 --- a/virtualization/loongarch_vcpu/src/registers.rs +++ b/virtualization/loongarch_vcpu/src/registers.rs @@ -2,6 +2,10 @@ use ax_kspin::SpinNoIrq as Mutex; pub const CSR_GSTAT: u16 = 0x50; pub const CSR_EENTRY: u16 = 0x0c; +pub const CSR_TLBIDX: u16 = 0x10; +pub const CSR_TLBEHI: u16 = 0x11; +pub const CSR_TLBELO0: u16 = 0x12; +pub const CSR_TLBELO1: u16 = 0x13; pub const CSR_GCTL: u16 = 0x51; pub const CSR_GTLBC: u16 = 0x15; pub const CSR_GINTC: u16 = 0x52; @@ -11,6 +15,9 @@ pub const CSR_PWCL: u16 = 0x1c; pub const CSR_PWCH: u16 = 0x1d; pub const CSR_STLBPS: u16 = 0x1e; pub const CSR_TLBRENTRY: u16 = 0x88; +pub const CSR_TLBRELO0: u16 = 0x8c; +pub const CSR_TLBRELO1: u16 = 0x8d; +pub const CSR_TLBREHI: u16 = 0x8e; pub const CSR_ECFG: u16 = 0x4; pub const GCSR_ESTAT: usize = 0x5; @@ -122,8 +129,8 @@ pub(crate) unsafe fn gstat_set_gid(gid: usize) { } #[inline(always)] -pub(crate) unsafe fn gstat_set_pgm(pgm: bool) { - set_csr_bit::(1, pgm); +pub(crate) unsafe fn gstat_set_pvm(pvm: bool) { + set_csr_bit::(1, pvm); } #[inline(always)] @@ -177,9 +184,14 @@ pub(crate) unsafe fn gcfg_set_gpm_num(gpm_num: usize) { } #[inline(always)] -pub(crate) unsafe fn gintc_set_hwip(mask: usize) { +pub(crate) unsafe fn gintc_set_hwi_passthrough(mask: usize) { let mut gintc = read_gintc(); gintc &= !GINTC_HWIP_MASK; + // Do NOT clear HWIC here: writing HWIC bits clears the corresponding + // HWIS (pending) bits in GINTC. If an HWI was pending for the guest + // while a timer-induced VM exit was being handled, setting HWIC would + // silently discard that interrupt, eventually starving the guest's + // UART driver and freezing the console. gintc |= (mask << GINTC_HWIP_SHIFT) & GINTC_HWIP_MASK; write_gintc(gintc); } @@ -219,6 +231,25 @@ unsafe fn write_gintc(value: usize) { csr_write::(value); } +fn current_hwis() -> usize { + (read_gintc() & GINTC_HWIS_MASK) >> GINTC_HWIS_SHIFT +} + +unsafe fn pulse_hwi(vector: usize) { + let hwis_bit = 1 << (vector - INT_HWI0); + + let mut gintc = read_gintc(); + let cleared_hwis = current_hwis() & !hwis_bit; + gintc &= !GINTC_HWIS_MASK; + gintc |= (cleared_hwis << GINTC_HWIS_SHIFT) & GINTC_HWIS_MASK; + write_gintc(gintc); + + let mut gintc = read_gintc(); + gintc &= !GINTC_HWIS_MASK; + gintc |= ((cleared_hwis | hwis_bit) << GINTC_HWIS_SHIFT) & GINTC_HWIS_MASK; + write_gintc(gintc); +} + pub fn inject_interrupt(vector: usize) { if vector > INT_IPI { log::warn!("LoongArch64: invalid interrupt vector {vector}"); @@ -229,12 +260,7 @@ pub fn inject_interrupt(vector: usize) { unsafe { if (INT_HWI0..=INT_HWI7).contains(&vector) { - let hwis_bit = 1 << (vector - INT_HWI0); - let current_hwis = (read_gintc() & GINTC_HWIS_MASK) >> GINTC_HWIS_SHIFT; - let mut gintc = read_gintc(); - gintc &= !GINTC_HWIS_MASK; - gintc |= ((current_hwis | hwis_bit) << GINTC_HWIS_SHIFT) & GINTC_HWIS_MASK; - write_gintc(gintc); + pulse_hwi(vector); } else { let estat = gcsr_read::(); gcsr_write::(estat | (1usize << vector)); From bc3ef62a9aaa426c0be95f892cd7f19a0367f0c9 Mon Sep 17 00:00:00 2001 From: szy Date: Tue, 2 Jun 2026 14:38:47 +0800 Subject: [PATCH 02/50] add debug --- os/axvisor/doc/loongarch/debug-log-restore.md | 17 ++ .../doc/loongarch/restore-debug-logs.patch | 277 ++++++++++++++++++ 2 files changed, 294 insertions(+) create mode 100644 os/axvisor/doc/loongarch/debug-log-restore.md create mode 100644 os/axvisor/doc/loongarch/restore-debug-logs.patch diff --git a/os/axvisor/doc/loongarch/debug-log-restore.md b/os/axvisor/doc/loongarch/debug-log-restore.md new file mode 100644 index 0000000000..adf162e259 --- /dev/null +++ b/os/axvisor/doc/loongarch/debug-log-restore.md @@ -0,0 +1,17 @@ +# LoongArch 调试日志恢复补丁 + +`restore-debug-logs.patch` 保存了一组 LoongArch LVZ 启动/VM-exit 定位用日志。 + +正常开发时不应用该补丁，避免启动日志变慢、变多。需要重新定位启动卡顿、中断、GSPR/IOCSR、timer、guest PC 推进等问题时，在仓库根目录执行： + +```bash +git apply os/axvisor/doc/loongarch/restore-debug-logs.patch +``` + +定位完成后移除这些调试日志： + +```bash +git apply -R os/axvisor/doc/loongarch/restore-debug-logs.patch +``` + +补丁已用 `git apply --check` 验证可应用到当前代码。 diff --git a/os/axvisor/doc/loongarch/restore-debug-logs.patch b/os/axvisor/doc/loongarch/restore-debug-logs.patch new file mode 100644 index 0000000000..f424390f78 --- /dev/null +++ b/os/axvisor/doc/loongarch/restore-debug-logs.patch @@ -0,0 +1,277 @@ +--- a/components/loongarch_vcpu/src/exception.rs ++++ b/components/loongarch_vcpu/src/exception.rs +@@ -125,6 +125,24 @@ + + static GUEST_IOCSR_IPI_STATUS: AtomicUsize = AtomicUsize::new(0); + static GUEST_IOCSR_IPI_ENABLE: AtomicUsize = AtomicUsize::new(0); ++static DBG_TIMER_FORWARD_COUNT: AtomicUsize = AtomicUsize::new(0); ++static DBG_TIMER_WRITE_COUNT: AtomicUsize = AtomicUsize::new(0); ++static DBG_IDLE_EXIT_COUNT: AtomicUsize = AtomicUsize::new(0); ++static DBG_IOCSR_EMULATION_COUNT: AtomicUsize = AtomicUsize::new(0); ++static DBG_FETCHED_INSTRUCTION_COUNT: AtomicUsize = AtomicUsize::new(0); ++static DBG_GSPR_EMULATION_COUNT: AtomicUsize = AtomicUsize::new(0); ++static DBG_IRQ_EXIT_COUNT: AtomicUsize = AtomicUsize::new(0); ++static DBG_PC_ADVANCE_COUNT: AtomicUsize = AtomicUsize::new(0); ++static DBG_BRANCH_EMULATION_COUNT: AtomicUsize = AtomicUsize::new(0); ++ ++fn dbg_log_sparse(counter: &AtomicUsize) -> Option { ++ let count = counter.fetch_add(1, Ordering::Relaxed) + 1; ++ if count <= 16 || count.is_power_of_two() { ++ Some(count) ++ } else { ++ None ++ } ++} + + #[repr(u8)] + #[derive(Debug, Clone, Copy, PartialEq, Eq)] +@@ -370,6 +388,10 @@ + ctx.gcsr_crmd &= !(CSR_CRMD_PLV_MASK | CSR_CRMD_IE); + ctx.sepc = ctx.gcsr_eentry + ecode * guest_exception_vector_size(ctx); + ctx.guest_pc = ctx.sepc; ++ log::debug!( ++ "LoongArch inject guest exception: ecode={:#x}, esubcode={:#x}, pc={:#x}, badv={:#x}, entry={:#x}, gcrmd={:#x}, gestat={:#x}, gbadi={:#x}", ++ ecode, esubcode, pc, badv, ctx.sepc, ctx.gcsr_crmd, ctx.gcsr_estat, ctx.gcsr_badi, ++ ); + } + + fn inject_guest_emulated_memory_fault( +@@ -404,6 +426,10 @@ + ctx.gcsr_crmd = + (ctx.gcsr_crmd | CSR_CRMD_DA) & !(CSR_CRMD_PG | CSR_CRMD_PLV_MASK | CSR_CRMD_IE); + ctx.sepc = ctx.gcsr_tlbrentry; ++ log::debug!( ++ "LoongArch inject guest TLB refill: pc={:#x}, badv={:#x}, tlbrentry={:#x}, tlbrehi={:#x}, pgd={:#x}", ++ pc, badv, ctx.sepc, ctx.gcsr_tlbrehi, ctx.gcsr_pgd, ++ ); + } + + fn get_guest_interrupt_status(ctx: &LoongArchContextFrame) -> usize { +@@ -417,7 +443,14 @@ + } + + fn forward_timer_interrupt(ctx: &mut LoongArchContextFrame) { ++ let old_gestat = ctx.gcsr_estat; + ctx.gcsr_estat |= TIMER_BIT; ++ if let Some(count) = dbg_log_sparse(&DBG_TIMER_FORWARD_COUNT) { ++ log::debug!( ++ "LoongArch forward guest timer #{count}: pc={:#x}, sepc={:#x}, host_estat={:#x}, gcrmd={:#x}, gecfg={:#x}, old_gestat={:#x}, new_gestat={:#x}, host_tcfg={:#x}, host_tval={:#x}", ++ get_guest_pc(ctx), ctx.sepc, ctx.host_estat, ctx.gcsr_crmd, ctx.gcsr_ectl, old_gestat, ctx.gcsr_estat, read_host_timer_csr(CSR_TCFG), read_host_timer_csr(CSR_TVAL), ++ ); ++ } + ack_host_timer_interrupt(); + } + +@@ -447,16 +480,33 @@ + } + + fn advance_guest_pc(ctx: &mut LoongArchContextFrame) { +- let pc = get_guest_pc(ctx).wrapping_add(4); ++ let old_pc = get_guest_pc(ctx); ++ let old_sepc = ctx.sepc; ++ let old_gcsr_era = ctx.gcsr_era; ++ let pc = old_pc.wrapping_add(4); + ctx.sepc = pc; + ctx.guest_pc = pc; + ctx.gcsr_estat &= !CSR_ESTAT_EXC_MASK; ++ if let Some(count) = dbg_log_sparse(&DBG_PC_ADVANCE_COUNT) { ++ log::debug!( ++ "LoongArch guest PC advance #{count}: old_pc={:#x}, new_pc={:#x}, old_sepc={:#x}, preserved_gcsr_era={:#x}, host_tlbrera={:#x}", ++ old_pc, pc, old_sepc, old_gcsr_era, ctx.host_tlbrera, ++ ); ++ } + } + + fn set_guest_pc(ctx: &mut LoongArchContextFrame, pc: usize) { ++ let old_pc = get_guest_pc(ctx); ++ let old_sepc = ctx.sepc; + ctx.sepc = pc; + ctx.guest_pc = pc; + ctx.gcsr_estat &= !CSR_ESTAT_EXC_MASK; ++ if let Some(count) = dbg_log_sparse(&DBG_BRANCH_EMULATION_COUNT) { ++ log::debug!( ++ "LoongArch guest branch emulation #{count}: old_pc={:#x}, new_pc={:#x}, old_sepc={:#x}, host_era={:#x}, host_estat={:#x}", ++ old_pc, pc, old_sepc, ctx.host_era, ctx.host_estat, ++ ); ++ } + } + + fn emulate_cpucfg(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { +@@ -488,6 +538,10 @@ + emulate_guest_csr(ctx, rd, rj, csr); + advance_guest_pc(ctx); + if csr == CSR_CRMD && ctx.gcsr_crmd & CSR_CRMD_IE != 0 && ctx.gcsr_estat & TIMER_BIT != 0 { ++ log::debug!( ++ "LoongArch guest CRMD enables pending timer: pc={:#x}, gcrmd={:#x}, gecfg={:#x}, gestat={:#x}", ++ get_guest_pc(ctx), ctx.gcsr_crmd, ctx.gcsr_ectl, ctx.gcsr_estat, ++ ); + forward_timer_interrupt(ctx); + } + AxVCpuExitReason::Nothing +@@ -531,7 +585,10 @@ + CSR_STLBPS => ctx.gcsr_stlbps, + CSR_TCFG | CSR_TVAL | CSR_TICLR => read_host_timer_csr(csr), + CSR_SAVE0..=CSR_SAVE15 => read_guest_save_csr(ctx, csr), +- _ => 0, ++ _ => { ++ log::debug!("LoongArch GSPR csrrd emulation: csr={:#x}", csr); ++ 0 ++ }, + } + } + +@@ -552,7 +609,10 @@ + CSR_STLBPS => ctx.gcsr_stlbps = value, + CSR_TCFG | CSR_TVAL | CSR_TICLR => emulate_timer_write(ctx, csr, value), + CSR_SAVE0..=CSR_SAVE15 => write_guest_save_csr(ctx, csr, value), +- _ => {} ++ _ => log::debug!( ++ "LoongArch GSPR csr write emulation ignored: csr={:#x}, value={:#x}", ++ csr, value, ++ ) + } + } + +@@ -606,6 +666,12 @@ + /// when it fires the IRQ handler injects the interrupt into the guest ESTAT. + fn emulate_timer_write(ctx: &mut LoongArchContextFrame, csr: usize, value: usize) { + write_host_timer_csr(csr, value); ++ if let Some(count) = dbg_log_sparse(&DBG_TIMER_WRITE_COUNT) { ++ log::debug!( ++ "LoongArch guest timer CSR write #{count}: csr={:#x}, value={:#x}, pc={:#x}, gcrmd={:#x}, gecfg={:#x}, gestat={:#x}, host_tcfg={:#x}, host_tval={:#x}", ++ csr, value, get_guest_pc(ctx), ctx.gcsr_crmd, ctx.gcsr_ectl, ctx.gcsr_estat, read_host_timer_csr(CSR_TCFG), read_host_timer_csr(CSR_TVAL), ++ ); ++ } + if csr == CSR_TICLR && (value & CSR_TICLR_TI) != 0 { + ctx.gcsr_estat &= !TIMER_BIT; + ack_host_timer_interrupt(); +@@ -639,12 +705,22 @@ + } + + fn emulate_cacop(ctx: &mut LoongArchContextFrame, _ins: usize) -> AxVCpuExitReason { ++ log::debug!( ++ "LoongArch GSPR cacop emulation skipped at guest_pc={:#x}", ++ get_guest_pc(ctx), ++ ); + advance_guest_pc(ctx); + AxVCpuExitReason::Nothing + } + + fn emulate_idle(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { +- let _ = ins; ++ let level = extract_field(ins, 0, 15); ++ if let Some(count) = dbg_log_sparse(&DBG_IDLE_EXIT_COUNT) { ++ log::debug!( ++ "LoongArch guest idle request #{count}: level={:#x}, pc={:#x}, gcrmd={:#x}, gecfg={:#x}, gestat={:#x}, host_tcfg={:#x}, host_tval={:#x}", ++ level, get_guest_pc(ctx), ctx.gcsr_crmd, ctx.gcsr_ectl, ctx.gcsr_estat, read_host_timer_csr(CSR_TCFG), read_host_timer_csr(CSR_TVAL), ++ ); ++ } + advance_guest_pc(ctx); + AxVCpuExitReason::Idle + } +@@ -687,6 +763,12 @@ + let rj = extract_field(ins, 5, 5); + let rj_value = ctx.x[rj]; + let rd_value = ctx.x[rd]; ++ if let Some(count) = dbg_log_sparse(&DBG_IOCSR_EMULATION_COUNT) { ++ log::debug!( ++ "LoongArch IOCSR emulation #{count}: pc={:#x}, ins={:#x}, ty={}, rd={}, rd_value={:#x}, rj={}, rj_value={:#x}, host_estat={:#x}, host_badi={:#x}", ++ get_guest_pc(ctx), ins, ty, rd, rd_value, rj, rj_value, ctx.host_estat, ctx.host_badi, ++ ); ++ } + + if ty <= 3 { + if let Some(value) = read_guest_iocsr_ipi(rj_value) { +@@ -1227,7 +1309,7 @@ + ins: u32, + ) -> Option { + let ins = ins as usize; +- emulate_guest_pointer_access(ctx, ins) ++ let result = emulate_guest_pointer_access(ctx, ins) + .or_else(|| emulate_guest_regular_memory_access(ctx, ins)) + .or_else(|| emulate_guest_ll_sc(ctx, ins)) + .or_else(|| emulate_guest_logical_imm(ctx, ins)) +@@ -1246,7 +1328,14 @@ + .or_else(|| emulate_guest_alu_reg(ctx, ins)) + .or_else(|| emulate_guest_compact_branch(ctx, ins)) + .or_else(|| emulate_guest_branch(ctx, ins)) +- .or_else(|| try_emulate_gspr(ctx, ins)) ++ .or_else(|| try_emulate_gspr(ctx, ins)); ++ if let Some(count) = dbg_log_sparse(&DBG_FETCHED_INSTRUCTION_COUNT) { ++ log::debug!( ++ "LoongArch fetched instruction emulation #{count}: pc={:#x}, sepc={:#x}, gcsr_era={:#x}, host_era={:#x}, host_badi={:#x}, ins={:#x}, result={:?}", ++ get_guest_pc(ctx), ctx.sepc, ctx.gcsr_era, ctx.host_era, ctx.host_badi, ins, result, ++ ); ++ } ++ result + } + + fn try_emulate_gspr(ctx: &mut LoongArchContextFrame, ins: usize) -> Option { +@@ -1287,12 +1376,22 @@ + + fn emulate_gspr(ctx: &mut LoongArchContextFrame) -> AxVCpuExitReason { + let ins = get_guest_instruction(ctx); ++ if let Some(count) = dbg_log_sparse(&DBG_GSPR_EMULATION_COUNT) { ++ log::debug!( ++ "LoongArch GSPR emulation #{count}: pc={:#x}, ins={:#x}, host_estat={:#x}, host_badi={:#x}, guest_badi={:#x}, sepc={:#x}, gcsr_era={:#x}, host_era={:#x}", ++ get_guest_pc(ctx), ins, ctx.host_estat, ctx.host_badi, ctx.gcsr_badi, ctx.sepc, ctx.gcsr_era, ctx.host_era, ++ ); ++ } + if let Some(reason) = try_emulate_gspr(ctx, ins) { + return reason; + } + + let pc = get_guest_pc(ctx); + let fetch_gpa = direct_map_guest_addr_to_gpa(pc); ++ log::debug!( ++ "LoongArch GSPR BADI did not decode, fetching guest instruction: pc={:#x}, fetch_gpa={:#x}, badi={:#x}", ++ pc, fetch_gpa, ins, ++ ); + AxVCpuExitReason::GuestInstructionFetch { + addr: GuestPhysAddr::from(fetch_gpa), + } +@@ -1400,6 +1499,10 @@ + } else if is_qemu_invalid_badi(ins) { + let pc = get_guest_pc(ctx); + let fetch_gpa = direct_map_guest_addr_to_gpa(pc); ++ log::debug!( ++ "LoongArch INE BADI did not decode, fetching guest instruction: pc={:#x}, fetch_gpa={:#x}, badi={:#x}", ++ pc, fetch_gpa, ins, ++ ); + Ok(AxVCpuExitReason::GuestInstructionFetch { + addr: GuestPhysAddr::from(fetch_gpa), + }) +@@ -1441,6 +1544,10 @@ + // is never taken. Forward the timer interrupt into the guest by setting the + // timer bit in the guest ESTAT so that it is observed on the next VM entry. + if get_guest_interrupt_status(ctx) & TIMER_BIT != 0 { ++ log::debug!( ++ "LoongArch pending timer after sync: result={:?}, pc={:#x}, host_estat={:#x}, gestat={:#x}", ++ result, get_guest_pc(ctx), ctx.host_estat, ctx.gcsr_estat, ++ ); + forward_timer_interrupt(ctx); + } + result +@@ -1451,6 +1558,12 @@ + let is = guest_is; + + if let Some(vector) = decode_interrupt_vector(is) { ++ if let Some(count) = dbg_log_sparse(&DBG_IRQ_EXIT_COUNT) { ++ log::debug!( ++ "LoongArch irq exit #{count}: vector={}, guest_is={:#x}, host_estat={:#x}, pc={:#x}, gcrmd={:#x}, gecfg={:#x}, gestat={:#x}", ++ vector, guest_is, ctx.host_estat, get_guest_pc(ctx), ctx.gcsr_crmd, ctx.gcsr_ectl, ctx.gcsr_estat, ++ ); ++ } + // Inject the timer interrupt into the guest by setting the timer bit + // in the guest ESTAT. On the next VM entry RESTORE_GUEST_REGS will + // write this to GCSR ESTAT, so the guest sees the interrupt. +--- a/components/loongarch_vcpu/src/vcpu.rs ++++ b/components/loongarch_vcpu/src/vcpu.rs +@@ -182,6 +182,7 @@ + fn run(&mut self) -> AxResult { + #[cfg(target_arch = "loongarch64")] + { ++ log::debug!("LoongArch guest entry context:\n{}", self.ctx); + self.ctx.guest_pc = self.ctx.sepc; + let exit_reason = unsafe { + save_host_sp(); From 2cc7b0859213b5be04961f50d74051c2f1c0f863 Mon Sep 17 00:00:00 2001 From: szy Date: Tue, 2 Jun 2026 15:38:58 +0800 Subject: [PATCH 03/50] opt qemu env --- os/axvisor/doc/qemu-quickstart.md | 18 ++- os/axvisor/doc/qemu-quickstart_cn.md | 18 ++- os/axvisor/scripts/qemu-lvz.version | 4 + os/axvisor/scripts/quick-start.sh | 48 +++++-- os/axvisor/scripts/setup_qemu_lvz.sh | 144 ++++++++++++++++++++ scripts/axbuild/src/context/mod.rs | 36 ++--- scripts/axbuild/src/context/tests/arceos.rs | 62 +++++---- 7 files changed, 268 insertions(+), 62 deletions(-) create mode 100644 os/axvisor/scripts/qemu-lvz.version create mode 100755 os/axvisor/scripts/setup_qemu_lvz.sh diff --git a/os/axvisor/doc/qemu-quickstart.md b/os/axvisor/doc/qemu-quickstart.md index 708380820a..dbb0f96c96 100644 --- a/os/axvisor/doc/qemu-quickstart.md +++ b/os/axvisor/doc/qemu-quickstart.md @@ -171,6 +171,14 @@ Success indicator: `Hello, world!` appears in the output. ### AxVisor Shell (LoongArch64, requires QEMU-LVZ) +Install the pinned QEMU-LVZ once: + +```bash +./scripts/setup_qemu_lvz.sh +``` + +After that, quick-start auto-detects the cached binary: + ```bash ./scripts/quick-start.sh qemu-loongarch64 start ``` @@ -179,7 +187,13 @@ This command launches AxVisor directly and enters the built-in shell instead of Success indicator: `Welcome to AxVisor Shell!` appears in the output. -> **Note**: Stock `qemu-system-loongarch64` usually does not expose LoongArch virtualization extensions. Use `QEMU-LVZ`, or set `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` to a validated virtualization-capable binary. +For the Linux guest flow, run: + +```bash +./scripts/quick-start.sh qemu-loongarch64 run --linux +``` + +> **Note**: Stock `qemu-system-loongarch64` usually does not expose LoongArch virtualization extensions. Run `./scripts/setup_qemu_lvz.sh` once, or set `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` to a validated virtualization-capable binary. ## 5. What Does setup_qemu.sh Do? @@ -211,7 +225,7 @@ QEMU is not installed. Run the `apt install` command from Step 1. ### `Hardware support: false` followed by a panic on LoongArch64 -AxVisor was launched with a LoongArch QEMU binary that does not provide virtualization extensions. Switch to `QEMU-LVZ`, or export `AXBUILD_QEMU_SYSTEM_LOONGARCH64` to point at a validated `qemu-system-loongarch64` binary before running `./scripts/quick-start.sh qemu-loongarch64 start`. +AxVisor was launched with a LoongArch QEMU binary that does not provide virtualization extensions. Run `./scripts/setup_qemu_lvz.sh` once, or export `AXBUILD_QEMU_SYSTEM_LOONGARCH64` to point at a validated `qemu-system-loongarch64` binary before running `./scripts/quick-start.sh qemu-loongarch64 start`. ### `Auto syncing from registry ... timed out` diff --git a/os/axvisor/doc/qemu-quickstart_cn.md b/os/axvisor/doc/qemu-quickstart_cn.md index 37ee3f140d..235f4a4079 100644 --- a/os/axvisor/doc/qemu-quickstart_cn.md +++ b/os/axvisor/doc/qemu-quickstart_cn.md @@ -129,6 +129,14 @@ cargo xtask qemu \ ### AxVisor Shell（LoongArch64，需要 QEMU-LVZ） +首次使用先安装固定版本 QEMU-LVZ： + +```bash +./scripts/setup_qemu_lvz.sh +``` + +安装完成后，quick-start 会自动发现缓存中的 QEMU-LVZ： + ```bash ./scripts/quick-start.sh qemu-loongarch64 start ``` @@ -137,7 +145,13 @@ cargo xtask qemu \ 启动成功标志：输出中出现 `Welcome to AxVisor Shell!` -> **注意**：标准版 `qemu-system-loongarch64` 通常不会暴露 LoongArch 虚拟化扩展。请使用 `QEMU-LVZ`，或者通过 `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` 指向一个已经确认支持虚拟化扩展的二进制。 +Linux guest 启动使用： + +```bash +./scripts/quick-start.sh qemu-loongarch64 run --linux +``` + +> **注意**：标准版 `qemu-system-loongarch64` 通常不会暴露 LoongArch 虚拟化扩展。请先运行一次 `./scripts/setup_qemu_lvz.sh`，或者通过 `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` 指向一个已经确认支持虚拟化扩展的二进制。 ## 5. setup_qemu.sh 做了什么 @@ -165,7 +179,7 @@ VM 配置中的 `kernel_path` 指向了不存在的文件。运行 `./scripts/se ### LoongArch64 下出现 `Hardware support: false`，随后 panic -这说明当前启动使用的 LoongArch QEMU 二进制没有提供虚拟化扩展。请切换到 `QEMU-LVZ`，或在运行 `./scripts/quick-start.sh qemu-loongarch64 start` 前导出 `AXBUILD_QEMU_SYSTEM_LOONGARCH64`，把它指向一个已验证支持虚拟化扩展的 `qemu-system-loongarch64`。 +这说明当前启动使用的 LoongArch QEMU 二进制没有提供虚拟化扩展。请先运行一次 `./scripts/setup_qemu_lvz.sh`，或在运行 `./scripts/quick-start.sh qemu-loongarch64 start` 前导出 `AXBUILD_QEMU_SYSTEM_LOONGARCH64`，把它指向一个已验证支持虚拟化扩展的 `qemu-system-loongarch64`。 ### `Auto syncing from registry ... timed out` diff --git a/os/axvisor/scripts/qemu-lvz.version b/os/axvisor/scripts/qemu-lvz.version new file mode 100644 index 0000000000..f10b8b0b56 --- /dev/null +++ b/os/axvisor/scripts/qemu-lvz.version @@ -0,0 +1,4 @@ +QEMU_LVZ_REPO=https://github.com/Hengyu-Yu/QEMU-LVZ.git +QEMU_LVZ_COMMIT=360a7753d3df618b3cceddc82dc8e1ff363ff846 +QEMU_LVZ_VERSION=9.0.50 +QEMU_LVZ_TARGET_LIST=loongarch64-softmmu diff --git a/os/axvisor/scripts/quick-start.sh b/os/axvisor/scripts/quick-start.sh index 0b6d9f48cb..271da66a4a 100755 --- a/os/axvisor/scripts/quick-start.sh +++ b/os/axvisor/scripts/quick-start.sh @@ -26,6 +26,22 @@ error() { echo -e "${RED}[ERROR]${NC} $1" } +qemu_lvz_version_value() { + local key="$1" + local version_file="scripts/qemu-lvz.version" + if [[ -f "$version_file" ]]; then + sed -n "s/^${key}=//p" "$version_file" | tail -n 1 + fi +} + +qemu_lvz_cache_binary() { + local commit + commit="$(qemu_lvz_version_value QEMU_LVZ_COMMIT)" + if [[ -n "$commit" ]]; then + printf '%s\n' "${AXVISOR_QEMU_LVZ_CACHE:-$HOME/.cache/axvisor/qemu-lvz}/$commit/bin/qemu-system-loongarch64" + fi +} + # Execute command and display it run_cmd() { echo -e "${BLUE}$@${NC}" @@ -336,18 +352,17 @@ setup_qemu_loongarch64() { info "Preparing QEMU config file..." run_cmd cp configs/qemu/qemu-loongarch64.toml tmp/configs/qemu-loongarch64-runtime.toml + local cached_qemu + cached_qemu="$(qemu_lvz_cache_binary)" + if [[ -n "${AXBUILD_QEMU_SYSTEM_LOONGARCH64:-}" ]]; then info "Using explicit LoongArch QEMU override: ${AXBUILD_QEMU_SYSTEM_LOONGARCH64}" - elif [[ -x "$HOME/qemu-lvz-ci-install/bin/qemu-system-loongarch64" ]]; then - info "Detected CI-pinned QEMU-LVZ at $HOME/qemu-lvz-ci-install/bin/qemu-system-loongarch64" - elif [[ -x "$HOME/QEMU-LVZ/build/qemu-system-loongarch64" ]]; then - info "Detected QEMU-LVZ at $HOME/QEMU-LVZ/build/qemu-system-loongarch64" - elif [[ -x "$HOME/qemu-lvz/build/qemu-system-loongarch64" ]]; then - info "Detected QEMU-LVZ at $HOME/qemu-lvz/build/qemu-system-loongarch64" + elif [[ -n "$cached_qemu" && -x "$cached_qemu" ]]; then + info "Detected pinned QEMU-LVZ cache at $cached_qemu" elif command -v qemu-system-loongarch64 &> /dev/null; then warn "Using qemu-system-loongarch64 from PATH. Stock QEMU usually lacks LoongArch virtualization extensions; prefer QEMU-LVZ." else - warn "No LoongArch QEMU binary detected. Set AXBUILD_QEMU_SYSTEM_LOONGARCH64 or install QEMU-LVZ before running." + warn "No LoongArch QEMU binary detected. Run ./scripts/setup_qemu_lvz.sh once, or set AXBUILD_QEMU_SYSTEM_LOONGARCH64." fi info "=== QEMU LoongArch64 Preparation Complete ===" @@ -361,14 +376,15 @@ run_qemu_loongarch64_axvisor() { } loongarch64_qemu_binary() { + local cached_qemu + cached_qemu="$(qemu_lvz_cache_binary)" + if [[ -n "${AXBUILD_QEMU_SYSTEM_LOONGARCH64:-}" ]]; then printf '%s\n' "${AXBUILD_QEMU_SYSTEM_LOONGARCH64}" - elif [[ -x "$HOME/qemu-lvz-ci-install/bin/qemu-system-loongarch64" ]]; then - printf '%s\n' "$HOME/qemu-lvz-ci-install/bin/qemu-system-loongarch64" - elif [[ -x "$HOME/QEMU-LVZ/build/qemu-system-loongarch64" ]]; then - printf '%s\n' "$HOME/QEMU-LVZ/build/qemu-system-loongarch64" - elif [[ -x "$HOME/qemu-lvz/build/qemu-system-loongarch64" ]]; then - printf '%s\n' "$HOME/qemu-lvz/build/qemu-system-loongarch64" + elif [[ -n "$cached_qemu" && -x "$cached_qemu" ]]; then + printf '%s\n' "$cached_qemu" + elif command -v qemu-system-loongarch64 &> /dev/null; then + command -v qemu-system-loongarch64 else return 1 fi @@ -378,11 +394,15 @@ run_axvisor_qemu_with_loongarch64_qemu() { local qemu_bin local qemu_dir qemu_bin="$(loongarch64_qemu_binary)" || { - error "QEMU-LVZ qemu-system-loongarch64 not found. Set AXBUILD_QEMU_SYSTEM_LOONGARCH64 or install QEMU-LVZ." + error "LoongArch qemu-system-loongarch64 not found. Run ./scripts/setup_qemu_lvz.sh once, or set AXBUILD_QEMU_SYSTEM_LOONGARCH64." exit 1 } qemu_dir="$(dirname "$qemu_bin")" info "Using LoongArch QEMU: $qemu_bin" + "$qemu_bin" --version | head -n 1 + if [[ "$qemu_bin" == "$(command -v qemu-system-loongarch64 2>/dev/null || true)" ]]; then + warn "PATH qemu-system-loongarch64 may not support LoongArch LVZ. If boot fails, run ./scripts/setup_qemu_lvz.sh." + fi PATH="$qemu_dir:$PATH" run_axvisor_qemu "$@" } diff --git a/os/axvisor/scripts/setup_qemu_lvz.sh b/os/axvisor/scripts/setup_qemu_lvz.sh new file mode 100755 index 0000000000..a3d4f991b3 --- /dev/null +++ b/os/axvisor/scripts/setup_qemu_lvz.sh @@ -0,0 +1,144 @@ +#!/bin/bash +# +# Build and install the pinned QEMU-LVZ used by LoongArch64 AxVisor runs. + +set -euo pipefail + +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +VERSION_FILE="$SCRIPT_DIR/qemu-lvz.version" + +if [[ ! -f "$VERSION_FILE" ]]; then + echo "[ERROR] QEMU-LVZ version file not found: $VERSION_FILE" >&2 + exit 1 +fi + +# shellcheck disable=SC1090 +source "$VERSION_FILE" + +: "${QEMU_LVZ_REPO:?missing QEMU_LVZ_REPO in $VERSION_FILE}" +: "${QEMU_LVZ_COMMIT:?missing QEMU_LVZ_COMMIT in $VERSION_FILE}" +: "${QEMU_LVZ_TARGET_LIST:?missing QEMU_LVZ_TARGET_LIST in $VERSION_FILE}" + +CACHE_ROOT="${AXVISOR_QEMU_LVZ_CACHE:-$HOME/.cache/axvisor/qemu-lvz}" +SRC_DIR="$CACHE_ROOT/src/$QEMU_LVZ_COMMIT" +INSTALL_DIR="$CACHE_ROOT/$QEMU_LVZ_COMMIT" +QEMU_BIN="$INSTALL_DIR/bin/qemu-system-loongarch64" +PYTHON_VENV="$CACHE_ROOT/python-venv" + +jobs="${JOBS:-$(nproc 2>/dev/null || echo 1)}" + +case "${1:-}" in + -h|--help) + cat <&2 + exit 1 + ;; +esac + +info() { + echo "[INFO] $*" +} + +run() { + echo "+ $*" + "$@" +} + +git_run() { + echo "+ git $*" + GIT_CONFIG_NOSYSTEM=1 GIT_CONFIG_GLOBAL=/dev/null git "$@" +} + +host_python() { + if [[ -n "${AXVISOR_QEMU_LVZ_PYTHON:-}" ]]; then + printf '%s\n' "$AXVISOR_QEMU_LVZ_PYTHON" + elif [[ -x /usr/bin/python3 ]]; then + printf '%s\n' /usr/bin/python3 + else + command -v python3 + fi +} + +prepare_python() { + local base_python="$1" + + if "$base_python" -c 'import distlib' >/dev/null 2>&1; then + printf '%s\n' "$base_python" + return 0 + fi + + if [[ ! -x "$PYTHON_VENV/bin/python3" ]] \ + || ! "$PYTHON_VENV/bin/python3" -c 'import distlib' >/dev/null 2>&1; then + info "Preparing QEMU configure Python venv" >&2 + run "$base_python" -m venv "$PYTHON_VENV" >&2 + run "$PYTHON_VENV/bin/python3" -m pip install --upgrade pip >&2 + run "$PYTHON_VENV/bin/python3" -m pip install distlib >&2 + fi + + printf '%s\n' "$PYTHON_VENV/bin/python3" +} + +if [[ -x "$QEMU_BIN" ]]; then + info "Pinned QEMU-LVZ already installed: $QEMU_BIN" +else + base_python="$(host_python)" || { + echo "[ERROR] python3 not found. Install python3 or set AXVISOR_QEMU_LVZ_PYTHON." >&2 + exit 1 + } + qemu_python="$(prepare_python "$base_python")" + + mkdir -p "$CACHE_ROOT/src" + + if [[ ! -d "$SRC_DIR/.git" ]]; then + info "Cloning QEMU-LVZ $QEMU_LVZ_COMMIT" + git_run clone "$QEMU_LVZ_REPO" "$SRC_DIR" + fi + + git_run -C "$SRC_DIR" fetch --depth 1 origin "$QEMU_LVZ_COMMIT" + git_run -C "$SRC_DIR" checkout --detach "$QEMU_LVZ_COMMIT" + + mkdir -p "$INSTALL_DIR" + + mkdir -p "$SRC_DIR/build" + if [[ ! -f "$SRC_DIR/build/build.ninja" ]]; then + info "Configuring QEMU-LVZ" + ( + cd "$SRC_DIR/build" + GIT_CONFIG_NOSYSTEM=1 GIT_CONFIG_GLOBAL=/dev/null run ../configure \ + --target-list="$QEMU_LVZ_TARGET_LIST" \ + --prefix="$INSTALL_DIR" \ + --python="$qemu_python" + ) + fi + + info "Building QEMU-LVZ with $jobs job(s)" + run make -C "$SRC_DIR/build" -j "$jobs" + run make -C "$SRC_DIR/build" install +fi + +info "QEMU-LVZ binary: $QEMU_BIN" +"$QEMU_BIN" --version +info "After this one-time setup, run ./scripts/quick-start.sh qemu-loongarch64 run --linux directly." diff --git a/scripts/axbuild/src/context/mod.rs b/scripts/axbuild/src/context/mod.rs index 965ed6223d..108b462143 100644 --- a/scripts/axbuild/src/context/mod.rs +++ b/scripts/axbuild/src/context/mod.rs @@ -556,29 +556,31 @@ fn find_loongarch_qemu_dir(workspace_root: &Path) -> Option { fn loongarch_qemu_dir_candidates(workspace_root: &Path) -> Vec { let mut candidates = Vec::new(); - if let Some(home) = env::var_os("HOME").map(PathBuf::from) { - for suffix in [ - "qemu-lvz-ci-install/bin", - "QEMU-LVZ/build", - "qemu-lvz/build", - ] { - candidates.push(home.join(suffix)); - } - } - - for ancestor in workspace_root.ancestors() { - for suffix in [ - "qemu-lvz-ci-install/bin", - "QEMU-LVZ/build", - "qemu-lvz/build", - ] { - candidates.push(ancestor.join(suffix)); + if let Some(commit) = pinned_qemu_lvz_commit(workspace_root) { + let cache_root = env::var_os("AXVISOR_QEMU_LVZ_CACHE") + .map(PathBuf::from) + .or_else(|| { + env::var_os("HOME").map(|home| PathBuf::from(home).join(".cache/axvisor/qemu-lvz")) + }); + if let Some(cache_root) = cache_root { + candidates.push(cache_root.join(commit).join("bin")); } } candidates } +fn pinned_qemu_lvz_commit(workspace_root: &Path) -> Option { + let version_file = workspace_root.join("os/axvisor/scripts/qemu-lvz.version"); + let content = std::fs::read_to_string(version_file).ok()?; + content + .lines() + .find_map(|line| line.strip_prefix("QEMU_LVZ_COMMIT=")) + .map(str::trim) + .filter(|commit| !commit.is_empty()) + .map(str::to_owned) +} + fn is_loongarch_qemu_dir(dir: &Path) -> bool { dir.join("qemu-system-loongarch64").exists() } diff --git a/scripts/axbuild/src/context/tests/arceos.rs b/scripts/axbuild/src/context/tests/arceos.rs index f7f1cde494..7c2ea6d91c 100644 --- a/scripts/axbuild/src/context/tests/arceos.rs +++ b/scripts/axbuild/src/context/tests/arceos.rs @@ -216,48 +216,56 @@ fn find_loongarch_qemu_dir_prefers_explicit_env_override() { } #[test] -fn find_loongarch_qemu_dir_checks_home_before_workspace_ancestors() { +fn find_loongarch_qemu_dir_uses_pinned_cache() { let _lock = ENV_LOCK.lock().unwrap(); let home = tempdir().unwrap(); - let workspace_parent = tempdir().unwrap(); - let workspace_root = workspace_parent.path().join("workspace/repo"); - let home_qemu_dir = home.path().join("QEMU-LVZ/build"); - let ancestor_qemu_dir = workspace_parent.path().join("qemu-lvz/build"); - - fs::create_dir_all(&workspace_root).unwrap(); - fs::create_dir_all(&home_qemu_dir).unwrap(); - fs::create_dir_all(&ancestor_qemu_dir).unwrap(); - fs::write(home_qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); - fs::write(ancestor_qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); + let workspace = tempdir().unwrap(); + let commit = "1234567890abcdef"; + let qemu_dir = home + .path() + .join(".cache/axvisor/qemu-lvz") + .join(commit) + .join("bin"); + + fs::create_dir_all(workspace.path().join("os/axvisor/scripts")).unwrap(); + fs::write( + workspace.path().join("os/axvisor/scripts/qemu-lvz.version"), + format!("QEMU_LVZ_COMMIT={commit}\n"), + ) + .unwrap(); + fs::create_dir_all(&qemu_dir).unwrap(); + fs::write(qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); let _qemu_dir = TempEnvVar::unset("AXBUILD_QEMU_DIR"); let _qemu_bin = TempEnvVar::unset("AXBUILD_QEMU_SYSTEM_LOONGARCH64"); let _home = TempEnvVar::set("HOME", home.path()); - assert_eq!( - find_loongarch_qemu_dir(&workspace_root), - Some(home_qemu_dir) - ); + assert_eq!(find_loongarch_qemu_dir(workspace.path()), Some(qemu_dir)); } #[test] -fn find_loongarch_qemu_dir_prefers_ci_pinned_home_install() { +fn find_loongarch_qemu_dir_honors_custom_pinned_cache_root() { let _lock = ENV_LOCK.lock().unwrap(); - let home = tempdir().unwrap(); - let root = tempdir().unwrap(); - let ci_qemu_dir = home.path().join("qemu-lvz-ci-install/bin"); - let legacy_qemu_dir = home.path().join("QEMU-LVZ/build"); - - fs::create_dir_all(&ci_qemu_dir).unwrap(); - fs::create_dir_all(&legacy_qemu_dir).unwrap(); - fs::write(ci_qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); - fs::write(legacy_qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); + let cache = tempdir().unwrap(); + let workspace = tempdir().unwrap(); + let commit = "abcdef1234567890"; + let qemu_dir = cache.path().join(commit).join("bin"); + + fs::create_dir_all(workspace.path().join("os/axvisor/scripts")).unwrap(); + fs::write( + workspace.path().join("os/axvisor/scripts/qemu-lvz.version"), + format!("QEMU_LVZ_COMMIT={commit}\n"), + ) + .unwrap(); + fs::create_dir_all(&qemu_dir).unwrap(); + fs::write(qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); let _qemu_dir = TempEnvVar::unset("AXBUILD_QEMU_DIR"); let _qemu_bin = TempEnvVar::unset("AXBUILD_QEMU_SYSTEM_LOONGARCH64"); - let _home = TempEnvVar::set("HOME", home.path()); + let _home = TempEnvVar::unset("HOME"); + let _cache = TempEnvVar::set("AXVISOR_QEMU_LVZ_CACHE", cache.path()); - assert_eq!(find_loongarch_qemu_dir(root.path()), Some(ci_qemu_dir)); + assert_eq!(find_loongarch_qemu_dir(workspace.path()), Some(qemu_dir)); } #[test] From 42468d0275ca239a3e9b0ac809d10046562b82cb Mon Sep 17 00:00:00 2001 From: szy Date: Wed, 3 Jun 2026 09:13:45 +0800 Subject: [PATCH 04/50] rootfs --- components/axcpu/src/loongarch64/asm.rs | 66 +++++- .../board/qemu-loongarch64-guest-rootfs.toml | 9 + os/axvisor/configs/qemu/qemu-loongarch64.toml | 2 + .../linux-loongarch64-qemu-rootfs-smp1.dts | 184 ++++++++++++++++ .../linux-loongarch64-qemu-rootfs-smp1.toml | 67 ++++++ os/axvisor/scripts/quick-start.sh | 67 +++++- .../axconfig.toml | 4 +- .../src/irq/eiointc.rs | 15 +- .../src/irq/pch_pic.rs | 27 ++- .../ax-plat-loongarch64-qemu-virt/src/mem.rs | 5 +- .../ax-plat-loongarch64-qemu-virt/src/time.rs | 4 +- virtualization/axvcpu/src/exit.rs | 33 --- virtualization/axvcpu/src/vcpu.rs | 16 +- .../loongarch_vcpu/src/context_frame.rs | 10 +- virtualization/loongarch_vcpu/src/exception.S | 208 +++++++++++++----- virtualization/loongarch_vcpu/src/lib.rs | 2 + .../loongarch_vcpu/src/registers.rs | 20 +- 17 files changed, 611 insertions(+), 128 deletions(-) create mode 100644 os/axvisor/configs/board/qemu-loongarch64-guest-rootfs.toml create mode 100644 os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts create mode 100644 os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml diff --git a/components/axcpu/src/loongarch64/asm.rs b/components/axcpu/src/loongarch64/asm.rs index 2a4232f80d..3c79599a90 100644 --- a/components/axcpu/src/loongarch64/asm.rs +++ b/components/axcpu/src/loongarch64/asm.rs @@ -3,7 +3,32 @@ use core::arch::asm; use ax_memory_addr::{PhysAddr, VirtAddr}; -use loongArch64::register::{crmd, ecfg, eentry, pgdh, pgdl}; +use loongArch64::register::{ + crmd, + ecfg::{self, LineBasedInterrupt}, + eentry, estat, pgdh, pgdl, tcfg, tlbrentry, tval, +}; + +#[derive(Debug, Clone, Copy)] +/// A raw snapshot of LoongArch interrupt and timer CSRs. +pub struct IrqDebugSnapshot { + /// Current mode information CSR. + pub crmd: usize, + /// Exception configuration CSR. + pub ecfg: usize, + /// Exception status CSR. + pub estat: usize, + /// General exception entry base CSR. + pub eentry: usize, + /// TLB refill exception entry base CSR. + pub tlbrentry: usize, + /// Timer configuration CSR. + pub tcfg: usize, + /// Timer value CSR. + pub tval: usize, + /// Kernel scratch CSR used by the host trap entry to save the kernel stack. + pub ksave_ksp: usize, +} /// Allows the current CPU to respond to interrupts. #[inline] @@ -23,12 +48,49 @@ pub fn irqs_enabled() -> bool { crmd::read().ie() } +/// Enables or disables the local timer interrupt line. +#[inline] +pub fn set_timer_irq_enabled(enabled: bool) { + set_local_irq_line_enabled(LineBasedInterrupt::TIMER, enabled) +} + +/// Enables or disables a local interrupt line. +#[inline] +fn set_local_irq_line_enabled(line: LineBasedInterrupt, enabled: bool) { + let current = ecfg::read().lie(); + let new_value = if enabled { + current | line + } else { + current & !line + }; + ecfg::set_lie(new_value); +} + +/// Captures the local interrupt and timer CSRs for LoongArch debugging. +#[inline] +pub fn irq_debug_snapshot() -> IrqDebugSnapshot { + let ksave_ksp: usize; + unsafe { + asm!("csrrd {}, 0x30", out(reg) ksave_ksp); + } + IrqDebugSnapshot { + crmd: crmd::read().raw(), + ecfg: ecfg::read().raw(), + estat: estat::read().raw(), + eentry: eentry::read().raw(), + tlbrentry: tlbrentry::read().raw(), + tcfg: tcfg::read().raw(), + tval: tval::read().raw(), + ksave_ksp, + } +} + /// Relaxes the current CPU and waits for interrupts. /// /// It must be called with interrupts enabled, otherwise it will never return. #[inline] pub fn wait_for_irqs() { - unsafe { loongArch64::asm::idle() } + unsafe { asm!("idle 0", options(nomem, nostack)) } } /// Halt the current CPU. diff --git a/os/axvisor/configs/board/qemu-loongarch64-guest-rootfs.toml b/os/axvisor/configs/board/qemu-loongarch64-guest-rootfs.toml new file mode 100644 index 0000000000..2a6f04e109 --- /dev/null +++ b/os/axvisor/configs/board/qemu-loongarch64-guest-rootfs.toml @@ -0,0 +1,9 @@ +env = {AX_IP = "10.0.2.15", AX_GW = "10.0.2.2"} +features = [ + "ax-hal/loongarch64-qemu-virt", + "ept-level-4", +] +log = "Info" +max_cpu_num = 1 +target = "loongarch64-unknown-none-softfloat" +vm_configs = [] diff --git a/os/axvisor/configs/qemu/qemu-loongarch64.toml b/os/axvisor/configs/qemu/qemu-loongarch64.toml index 0ed2e79ddc..c8dcfbad8e 100644 --- a/os/axvisor/configs/qemu/qemu-loongarch64.toml +++ b/os/axvisor/configs/qemu/qemu-loongarch64.toml @@ -11,6 +11,8 @@ args = [ "-serial", "mon:stdio", "-no-reboot", + "-net", + "none", "-device", "virtio-blk-pci,drive=disk0", "-drive", diff --git a/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts b/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts new file mode 100644 index 0000000000..7bbfe753b1 --- /dev/null +++ b/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts @@ -0,0 +1,184 @@ +/dts-v1/; + +/ { + #size-cells = <0x02>; + #address-cells = <0x02>; + compatible = "linux,dummy-loongson3"; + + platform-bus@16000000 { + interrupt-parent = <0x8003>; + ranges = <0x00 0x00 0x16000000 0x2000000>; + #address-cells = <0x01>; + #size-cells = <0x01>; + compatible = "qemu,platform\0simple-bus"; + }; + + poweroff { + value = <0x34>; + offset = <0x00>; + regmap = <0x8005>; + compatible = "syscon-poweroff"; + }; + + reboot { + value = <0x42>; + offset = <0x02>; + regmap = <0x8005>; + compatible = "syscon-reboot"; + }; + + ged@100e001c { + phandle = <0x8005>; + reg-io-width = <0x01>; + reg-shift = <0x00>; + reg = <0x00 0x100e001c 0x00 0x03>; + compatible = "syscon"; + }; + + rtc@100d0100 { + interrupt-parent = <0x8003>; + interrupts = <0x06 0x04>; + reg = <0x00 0x100d0100 0x00 0x100>; + compatible = "loongson,ls7a-rtc"; + }; + + serial@1fe001e0 { + interrupt-parent = <0x8003>; + interrupts = <0x02 0x04>; + clock-frequency = <0x5f5e100>; + reg = <0x00 0x1fe001e0 0x00 0x100>; + compatible = "ns16550a"; + }; + + serial@1fe002e0 { + status = "disabled"; + interrupt-parent = <0x8003>; + interrupts = <0x03 0x04>; + clock-frequency = <0x5f5e100>; + reg = <0x00 0x1fe002e0 0x00 0x100>; + compatible = "ns16550a"; + }; + + serial@1fe003e0 { + status = "disabled"; + interrupt-parent = <0x8003>; + interrupts = <0x04 0x04>; + clock-frequency = <0x5f5e100>; + reg = <0x00 0x1fe003e0 0x00 0x100>; + compatible = "ns16550a"; + }; + + serial@1fe004e0 { + status = "disabled"; + interrupt-parent = <0x8003>; + interrupts = <0x05 0x04>; + clock-frequency = <0x5f5e100>; + reg = <0x00 0x1fe004e0 0x00 0x100>; + compatible = "ns16550a"; + }; + + pcie@20000000 { + interrupt-map-mask = <0x1800 0x00 0x00 0x07>; + interrupt-map = <0x800 0x00 0x00 0x01 0x8003 0x11 0x04 + 0x800 0x00 0x00 0x02 0x8003 0x12 0x04 + 0x800 0x00 0x00 0x03 0x8003 0x13 0x04 + 0x800 0x00 0x00 0x04 0x8003 0x10 0x04>; + msi-map = <0x00 0x8004 0x00 0x10000>; + ranges = <0x1000000 0x00 0x4000 0x00 0x18004000 0x00 0xc000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000>; + reg = <0x00 0x20000000 0x00 0x8000000>; + dma-coherent; + bus-range = <0x00 0x7f>; + linux,pci-domain = <0x00>; + #interrupt-cells = <0x01>; + #size-cells = <0x02>; + #address-cells = <0x03>; + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + }; + + msi@2ff00000 { + loongson,msi-num-vecs = <0xe0>; + loongson,msi-base-vec = <0x20>; + interrupt-parent = <0x8002>; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + #msi-cells = <0x01>; + msi-controller; + interrupt-controller; + reg = <0x00 0x2ff00000 0x00 0x08>; + compatible = "loongson,pch-msi-1.0"; + phandle = <0x8004>; + }; + + platic@10000000 { + loongson,pic-base-vec = <0x00>; + interrupt-parent = <0x8002>; + #address-cells = <0x00>; + #interrupt-cells = <0x02>; + interrupt-controller; + reg = <0x00 0x10000000 0x00 0x400>; + compatible = "loongson,pch-pic-1.0"; + phandle = <0x8003>; + }; + + eiointc@1400 { + reg = <0x00 0x1400 0x00 0x800>; + interrupts = <0x03>; + interrupt-parent = <0x8001>; + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "loongson,ls2k2000-eiointc"; + phandle = <0x8002>; + }; + + cpuic { + #address-cells = <0x00>; + #interrupt-cells = <0x01>; + interrupt-controller; + compatible = "loongson,cpu-interrupt-controller"; + phandle = <0x8001>; + }; + + flash@1c000000 { + bank-width = <0x04>; + reg = <0x00 0x1c000000 0x00 0x1000000 0x00 0x1d000000 0x00 0x1000000>; + compatible = "cfi-flash"; + }; + + fw_cfg@1e020000 { + dma-coherent; + reg = <0x00 0x1e020000 0x00 0x18>; + compatible = "qemu,fw-cfg-mmio"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00 0x00 0x00 0x0a000000>; + }; + + cpus { + #size-cells = <0x00>; + #address-cells = <0x01>; + + cpu-map { + socket0 { + core0 { + cpu = <0x8000>; + }; + }; + }; + + cpu@0 { + phandle = <0x8000>; + reg = <0x00>; + compatible = "loongarch,Loongson-3A5000"; + device_type = "cpu"; + }; + }; + + chosen { + bootargs = ""; + stdout-path = "/serial@1fe001e0"; + }; +}; diff --git a/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml b/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml new file mode 100644 index 0000000000..db7395dbb9 --- /dev/null +++ b/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml @@ -0,0 +1,67 @@ +# Vm base info configs +# +[base] +# Guest vm id. +id = 1 +# Guest vm name. +name = "linux-loongarch64-qemu-rootfs" +# Virtualization type. +vm_type = 1 +# The number of virtual CPUs. +cpu_num = 1 +# Guest vm physical cpu ids. +phys_cpu_ids = [0] + +# +# Vm kernel configs +# +[kernel] +# The entry point is replaced by the LoongArch ELF loader when vmlinux.elf is used. +entry_point = 0x0020_0000 +# The location of image: "memory" | "fs". +image_location = "fs" +# The file path of the kernel image. +kernel_path = "/guest/linux/qemu-loongarch64" +# The ELF LOAD paddr is used by the LoongArch loader; this is a fallback for flat images. +kernel_load_addr = 0x0020_0000 +# The file path of the device tree blob (DTB). +dtb_path = "/guest/linux/linux-loongarch64-qemu-rootfs-smp1.dtb" +# The load address of the device tree blob (DTB). +dtb_load_addr = 0x0010_0000 +# Kernel command line. Rootfs mode intentionally uses virtio-blk /dev/vda. +cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw init=/init console=ttyS0 earlycon=uart,mmio,0x1fe001e0 keep_bootcon nokaslr loglevel=8 ignore_loglevel pci=nomsi swiotlb=1024 initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" + +# Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`). +# For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`, 2 means `MAP_RESERVED`. +memory_regions = [ + [0x0008_0000, 0x0018_0000, 0x7, 2], # Low bootinfo/DTB RAM 512K-2M MAP_RESERVED + [0x0020_0000, 0x03e0_0000, 0x7, 2], # System RAM 2-64M MAP_RESERVED + [0x0400_0000, 0x0200_0000, 0x7, 2], # System RAM 64-96M MAP_RESERVED + [0x0600_0000, 0x0200_0000, 0x7, 2], # System RAM 96-128M MAP_RESERVED + [0x0800_0000, 0x0200_0000, 0x7, 2], # System RAM 128-160M MAP_RESERVED +] + +# +# Device specifications +# +[devices] +# The interrupt mode. +interrupt_mode = "passthrough" + +# Pass-through devices. +passthrough_devices = [ + ["/"], +] + +# Passthrough addresses. +# Base-GPA Length. +passthrough_addresses = [ +] + +# Devices that are not desired to be passed through to the guest +excluded_devices = [ +] + +# Emu_devices. +emu_devices = [ +] diff --git a/os/axvisor/scripts/quick-start.sh b/os/axvisor/scripts/quick-start.sh index 271da66a4a..98bf8eb6ca 100755 --- a/os/axvisor/scripts/quick-start.sh +++ b/os/axvisor/scripts/quick-start.sh @@ -111,7 +111,8 @@ Launch Options (for run/start commands): -a, --arceos Launch single ArceOS guest (default) QEMU LoongArch64: --axvisor Launch AxVisor shell smoke (default) - -l, --linux Launch single Linux guest + -l, --linux Launch single Linux guest with virtio-blk rootfs + --linux-rootfs Launch single Linux guest with virtio-blk rootfs QEMU x86_64: -n, --nimbos Launch single NimbOS guest (default) -l, --linux Launch single Linux guest @@ -142,7 +143,8 @@ Examples: # QEMU LoongArch64 $0 qemu-loongarch64 start --axvisor # One-step: prepare + launch AxVisor shell - $0 qemu-loongarch64 start --linux # One-step: prepare + launch Linux + $0 qemu-loongarch64 start --linux # One-step: launch Linux with virtio-blk rootfs + $0 qemu-loongarch64 start --linux-rootfs # Same as above $0 qemu-loongarch64 start # Same as above (default axvisor) # QEMU x86_64 @@ -319,16 +321,23 @@ setup_qemu_loongarch64() { info "Preparing board config file..." run_cmd cp configs/board/qemu-loongarch64.toml tmp/configs/ + run_cmd cp configs/board/qemu-loongarch64-guest-rootfs.toml tmp/configs/ info "Preparing Linux guest config file..." run_cmd cp configs/vms/linux-loongarch64-qemu-smp1.toml tmp/configs/ + run_cmd cp configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml tmp/configs/ run_cmd cp configs/vms/linux-loongarch64-qemu-smp1.dts tmp/configs/ + run_cmd cp configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts tmp/configs/ local guest_dir="${AXVISOR_LOONGARCH64_GUEST_DIR:-$(cd ../../.. && pwd)/axvisor-guest/IMAGES/qemu/loongarch64/linux}" - if [ -f "$guest_dir/qemu-loongarch64" ] && [ -f "$guest_dir/initramfs.cpio.gz" ]; then + if [ -f "$guest_dir/qemu-loongarch64" ]; then info "Using LoongArch Linux guest artifacts from: $guest_dir" run_cmd cp "$guest_dir/qemu-loongarch64" tmp/images/qemu_loongarch64_linux/ - run_cmd cp "$guest_dir/initramfs.cpio.gz" tmp/images/qemu_loongarch64_linux/ + if [ -f "$guest_dir/initramfs.cpio.gz" ]; then + run_cmd cp "$guest_dir/initramfs.cpio.gz" tmp/images/qemu_loongarch64_linux/ + else + warn "LoongArch Linux initramfs not found in: $guest_dir" + fi if [ -f "$guest_dir/rootfs.img" ]; then run_cmd cp "$guest_dir/rootfs.img" tmp/images/qemu_loongarch64_linux/ fi @@ -342,12 +351,17 @@ setup_qemu_loongarch64() { exit 1 fi run_cmd dtc -I dts -O dtb -o tmp/configs/linux-loongarch64-qemu-smp1.dtb tmp/configs/linux-loongarch64-qemu-smp1.dts + run_cmd dtc -I dts -O dtb -o tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dtb tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dts run_cmd cp tmp/configs/linux-loongarch64-qemu-smp1.dtb tmp/images/qemu_loongarch64_linux/ + run_cmd cp tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dtb tmp/images/qemu_loongarch64_linux/ run_cmd sed -i 's|^image_location = "fs"|image_location = "memory"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml run_cmd sed -i 's|^kernel_path = .*|kernel_path = "../images/qemu_loongarch64_linux/qemu-loongarch64"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml run_cmd sed -i 's|^dtb_path = .*|dtb_path = "linux-loongarch64-qemu-smp1.dtb"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml run_cmd sed -i 's|^ramdisk_path = .*|ramdisk_path = "../images/qemu_loongarch64_linux/initramfs.cpio.gz"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml + run_cmd sed -i 's|^image_location = "fs"|image_location = "memory"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml + run_cmd sed -i 's|^kernel_path = .*|kernel_path = "../images/qemu_loongarch64_linux/qemu-loongarch64"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml + run_cmd sed -i 's|^dtb_path = .*|dtb_path = "linux-loongarch64-qemu-rootfs-smp1.dtb"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml info "Preparing QEMU config file..." run_cmd cp configs/qemu/qemu-loongarch64.toml tmp/configs/qemu-loongarch64-runtime.toml @@ -419,19 +433,48 @@ ensure_loongarch64_host_rootfs() { run_cmd mkfs.ext4 -q -F "$rootfs" } +ensure_loongarch64_guest_rootfs() { + local workspace_root="$1" + local rootfs="$workspace_root/tmp/axbuild/rootfs/rootfs-loongarch64-alpine.img" + local source_rootfs="${AXVISOR_LOONGARCH64_ROOTFS:-$(pwd)/tmp/images/qemu_loongarch64_linux/rootfs.img}" + + run_cmd mkdir -p "$(dirname "$rootfs")" + + if [[ -f "$source_rootfs" ]]; then + info "Using LoongArch Linux guest rootfs image: $source_rootfs" + if [[ "$(realpath -m "$source_rootfs")" != "$(realpath -m "$rootfs")" ]]; then + run_cmd cp "$source_rootfs" "$rootfs" + fi + return 0 + fi + + error "LoongArch Linux rootfs image not found." + echo "Expected one of:" + echo " $source_rootfs" + echo " AXVISOR_LOONGARCH64_ROOTFS=/path/to/rootfs.img" + echo "" + echo "Build or provide rootfs.img in AXVISOR_LOONGARCH64_GUEST_DIR before using --linux." + exit 1 +} + run_qemu_loongarch64_linux() { - info "=== Launching QEMU LoongArch64 Linux Guest ===" + info "=== Launching QEMU LoongArch64 Linux Guest with virtio-blk rootfs ===" setup_qemu_loongarch64 local workspace_root workspace_root="$(cd ../.. && pwd)" - ensure_loongarch64_host_rootfs "$workspace_root" + ensure_loongarch64_guest_rootfs "$workspace_root" + run_cmd sed -i 's|virtio-blk-pci,drive=disk0|virtio-blk-pci,drive=disk0,disable-modern=on|g' tmp/configs/qemu-loongarch64-runtime.toml run_axvisor_qemu_with_loongarch64_qemu \ - --config "$(pwd)/tmp/configs/qemu-loongarch64.toml" \ + --config "$(pwd)/tmp/configs/qemu-loongarch64-guest-rootfs.toml" \ --qemu-config "$(pwd)/tmp/configs/qemu-loongarch64-runtime.toml" \ - --vmconfigs "$(pwd)/tmp/configs/linux-loongarch64-qemu-smp1.toml" + --vmconfigs "$(pwd)/tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml" +} + +run_qemu_loongarch64_linux_rootfs() { + run_qemu_loongarch64_linux } # ============================================================================ @@ -1120,6 +1163,9 @@ cmd_run_qemu_loongarch64() { -l|--linux) run_qemu_loongarch64_linux ;; + --linux-rootfs) + run_qemu_loongarch64_linux_rootfs + ;; -a|--arceos) error "Unsupported combination: QEMU LoongArch64 quick start does not launch an ArceOS guest yet" echo "" @@ -1150,7 +1196,8 @@ cmd_run_qemu_loongarch64() { echo "" echo "QEMU LoongArch64 platform supports the following options:" echo " --axvisor Launch AxVisor shell smoke" - echo " -l, --linux Launch Linux guest" + echo " -l, --linux Launch Linux guest with virtio-blk rootfs" + echo " --linux-rootfs Launch Linux guest with virtio-blk rootfs" exit 1 ;; esac @@ -1159,7 +1206,7 @@ cmd_run_qemu_loongarch64() { cmd_start_qemu_loongarch64() { local mode="$1" case "$mode" in - --axvisor|-l|--linux|"") + --axvisor|-l|--linux|--linux-rootfs|"") ;; *) cmd_run_qemu_loongarch64 "$mode" diff --git a/platforms/ax-plat-loongarch64-qemu-virt/axconfig.toml b/platforms/ax-plat-loongarch64-qemu-virt/axconfig.toml index 0894c4ddd6..46ef803a2c 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/axconfig.toml +++ b/platforms/ax-plat-loongarch64-qemu-virt/axconfig.toml @@ -34,9 +34,9 @@ phys-virt-offset = "0x9000_0000_0000_0000" # uint phys-bus-offset = 0 # uint # Base physical address of the kernel image. -kernel-base-paddr = 0x0020_0000 # uint +kernel-base-paddr = 0x8000_0000 # uint # Base virtual address of the kernel image. -kernel-base-vaddr = "0x9000_0000_0020_0000" # uint +kernel-base-vaddr = "0x9000_0000_8000_0000" # uint # Kernel page-table-backed address space. # # LoongArch64 uses the 0x9000_0000_0000_0000 DMW window for cached direct diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs index 5e3bad9630..d77b0cfa23 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs @@ -63,6 +63,17 @@ pub fn enable_irq(irq: usize) { iocsr_write_d(addr, iocsr_read_d(addr) | bit); } } + +#[cfg(feature = "hypervisor")] +pub fn debug_snapshot(irq: usize) -> (u64, u64, u64) { + let (offset, _) = split_bit(irq); + ( + iocsr_read_d(EIOINTC_REG_ENABLE + offset), + iocsr_read_d(EIOINTC_REG_BOUNCE + offset), + iocsr_read_d(EIOINTC_REG_ISR + offset), + ) +} + pub fn disable_irq(irq: usize) { let (offset, bit) = split_bit(irq); let addr = EIOINTC_REG_ENABLE + offset; @@ -80,8 +91,8 @@ pub fn claim_irq() -> Option { } /// Write back the ISR bit to acknowledge (clear) the interrupt. /// Must be called after claim_irq() to allow the EIOINTC to deliver -/// subsequent interrupts. Required in both native and hypervisor -/// modes. +/// subsequent interrupts. In hypervisor passthrough mode, the host must not +/// claim the IRQ first; the guest owns the claim/complete sequence. pub fn complete_irq(irq: usize) { let (offset, bit) = split_bit(irq); iocsr_write_d(EIOINTC_REG_ISR + offset, bit); diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/pch_pic.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/pch_pic.rs index 5925730bc0..8117728496 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/pch_pic.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/pch_pic.rs @@ -7,7 +7,10 @@ const PIC_REG_COUNT: usize = 2; const PIC_IRQ_COUNT: usize = PIC_COUNT_PER_REG * PIC_REG_COUNT; const PCH_PIC_MASK: usize = 0x20; +const PCH_PIC_HTMSI_EN: usize = 0x40; const PCH_PIC_EDGE: usize = 0x60; +const PCH_PIC_CLR: usize = 0x80; +const PCH_INT_ROUTE: usize = 0x100; const PCH_PIC_POL: usize = 0x3e0; const PCH_INT_HTVEC: usize = 0x200; @@ -24,12 +27,21 @@ fn write_w(addr: usize, val: u32) { } pub fn init() { - // High level triggered for i in 0..PIC_REG_COUNT { let offset = i * 4; write_w(PCH_PIC_MASK + offset, u32::MAX); + write_w(PCH_PIC_CLR + offset, u32::MAX); + // High level triggered. write_w(PCH_PIC_EDGE + offset, 0); write_w(PCH_PIC_POL + offset, 0); + write_w(PCH_PIC_HTMSI_EN + offset, u32::MAX); + } + + for irq in 0..(PIC_COUNT_PER_REG * PIC_REG_COUNT) { + unsafe { + ((MMIO_BASE + PCH_INT_ROUTE + irq) as *mut u8).write_volatile(1); + ((MMIO_BASE + PCH_INT_HTVEC + irq) as *mut u8).write_volatile(irq as _); + } } } @@ -41,6 +53,19 @@ const fn valid_irq(irq: usize) -> bool { irq < PIC_IRQ_COUNT } +#[cfg(feature = "hypervisor")] +pub fn debug_snapshot(irq: usize) -> (u32, u32, u32, u32, u8) { + let (offset, _) = split_bit(irq); + let htv = unsafe { ((MMIO_BASE + PCH_INT_HTVEC + irq) as *mut u8).read_volatile() }; + ( + read_w(PCH_PIC_MASK + offset), + read_w(PCH_PIC_HTMSI_EN + offset), + read_w(PCH_PIC_EDGE + offset), + read_w(PCH_PIC_POL + offset), + htv, + ) +} + pub fn enable_irq(irq: usize) { if !valid_irq(irq) { return; diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/mem.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/mem.rs index abbaccc3ea..76e96e89e4 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/mem.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/mem.rs @@ -155,7 +155,10 @@ impl MemIf for MemIfImpl { /// Note that the ranges returned should not include the range where the /// kernel is loaded. fn reserved_phys_ram_ranges() -> &'static [RawRange] { - &[(0, 0x200000)] // boot_info + fdt + // AxVisor is loaded from high memory on LoongArch. Keep the low RAM + // bank out of the host allocator so passthrough devices can DMA to + // guest identity-mapped low memory. + &[(LOW_MEMORY_BASE, LOW_MEMORY_SIZE)] } /// Returns all device memory (MMIO) ranges on the platform. diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/time.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/time.rs index c5fb292e5c..1f86bb4f78 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/time.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/time.rs @@ -123,11 +123,13 @@ impl TimeIf for TimeIfImpl { /// LoongArch64 TCFG CSR: #[cfg(feature = "irq")] fn set_oneshot_timer(deadline_ns: u64) { - use loongArch64::register::tcfg; + use loongArch64::register::{tcfg, ticlr}; let ticks_now = Self::current_ticks(); let ticks_deadline = Self::nanos_to_ticks(deadline_ns); let init_value = ticks_deadline.saturating_sub(ticks_now).max(1); + ticlr::clear_timer_interrupt(); + tcfg::set_periodic(false); tcfg::set_init_val(init_value as _); tcfg::set_en(true); } diff --git a/virtualization/axvcpu/src/exit.rs b/virtualization/axvcpu/src/exit.rs index 3014a8f4d5..439e2a03c1 100644 --- a/virtualization/axvcpu/src/exit.rs +++ b/virtualization/axvcpu/src/exit.rs @@ -180,39 +180,6 @@ pub enum AxVCpuExitReason { access_flags: MappingFlags, }, - /// A guest memory access needs to be completed by the VM layer. - /// - /// Some architecture-specific instructions can trap before the guest has - /// installed its own exception vectors. The VCPU decodes the instruction, - /// while the VM owns the stage-2 address space needed to perform the access. - GuestMemoryRead { - /// Guest physical address being read from. - addr: GuestPhysAddr, - /// Width/size of the memory access. - width: AccessWidth, - /// Index of the guest register that will receive the read value. - reg: usize, - /// Whether to sign-extend the read value to fill the register. - signed_ext: bool, - }, - - /// A guest memory write needs to be completed by the VM layer. - GuestMemoryWrite { - /// Guest physical address being written to. - addr: GuestPhysAddr, - /// Width/size of the memory access. - width: AccessWidth, - /// Data being written to the memory location. - data: u64, - }, - - /// The VCPU needs the VM layer to fetch a guest instruction before it can - /// complete architecture-specific instruction emulation. - GuestInstructionFetch { - /// Guest physical address of the instruction. - addr: GuestPhysAddr, - }, - /// The guest VCpu has executed a halt instruction and is now idle. /// /// This typically occurs when the guest OS has no work to do and is diff --git a/virtualization/axvcpu/src/vcpu.rs b/virtualization/axvcpu/src/vcpu.rs index c1a5843acb..0b9656cdc1 100644 --- a/virtualization/axvcpu/src/vcpu.rs +++ b/virtualization/axvcpu/src/vcpu.rs @@ -336,21 +336,9 @@ impl AxVCpu { hpa: HostPhysAddr, access_flags: axaddrspace::MappingFlags, page_size: ax_page_table_multiarch::PageSize, - pair_mapping: Option<(HostPhysAddr, axaddrspace::MappingFlags)>, ) -> AxResult { - self.get_arch_vcpu().handle_nested_page_mapping( - gpa, - hpa, - access_flags, - page_size, - pair_mapping, - ) - } - - /// Completes architecture-specific instruction emulation after fetching - /// the instruction bytes from guest memory. - pub fn handle_fetched_guest_instruction(&self, ins: u32) -> AxResult> { - self.get_arch_vcpu().handle_fetched_guest_instruction(ins) + self.get_arch_vcpu() + .handle_nested_page_mapping(gpa, hpa, access_flags, page_size) } } diff --git a/virtualization/loongarch_vcpu/src/context_frame.rs b/virtualization/loongarch_vcpu/src/context_frame.rs index 6e4898afb5..7e85cb8815 100644 --- a/virtualization/loongarch_vcpu/src/context_frame.rs +++ b/virtualization/loongarch_vcpu/src/context_frame.rs @@ -111,10 +111,6 @@ pub struct LoongArchContextFrame { pub host_badi: usize, pub host_tlbrbadv: usize, pub host_tlbrera: usize, - pub guest_pc: usize, - pub entry_host_era: usize, - pub entry_guest_era: usize, - pub entry_gstat: usize, } impl LoongArchContextFrame { @@ -220,10 +216,6 @@ impl fmt::Display for LoongArchContextFrame { writeln!(f, "host_badv: {:016x}", self.host_badv)?; writeln!(f, "host_badi: {:016x}", self.host_badi)?; writeln!(f, "host_tlbrbadv: {:016x}", self.host_tlbrbadv)?; - writeln!(f, "host_tlbrera: {:016x}", self.host_tlbrera)?; - writeln!(f, "guest_pc: {:016x}", self.guest_pc)?; - writeln!(f, "entry_host_era: {:016x}", self.entry_host_era)?; - writeln!(f, "entry_guest_era: {:016x}", self.entry_guest_era)?; - write!(f, "entry_gstat: {:016x}", self.entry_gstat) + write!(f, "host_tlbrera: {:016x}", self.host_tlbrera) } } diff --git a/virtualization/loongarch_vcpu/src/exception.S b/virtualization/loongarch_vcpu/src/exception.S index 45d5e6ddc2..922511727c 100644 --- a/virtualization/loongarch_vcpu/src/exception.S +++ b/virtualization/loongarch_vcpu/src/exception.S @@ -5,6 +5,7 @@ .equ CSR_CRMD, 0x0 .equ CSR_PRMD, 0x1 .equ CSR_ECFG, 0x4 +.equ CSR_BADI, 0x8 .equ CSR_SAVE0, 0x30 .equ CSR_SAVE1, 0x31 .equ CSR_PGD, 0x1b @@ -26,7 +27,7 @@ st.d $r0, $sp, 0 st.d $r1, $sp, 8 st.d $r2, $sp, 16 - csrrd $t0, CSR_SAVE0 + csrrd $t0, 0x502 st.d $t0, $sp, 24 st.d $r4, $sp, 32 st.d $r5, $sp, 40 @@ -36,7 +37,7 @@ st.d $r9, $sp, 72 st.d $r10, $sp, 80 st.d $r11, $sp, 88 - csrrd $t0, CSR_TLBRSAVE + csrrd $t0, CSR_SAVE0 st.d $t0, $sp, 96 st.d $r13, $sp, 104 st.d $r14, $sp, 112 @@ -148,8 +149,11 @@ st.d $t0, $sp, 600 gcsrrd $t0, 0x41 st.d $t0, $sp, 608 - gcsrrd $t0, 0x42 - st.d $t0, $sp, 616 + /* + * Keep the software timer's logical TVAL in the Rust context. QEMU-LVZ + * reuses GCSR_TVAL as a pause/resume remaining-ticks value while the guest + * is stopped, so snapshotting it here pollutes the emulated guest timer. + */ gcsrrd $t0, 0x43 st.d $t0, $sp, 624 gcsrrd $t0, 0x44 @@ -187,11 +191,11 @@ st.d $t0, $sp, 752 csrrd $t0, 0x7 st.d $t0, $sp, 760 - csrrd $t0, 0x8 + csrrd $t0, CSR_BADI st.d $t0, $sp, 768 csrrd $t0, 0x89 st.d $t0, $sp, 776 - csrrd $t0, 0x8a + csrrd $t0, CSR_TLBRERA st.d $t0, $sp, 784 .endm @@ -235,11 +239,17 @@ ori $t1, $t1, CSR_GTLBC_TGID0 csrwr $t1, CSR_GTLBC + li.d $t0, CSR_GSTAT_PVM + csrxchg $t0, $t0, CSR_GSTAT + + csrrd $t0, CSR_ECFG + ori $t0, $t0, CSR_TIMER_IE + csrwr $t0, CSR_ECFG .endm .macro RESTORE_GUEST_REGS ld.d $t0, $sp, 24 - csrwr $t0, CSR_SAVE0 + csrwr $t0, 0x502 ld.d $t0, $sp, 256 csrwr $t0, 0x6 @@ -336,10 +346,9 @@ ld.d $t0, $sp, 608 gcsrwr $t0, 0x41 /* - * Do not restore GCSR_TVAL. QEMU-LVZ treats TVAL as the remaining - * ticks snapshot while guest mode is paused; writing it back on every - * VM entry re-bases a relative timer and keeps pushing the guest timer - * deadline into the future. + * QEMU-LVZ stores GCSR_TVAL as remaining ticks while guest mode is + * paused. Rewriting it on every VM entry re-bases the relative guest + * timer and can keep pushing one-shot deadlines into the future. */ ld.d $t0, $sp, 624 gcsrwr $t0, 0x43 @@ -371,7 +380,6 @@ gcsrwr $t0, 0x182 ld.d $t0, $sp, 736 gcsrwr $t0, 0x183 - ld.d $t0, $sp, 256 csrwr $t0, 0x6 csrrd $t1, CSR_TLBRERA @@ -383,16 +391,6 @@ and $t1, $t1, $t0 csrwr $t1, CSR_TLBRPRMD - li.d $t0, CSR_GSTAT_PVM - csrxchg $t0, $t0, CSR_GSTAT - - csrrd $t0, 0x6 - st.d $t0, $sp, 800 - gcsrrd $t0, 0x6 - st.d $t0, $sp, 808 - csrrd $t0, CSR_GSTAT - st.d $t0, $sp, 816 - ld.d $r1, $sp, 8 ld.d $r2, $sp, 16 ld.d $r4, $sp, 32 @@ -424,13 +422,13 @@ ld.d $r30, $sp, 240 ld.d $r31, $sp, 248 ld.d $r0, $sp, 0 - csrrd $sp, CSR_SAVE0 + csrrd $sp, 0x502 .endm .global _run_guest _run_guest: move $t1, $ra - addi.d $t0, $a0, 832 + addi.d $t0, $a0, 792 csrwr $t0, 0x33 move $sp, $a0 PREPARE_GUEST_ENTRY @@ -465,62 +463,170 @@ _guest_tlb_refill_vector: .Lguest_stage2_tlb_invalid: csrrd $t0, CSR_TLBRSAVE - csrwr $t0, CSR_TLBRSAVE + csrwr $t0, CSR_SAVE0 DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 - csrwr $sp, CSR_SAVE0 + csrwr $sp, 0x502 csrrd $sp, 0x33 - addi.d $sp, $sp, -832 + addi.d $sp, $sp, -792 SAVE_GUEST_REGS ENTER_HOST_MODE li.d $a0, 0 b _guest_exit -.section .text.vectors, "ax" -.balign 0x10000 +.section .vectors, "ax" +.align 12 .global _exception_vectors _exception_vectors: - .set __vec_slot, 0 - .rept 512 - .org __vec_slot * 0x80 - .if __vec_slot == 0 - b _irq_handler_vector - .elseif __vec_slot >= 64 - b _irq_handler_vector - .else - b _sync_handler_vector - .endif - .set __vec_slot, __vec_slot + 1 - .endr - .org 0x10000 + .org 0x0 + b _irq_handler_vector + .org 0x80 + b _sync_handler_vector + .org 0x100 + b _sync_handler_vector + .org 0x180 + b _sync_handler_vector + .org 0x200 + b _sync_handler_vector + .org 0x280 + b _sync_handler_vector + .org 0x400 + b _sync_handler_vector + .org 0x480 + b _sync_handler_vector + .org 0x500 + b _sync_handler_vector + .org 0x580 + b _sync_handler_vector + .org 0x600 + b _sync_handler_vector + .org 0x680 + b _sync_handler_vector + .org 0x700 + b _sync_handler_vector + .org 0x780 + b _sync_handler_vector + .org 0x800 + b _sync_handler_vector + .org 0x880 + b _sync_handler_vector + .org 0x900 + b _sync_handler_vector + .org 0x980 + b _sync_handler_vector + .org 0xa00 + b _sync_handler_vector + .org 0xa80 + b _sync_handler_vector + .org 0xb00 + b _hvc_handler_vector + .org 0xb80 + b _sync_handler_vector + .org 0xc00 + b _sync_handler_vector + .org 0xc80 + b _sync_handler_vector + .org 0xd00 + b _sync_handler_vector + .org 0xd80 + b _sync_handler_vector + + /* + * Hardware interrupts use EENTRY + (64 + vector) * vec_size. With VS=5 + * each slot is 0x80 bytes, so local interrupt 11 (timer) lands at 0x2580. + */ + .org 0x2000 + b _irq_handler_vector + .org 0x2080 + b _irq_handler_vector + .org 0x2100 + b _irq_handler_vector + .org 0x2180 + b _irq_handler_vector + .org 0x2200 + b _irq_handler_vector + .org 0x2280 + b _irq_handler_vector + .org 0x2300 + b _irq_handler_vector + .org 0x2380 + b _irq_handler_vector + .org 0x2400 + b _irq_handler_vector + .org 0x2480 + b _irq_handler_vector + .org 0x2500 + b _irq_handler_vector + .org 0x2580 + b _irq_handler_vector + .org 0x2600 + b _irq_handler_vector + .org 0x2680 + b _irq_handler_vector + .org 0x2700 + b _irq_handler_vector + .org 0x2780 + b _irq_handler_vector + .org 0x2800 + b _irq_handler_vector + .org 0x2880 + b _irq_handler_vector + .org 0x2900 + b _irq_handler_vector + .org 0x2980 + b _irq_handler_vector + .org 0x2a00 + b _irq_handler_vector + .org 0x2a80 + b _irq_handler_vector + .org 0x2b00 + b _irq_handler_vector + .org 0x2b80 + b _irq_handler_vector + .org 0x2c00 + b _irq_handler_vector + .org 0x2c80 + b _irq_handler_vector + .org 0x2d00 + b _irq_handler_vector + .org 0x2d80 + b _irq_handler_vector + .org 0x2e00 + b _irq_handler_vector + .org 0x2e80 + b _irq_handler_vector + .org 0x2f00 + b _irq_handler_vector + .org 0x2f80 + b _irq_handler_vector _irq_handler_vector: - csrwr $t0, CSR_TLBRSAVE + csrwr $t0, CSR_SAVE0 DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 - csrwr $sp, CSR_SAVE0 + csrwr $sp, 0x502 csrrd $sp, 0x33 - addi.d $sp, $sp, -832 + addi.d $sp, $sp, -792 SAVE_GUEST_REGS ENTER_HOST_MODE li.d $a0, 1 b _guest_exit _sync_handler_vector: - csrwr $t0, CSR_TLBRSAVE + csrwr $t0, CSR_SAVE0 DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 - csrwr $sp, CSR_SAVE0 + csrwr $sp, 0x502 csrrd $sp, 0x33 - addi.d $sp, $sp, -832 + addi.d $sp, $sp, -792 SAVE_GUEST_REGS ENTER_HOST_MODE li.d $a0, 0 b _guest_exit _hvc_handler_vector: - csrwr $t0, CSR_TLBRSAVE + csrwr $t0, CSR_SAVE0 DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 - csrwr $sp, CSR_SAVE0 + csrwr $sp, 0x502 csrrd $sp, 0x33 - addi.d $sp, $sp, -832 + addi.d $sp, $sp, -792 SAVE_GUEST_REGS ENTER_HOST_MODE li.d $a0, 0 diff --git a/virtualization/loongarch_vcpu/src/lib.rs b/virtualization/loongarch_vcpu/src/lib.rs index 722f7e5c90..4e8fb84dbe 100644 --- a/virtualization/loongarch_vcpu/src/lib.rs +++ b/virtualization/loongarch_vcpu/src/lib.rs @@ -1,6 +1,8 @@ #![no_std] #![allow(unsafe_op_in_unsafe_fn)] +extern crate alloc; + mod context_frame; mod exception; pub mod host; diff --git a/virtualization/loongarch_vcpu/src/registers.rs b/virtualization/loongarch_vcpu/src/registers.rs index 10f2f123ba..cc74167782 100644 --- a/virtualization/loongarch_vcpu/src/registers.rs +++ b/virtualization/loongarch_vcpu/src/registers.rs @@ -1,11 +1,16 @@ +use core::sync::atomic::{AtomicUsize, Ordering}; + use ax_kspin::SpinNoIrq as Mutex; pub const CSR_GSTAT: u16 = 0x50; +pub const CSR_CRMD: u16 = 0x0; +pub const CSR_PRMD: u16 = 0x1; pub const CSR_EENTRY: u16 = 0x0c; pub const CSR_TLBIDX: u16 = 0x10; pub const CSR_TLBEHI: u16 = 0x11; pub const CSR_TLBELO0: u16 = 0x12; pub const CSR_TLBELO1: u16 = 0x13; +pub const CSR_ASID: u16 = 0x18; pub const CSR_GCTL: u16 = 0x51; pub const CSR_GTLBC: u16 = 0x15; pub const CSR_GINTC: u16 = 0x52; @@ -18,7 +23,9 @@ pub const CSR_TLBRENTRY: u16 = 0x88; pub const CSR_TLBRELO0: u16 = 0x8c; pub const CSR_TLBRELO1: u16 = 0x8d; pub const CSR_TLBREHI: u16 = 0x8e; +pub const CSR_TLBRERA: u16 = 0x8a; pub const CSR_ECFG: u16 = 0x4; +pub const CSR_KSAVE_KSP: u16 = 0x30; pub const GCSR_ESTAT: usize = 0x5; pub const GCSR_EENTRY: usize = 0x0c; @@ -34,6 +41,7 @@ pub const INT_TIMER: usize = 11; pub const INT_IPI: usize = 12; static INJECT_INT_LOCK: Mutex<()> = Mutex::new(()); +static INJECT_INT_LOGS: AtomicUsize = AtomicUsize::new(0); #[cfg(target_arch = "loongarch64")] #[inline(always)] @@ -53,7 +61,7 @@ pub(crate) unsafe fn csr_read() -> usize { #[cfg(target_arch = "loongarch64")] #[inline(always)] pub(crate) unsafe fn csr_write(value: usize) { - core::arch::asm!("csrwr {}, {}", in(reg) value, const CSR_NUM); + core::arch::asm!("csrwr {}, {}", inout(reg) value => _, const CSR_NUM); } #[cfg(not(target_arch = "loongarch64"))] @@ -80,7 +88,7 @@ pub(crate) unsafe fn gcsr_read() -> usize { #[cfg(target_arch = "loongarch64")] #[inline(always)] pub(crate) unsafe fn gcsr_write(value: usize) { - core::arch::asm!("gcsrwr {}, {}", in(reg) value, const GCSR_NUM); + core::arch::asm!("gcsrwr {}, {}", inout(reg) value => _, const GCSR_NUM); } #[cfg(not(target_arch = "loongarch64"))] @@ -260,6 +268,14 @@ pub fn inject_interrupt(vector: usize) { unsafe { if (INT_HWI0..=INT_HWI7).contains(&vector) { + if INJECT_INT_LOGS.fetch_add(1, Ordering::Relaxed) < 16 { + log::info!( + "LoongArch vcpu pulse HWI: vector={}, gintc_before={:#x}, hwis_before={:#x}", + vector, + read_gintc(), + current_hwis() + ); + } pulse_hwi(vector); } else { let estat = gcsr_read::(); From 76d9f2bfd04d95be15ede3670bd2261988c0d319 Mon Sep 17 00:00:00 2001 From: szy Date: Wed, 3 Jun 2026 13:25:32 +0800 Subject: [PATCH 05/50] opt --- virtualization/loongarch_vcpu/src/registers.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/virtualization/loongarch_vcpu/src/registers.rs b/virtualization/loongarch_vcpu/src/registers.rs index cc74167782..5cd14a4a88 100644 --- a/virtualization/loongarch_vcpu/src/registers.rs +++ b/virtualization/loongarch_vcpu/src/registers.rs @@ -269,7 +269,7 @@ pub fn inject_interrupt(vector: usize) { unsafe { if (INT_HWI0..=INT_HWI7).contains(&vector) { if INJECT_INT_LOGS.fetch_add(1, Ordering::Relaxed) < 16 { - log::info!( + log::debug!( "LoongArch vcpu pulse HWI: vector={}, gintc_before={:#x}, hwis_before={:#x}", vector, read_gintc(), From 60d342dd1b96786e426a489fa8709847a553d5dc Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 4 Jun 2026 10:57:40 +0800 Subject: [PATCH 06/50] optimize quick start --- .../loongarch/linux-direct-boot-analysis.md | 8 ++-- os/axvisor/doc/loongarch/rootfs-virtio-blk.md | 45 ++++++++----------- os/axvisor/doc/qemu-quickstart.md | 2 +- os/axvisor/doc/qemu-quickstart_cn.md | 2 +- os/axvisor/scripts/quick-start.sh | 17 +------ 5 files changed, 27 insertions(+), 47 deletions(-) diff --git a/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md b/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md index 18c99fdd34..bdb7e03ef8 100644 --- a/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md +++ b/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md @@ -1,6 +1,6 @@ # LoongArch Linux Direct Boot -本文只记录 LoongArch Linux direct boot 问题：Axvisor 不经过 guest UEFI/bootloader，直接把 Linux kernel、cmdline、DTB/initrd 信息放到 guest 可见的位置，然后跳到 Linux entry。 +本文只记录 LoongArch Linux direct boot 问题：Axvisor 不经过 guest UEFI/bootloader，直接把 Linux kernel、cmdline、DTB 等启动信息放到 guest 可见的位置，然后跳到 Linux entry。 ## 这个文件是什么 @@ -15,7 +15,7 @@ ```text VM TOML -> ImageLoader 加载 LoongArch ELF kernel - -> 加载 DTB 和 initramfs + -> 加载 DTB -> setup_bootinfo 构造 LoongArch Linux bootinfo -> 设置 guest boot_args -> vCPU 进入 Linux entry @@ -70,7 +70,7 @@ config.cpu_config.boot_args = [1, CMDLINE_GPA, SYSTAB_GPA]; - EFI system table； - EFI config table； - EFI memory map； -- initrd table； +- optional initrd table； - optional DTB pointer。 ## Cmdline 原则 @@ -82,7 +82,7 @@ config.cpu_config.boot_args = [1, CMDLINE_GPA, SYSTAB_GPA]; - `kernel.cmdline` 缺失时直接报错； - 缺少 `console=` 只 warning； - 缺少 `init=` / `rdinit=` 只 warning； -- rootfs 方式由配置决定。 +- quick-start 当前只维护 `root=/dev/vda` 的 virtio-blk rootfs 方式。 这样可以确保使用者能从配置文件明确知道 guest 是如何启动的。 diff --git a/os/axvisor/doc/loongarch/rootfs-virtio-blk.md b/os/axvisor/doc/loongarch/rootfs-virtio-blk.md index 5b296363c4..ec42a5c07d 100644 --- a/os/axvisor/doc/loongarch/rootfs-virtio-blk.md +++ b/os/axvisor/doc/loongarch/rootfs-virtio-blk.md @@ -1,31 +1,31 @@ # LoongArch Rootfs And Virtio Block -本文只记录 LoongArch Linux guest rootfs 方式，以及为什么当前 quick-start 先使用 initramfs 而不是 virtio-blk 磁盘 rootfs。 +本文记录 LoongArch Linux guest 在 QEMU quick-start 中使用 virtio-blk 磁盘 rootfs 的方式。 ## 当前方式 -当前 LoongArch Linux quick-start 使用 ramdisk/initramfs 作为 guest rootfs： +当前 LoongArch Linux quick-start 只支持 virtio-blk rootfs。VM 配置使用： ```toml -ramdisk_path = "/guest/linux/initramfs.cpio.gz" -ramdisk_load_addr = 0x0700_0000 -cmdline = "root=/dev/ram rw console=ttyS0 ... init=/init ... pci=off ..." +dtb_path = "/guest/linux/linux-loongarch64-qemu-rootfs-smp1.dtb" +cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw init=/init console=ttyS0 ..." ``` 启动路径是： ```text -Axvisor 加载 initramfs 到 guest 内存 - -> LoongArch bootinfo 传递 initrd base/size - -> Linux 解包内存中的 initramfs - -> 执行 /init +Axvisor 加载 LoongArch Linux kernel 和 DTB + -> setup_bootinfo 构造 LoongArch Linux bootinfo + -> QEMU 暴露 virtio-blk rootfs 磁盘 + -> Linux 枚举 virtio-blk 并挂载 /dev/vda + -> 执行 rootfs 中的 /init ``` -这条路径不依赖 guest 块设备。 +这条路径依赖 guest 侧 virtio-blk 设备链路，quick-start 不再准备 initramfs 配置。 -## 磁盘 rootfs 需要的链路 +## Rootfs 设备链路 -如果改成磁盘 rootfs，典型 cmdline 是： +典型 cmdline 是： ```text root=/dev/vda rw console=ttyS0 @@ -44,11 +44,11 @@ Linux virtio-blk driver -> mount /dev/vda ``` -当前 LoongArch quick-start 没有把这条链路作为可靠启动路径。 +当前 LoongArch quick-start 已经把这条链路作为 Linux guest 的唯一启动路径。 -## 当前绕开的内容 +## Initramfs 状态 -使用 initramfs 主要绕开： +initramfs 曾用于早期 bring-up，用来绕开： - guest PCI 枚举； - virtio-blk device discovery； @@ -57,19 +57,12 @@ Linux virtio-blk driver - 外部设备中断注入 guest； - guest idle 后等待设备中断唤醒。 -QEMU runtime 配置里可以挂载： +现在 quick-start 已经切换到 rootfs，`--linux` 和 `--linux-rootfs` 都使用 `linux-loongarch64-qemu-rootfs-smp1.toml`。仓库里的通用 ramdisk/initrd 加载逻辑仍可被其他配置使用，但 LoongArch QEMU quick-start 不再维护 initramfs 作为启动模式。 + +QEMU runtime 配置中挂载： ```toml "virtio-blk-pci,drive=disk0" ``` -但当前 guest cmdline 使用 `root=/dev/ram` 并带有 `pci=off`，因此 Linux guest 启动 rootfs 时不会依赖 `/dev/vda`。 - -## 后续工作 - -1. 去掉 `pci=off`，确认 guest 能枚举 PCI host bridge。 -2. 确认 virtio-blk 设备能在 guest 中出现为 `/dev/vda`。 -3. 使用只读 rootfs 验证基本读 I/O。 -4. 验证 legacy IRQ/MSI 的注入和完成路径。 -5. 确认 guest idle 时，virtio-blk 完成中断能唤醒 vCPU。 -6. 将 cmdline 切换到 `root=/dev/vda rw`。 +VM cmdline 使用 `root=/dev/vda`，因此 Linux guest 启动依赖 virtio-blk rootfs。 diff --git a/os/axvisor/doc/qemu-quickstart.md b/os/axvisor/doc/qemu-quickstart.md index dbb0f96c96..cf0d628c53 100644 --- a/os/axvisor/doc/qemu-quickstart.md +++ b/os/axvisor/doc/qemu-quickstart.md @@ -187,7 +187,7 @@ This command launches AxVisor directly and enters the built-in shell instead of Success indicator: `Welcome to AxVisor Shell!` appears in the output. -For the Linux guest flow, run: +For the Linux guest flow with a virtio-blk rootfs, run: ```bash ./scripts/quick-start.sh qemu-loongarch64 run --linux diff --git a/os/axvisor/doc/qemu-quickstart_cn.md b/os/axvisor/doc/qemu-quickstart_cn.md index 235f4a4079..6f5d93292a 100644 --- a/os/axvisor/doc/qemu-quickstart_cn.md +++ b/os/axvisor/doc/qemu-quickstart_cn.md @@ -145,7 +145,7 @@ cargo xtask qemu \ 启动成功标志：输出中出现 `Welcome to AxVisor Shell!` -Linux guest 启动使用： +Linux guest 启动使用 virtio-blk rootfs： ```bash ./scripts/quick-start.sh qemu-loongarch64 run --linux diff --git a/os/axvisor/scripts/quick-start.sh b/os/axvisor/scripts/quick-start.sh index 98bf8eb6ca..2902bd5619 100755 --- a/os/axvisor/scripts/quick-start.sh +++ b/os/axvisor/scripts/quick-start.sh @@ -323,21 +323,14 @@ setup_qemu_loongarch64() { run_cmd cp configs/board/qemu-loongarch64.toml tmp/configs/ run_cmd cp configs/board/qemu-loongarch64-guest-rootfs.toml tmp/configs/ - info "Preparing Linux guest config file..." - run_cmd cp configs/vms/linux-loongarch64-qemu-smp1.toml tmp/configs/ + info "Preparing Linux guest rootfs config file..." run_cmd cp configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml tmp/configs/ - run_cmd cp configs/vms/linux-loongarch64-qemu-smp1.dts tmp/configs/ run_cmd cp configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts tmp/configs/ local guest_dir="${AXVISOR_LOONGARCH64_GUEST_DIR:-$(cd ../../.. && pwd)/axvisor-guest/IMAGES/qemu/loongarch64/linux}" if [ -f "$guest_dir/qemu-loongarch64" ]; then info "Using LoongArch Linux guest artifacts from: $guest_dir" run_cmd cp "$guest_dir/qemu-loongarch64" tmp/images/qemu_loongarch64_linux/ - if [ -f "$guest_dir/initramfs.cpio.gz" ]; then - run_cmd cp "$guest_dir/initramfs.cpio.gz" tmp/images/qemu_loongarch64_linux/ - else - warn "LoongArch Linux initramfs not found in: $guest_dir" - fi if [ -f "$guest_dir/rootfs.img" ]; then run_cmd cp "$guest_dir/rootfs.img" tmp/images/qemu_loongarch64_linux/ fi @@ -347,18 +340,12 @@ setup_qemu_loongarch64() { fi if ! command -v dtc &> /dev/null; then - error "dtc is required to build linux-loongarch64-qemu-smp1.dtb" + error "dtc is required to build linux-loongarch64-qemu-rootfs-smp1.dtb" exit 1 fi - run_cmd dtc -I dts -O dtb -o tmp/configs/linux-loongarch64-qemu-smp1.dtb tmp/configs/linux-loongarch64-qemu-smp1.dts run_cmd dtc -I dts -O dtb -o tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dtb tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dts - run_cmd cp tmp/configs/linux-loongarch64-qemu-smp1.dtb tmp/images/qemu_loongarch64_linux/ run_cmd cp tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dtb tmp/images/qemu_loongarch64_linux/ - run_cmd sed -i 's|^image_location = "fs"|image_location = "memory"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml - run_cmd sed -i 's|^kernel_path = .*|kernel_path = "../images/qemu_loongarch64_linux/qemu-loongarch64"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml - run_cmd sed -i 's|^dtb_path = .*|dtb_path = "linux-loongarch64-qemu-smp1.dtb"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml - run_cmd sed -i 's|^ramdisk_path = .*|ramdisk_path = "../images/qemu_loongarch64_linux/initramfs.cpio.gz"|g' tmp/configs/linux-loongarch64-qemu-smp1.toml run_cmd sed -i 's|^image_location = "fs"|image_location = "memory"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml run_cmd sed -i 's|^kernel_path = .*|kernel_path = "../images/qemu_loongarch64_linux/qemu-loongarch64"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml run_cmd sed -i 's|^dtb_path = .*|dtb_path = "linux-loongarch64-qemu-rootfs-smp1.dtb"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml From fcf5d0edf89c11770b01004c734c2725498d8f4a Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 4 Jun 2026 14:08:02 +0800 Subject: [PATCH 07/50] fix(axvisor): restore loongarch rootfs boot after dev rebase --- os/axvisor/src/config.rs | 4 + os/axvisor/src/fdt/mod.rs | 6 +- os/axvisor/src/images/loongarch_elf.rs | 165 ++++++++++++++++ os/axvisor/src/images/loongarch_linux.rs | 230 ++++++++++++++++++++++ os/axvisor/src/images/mod.rs | 61 +++++- virtualization/axvcpu/src/vcpu.rs | 12 -- virtualization/axvm/src/config.rs | 6 + virtualization/axvm/src/vm.rs | 2 + virtualization/loongarch_vcpu/src/vcpu.rs | 24 ++- 9 files changed, 486 insertions(+), 24 deletions(-) create mode 100644 os/axvisor/src/images/loongarch_elf.rs create mode 100644 os/axvisor/src/images/loongarch_linux.rs diff --git a/os/axvisor/src/config.rs b/os/axvisor/src/config.rs index f9019e52e0..c5088a46f3 100644 --- a/os/axvisor/src/config.rs +++ b/os/axvisor/src/config.rs @@ -221,6 +221,10 @@ pub(crate) fn build_axvm_config(cfg: &AxVMCrateConfig) -> AxVMConfig { cpu_config: AxVCpuConfig { bsp_entry: GuestPhysAddr::from(cfg.kernel.entry_point), ap_entry: GuestPhysAddr::from(cfg.kernel.entry_point), + #[cfg(target_arch = "loongarch64")] + boot_args: [0; 3], + #[cfg(target_arch = "loongarch64")] + boot_stack_top: 0, }, image_config: VMImageConfig { kernel_load_gpa: GuestPhysAddr::from(cfg.kernel.kernel_load_addr), diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index 448a67e30c..16e51cb2ee 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -29,11 +29,7 @@ use ax_errno::{AxResult, ax_err_type}; use ax_kspin::SpinNoIrq as Mutex; use ax_lazyinit::LazyInit; // pub use print::print_fdt; -#[cfg(any( - target_arch = "aarch64", - target_arch = "loongarch64", - target_arch = "riscv64" -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub use create::update_fdt; pub use device::build_all_node_paths; use fdt_parser::Fdt; diff --git a/os/axvisor/src/images/loongarch_elf.rs b/os/axvisor/src/images/loongarch_elf.rs new file mode 100644 index 0000000000..0dea55a657 --- /dev/null +++ b/os/axvisor/src/images/loongarch_elf.rs @@ -0,0 +1,165 @@ +use ax_errno::{AxResult, ax_err_type}; +use axvm::{AxVMRef, GuestPhysAddr}; + +use crate::images::{load_vm_image_from_memory, zero_vm_memory}; + +const ELF_MAGIC: &[u8; 4] = b"\x7fELF"; +const ELF_CLASS_64: u8 = 2; +const ELF_DATA_LE: u8 = 1; +const EM_LOONGARCH: u16 = 258; +const PT_LOAD: u32 = 1; +const LOONGARCH_DMW_MASK: u64 = (1u64 << 48) - 1; + +#[derive(Clone, Copy, Debug)] +pub struct ElfInfo { + pub entry: GuestPhysAddr, +} + +#[derive(Clone, Copy, Debug)] +struct ProgramHeader { + p_type: u32, + p_offset: u64, + p_paddr: u64, + p_filesz: u64, + p_memsz: u64, +} + +pub fn try_load(image: &[u8], vm: AxVMRef) -> AxResult> { + let Some(header) = Header::parse(image)? else { + return Ok(None); + }; + + for idx in 0..header.e_phnum { + let ph = read_program_header(image, &header, idx)?; + if ph.p_type != PT_LOAD || ph.p_memsz == 0 { + continue; + } + + let file_start = ph.p_offset as usize; + let file_size = ph.p_filesz as usize; + let file_end = file_start.checked_add(file_size).ok_or_else(|| { + ax_err_type!( + InvalidInput, + "LoongArch ELF LOAD segment file range overflows usize" + ) + })?; + let mem_size = ph.p_memsz as usize; + if file_end > image.len() { + return Err(ax_err_type!( + InvalidInput, + format!( + "LoongArch ELF LOAD segment exceeds image size: offset {:#x}, filesz {:#x}, image {:#x}", + ph.p_offset, + ph.p_filesz, + image.len() + ) + )); + } + if ph.p_filesz > ph.p_memsz { + return Err(ax_err_type!( + InvalidInput, + "LoongArch ELF LOAD segment filesz is larger than memsz" + )); + } + + let load_gpa = GuestPhysAddr::from((ph.p_paddr & LOONGARCH_DMW_MASK) as usize); + info!( + "Loading LoongArch ELF segment: paddr={:#x} -> gpa={:#x}, filesz={:#x}, memsz={:#x}", + ph.p_paddr, + load_gpa.as_usize(), + ph.p_filesz, + ph.p_memsz + ); + + zero_vm_memory(load_gpa, mem_size, vm.clone())?; + load_vm_image_from_memory(&image[file_start..file_end], load_gpa, vm.clone())?; + } + + Ok(Some(ElfInfo { + entry: GuestPhysAddr::from(header.e_entry as usize), + })) +} + +struct Header { + e_entry: u64, + e_phoff: u64, + e_phentsize: u16, + e_phnum: u16, +} + +impl Header { + fn parse(image: &[u8]) -> AxResult> { + if image.len() < 64 || &image[0..4] != ELF_MAGIC { + return Ok(None); + } + if image[4] != ELF_CLASS_64 || image[5] != ELF_DATA_LE { + return Err(ax_err_type!( + InvalidInput, + "LoongArch kernel ELF must be 64-bit little-endian" + )); + } + let machine = read_u16(image, 18)?; + if machine != EM_LOONGARCH { + return Ok(None); + } + + let e_phentsize = read_u16(image, 54)?; + if e_phentsize < 56 { + return Err(ax_err_type!( + InvalidInput, + format!("LoongArch ELF program header is too small: {e_phentsize}") + )); + } + + Ok(Some(Self { + e_entry: read_u64(image, 24)?, + e_phoff: read_u64(image, 32)?, + e_phentsize, + e_phnum: read_u16(image, 56)?, + })) + } +} + +fn read_program_header(image: &[u8], header: &Header, idx: u16) -> AxResult { + let start = (header.e_phoff as usize) + .checked_add(idx as usize * header.e_phentsize as usize) + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF phdr offset overflow"))?; + let end = start + .checked_add(header.e_phentsize as usize) + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF phdr end overflow"))?; + if end > image.len() { + return Err(ax_err_type!( + InvalidInput, + "LoongArch ELF program header exceeds image size" + )); + } + + Ok(ProgramHeader { + p_type: read_u32(image, start)?, + p_offset: read_u64(image, start + 8)?, + p_paddr: read_u64(image, start + 24)?, + p_filesz: read_u64(image, start + 32)?, + p_memsz: read_u64(image, start + 40)?, + }) +} + +fn read_u16(image: &[u8], offset: usize) -> AxResult { + let bytes = image + .get(offset..offset + 2) + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF u16 read out of range"))?; + Ok(u16::from_le_bytes(bytes.try_into().unwrap())) +} + +fn read_u32(image: &[u8], offset: usize) -> AxResult { + let bytes = image + .get(offset..offset + 4) + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF u32 read out of range"))?; + Ok(u32::from_le_bytes(bytes.try_into().unwrap())) +} + +fn read_u64(image: &[u8], offset: usize) -> AxResult { + let bytes = image + .get(offset..offset + 8) + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF u64 read out of range"))?; + Ok(u64::from_le_bytes(bytes.try_into().unwrap())) +} diff --git a/os/axvisor/src/images/loongarch_linux.rs b/os/axvisor/src/images/loongarch_linux.rs new file mode 100644 index 0000000000..a155b467eb --- /dev/null +++ b/os/axvisor/src/images/loongarch_linux.rs @@ -0,0 +1,230 @@ +use alloc::vec::Vec; + +use ax_errno::{AxResult, ax_err_type}; +use axvm::{AxVMRef, VMMemoryRegion}; +use axvmconfig::AxVMCrateConfig; + +use crate::images::load_vm_image_from_memory; + +const BOOTINFO_GPA: usize = 0x0008_0000; +const DTB_GPA: usize = 0x0010_0000; +const CMDLINE_GPA: usize = BOOTINFO_GPA; +const VENDOR_GPA: usize = BOOTINFO_GPA + 0x1000; +const SYSTAB_GPA: usize = BOOTINFO_GPA + 0x2000; +const CONFIG_TABLE_GPA: usize = BOOTINFO_GPA + 0x3000; +const BOOT_MEMMAP_GPA: usize = BOOTINFO_GPA + 0x4000; +const INITRD_TABLE_GPA: usize = BOOTINFO_GPA + 0x5000; +const BOOT_STACK_GPA: usize = 0x000f_0000; +const BOOT_STACK_SIZE: usize = 0x0001_0000; +const EFI_MEMORY_WB: u64 = 1 << 3; +const EFI_SYSTEM_TABLE_SIGNATURE: u64 = 0x5453_5953_2049_4249; +const EFI_2_10_SYSTEM_TABLE_REVISION: u32 = (2 << 16) | 10; +const EFI_MEMORY_DESCRIPTOR_VERSION: u32 = 1; +const EFI_LOADER_DATA: u32 = 2; +const EFI_CONVENTIONAL_MEMORY: u32 = 7; +const EFI_MEMORY_DESC_SIZE: usize = 40; + +pub fn setup_bootinfo(vm: AxVMRef, crate_config: &AxVMCrateConfig) -> AxResult { + let bootargs = crate_config + .kernel + .cmdline + .clone() + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch Linux requires kernel.cmdline"))?; + if !has_cmdline_arg(&bootargs, "init") && !has_cmdline_arg(&bootargs, "rdinit") { + warn!("LoongArch Linux cmdline has no init= or rdinit= argument"); + } + if !has_cmdline_arg(&bootargs, "console") { + warn!("LoongArch Linux cmdline has no console= argument"); + } + + let mut cmdline = [0u8; 4096]; + let bytes = bootargs.as_bytes(); + let len = bytes.len().min(cmdline.len() - 1); + cmdline[..len].copy_from_slice(&bytes[..len]); + load_vm_image_from_memory(&cmdline, CMDLINE_GPA.into(), vm.clone())?; + + let mut vendor = [0u8; 64]; + let vendor_utf16 = [ + b'A' as u16, + b'x' as u16, + b'v' as u16, + b'i' as u16, + b's' as u16, + b'o' as u16, + b'r' as u16, + 0, + ]; + for (idx, ch) in vendor_utf16.iter().enumerate() { + vendor[idx * 2..idx * 2 + 2].copy_from_slice(&ch.to_le_bytes()); + } + load_vm_image_from_memory(&vendor, VENDOR_GPA.into(), vm.clone())?; + + let vm_regions = vm.memory_regions(); + let regions = efi_memory_regions(&vm_regions, crate_config); + let map_size = regions.len() * EFI_MEMORY_DESC_SIZE; + let mut boot_memmap = Vec::new(); + write_u64(&mut boot_memmap, map_size as u64); + write_u64(&mut boot_memmap, EFI_MEMORY_DESC_SIZE as u64); + write_u32(&mut boot_memmap, EFI_MEMORY_DESCRIPTOR_VERSION); + write_u32(&mut boot_memmap, 0); + write_u64(&mut boot_memmap, 0); + write_u64(&mut boot_memmap, map_size as u64); + for region in ®ions { + let gpa = region.gpa.as_usize() as u64; + let pages = (region.size() as u64).div_ceil(4096); + let mem_type = match region.gpa.as_usize() { + BOOTINFO_GPA | DTB_GPA => EFI_LOADER_DATA, + _ => EFI_CONVENTIONAL_MEMORY, + }; + write_efi_memory_desc(&mut boot_memmap, gpa, pages, mem_type); + } + load_vm_image_from_memory(&boot_memmap, BOOT_MEMMAP_GPA.into(), vm.clone())?; + + let (dtb_addr, initrd_range) = vm.with_config(|config| { + let initrd_range = config.image_config.ramdisk.as_ref().and_then(|ramdisk| { + let size = ramdisk.size?; + let start = ramdisk.load_gpa.as_usize() as u64; + Some((start, size as u64)) + }); + (config.image_config.dtb_load_gpa, initrd_range) + }); + let mut config_table = Vec::new(); + write_guid( + &mut config_table, + 0x800f683f, + 0xd08b, + 0x423a, + &[0xa2, 0x93, 0x96, 0x5c, 0x3c, 0x6f, 0xe2, 0xb4], + ); + write_u64(&mut config_table, BOOT_MEMMAP_GPA as u64); + if let Some((base, size)) = initrd_range { + let mut initrd_table = Vec::new(); + write_u64(&mut initrd_table, base); + write_u64(&mut initrd_table, size); + load_vm_image_from_memory(&initrd_table, INITRD_TABLE_GPA.into(), vm.clone())?; + + write_guid( + &mut config_table, + 0x5568e427, + 0x68fc, + 0x4f3d, + &[0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68], + ); + write_u64(&mut config_table, INITRD_TABLE_GPA as u64); + } + if let Some(dtb_addr) = dtb_addr { + write_guid( + &mut config_table, + 0xb1b621d5, + 0xf19c, + 0x41a5, + &[0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0], + ); + write_u64(&mut config_table, dtb_addr.as_usize() as u64); + } + load_vm_image_from_memory(&config_table, CONFIG_TABLE_GPA.into(), vm.clone())?; + + let mut systab = Vec::new(); + write_u64(&mut systab, EFI_SYSTEM_TABLE_SIGNATURE); + write_u32(&mut systab, EFI_2_10_SYSTEM_TABLE_REVISION); + write_u32(&mut systab, 120); + write_u32(&mut systab, 0); + write_u32(&mut systab, 0); + write_u64(&mut systab, VENDOR_GPA as u64); + write_u32(&mut systab, 1); + write_u32(&mut systab, 0); + for _ in 0..8 { + write_u64(&mut systab, 0); + } + write_u64(&mut systab, (config_table.len() / 24) as u64); + write_u64(&mut systab, CONFIG_TABLE_GPA as u64); + load_vm_image_from_memory(&systab, SYSTAB_GPA.into(), vm.clone())?; + + let boot_stack = [0u8; BOOT_STACK_SIZE]; + load_vm_image_from_memory(&boot_stack, BOOT_STACK_GPA.into(), vm.clone())?; + + vm.with_config(|config| { + config.cpu_config.boot_args = [1, CMDLINE_GPA, SYSTAB_GPA]; + config.cpu_config.boot_stack_top = BOOT_STACK_GPA + BOOT_STACK_SIZE; + }); + info!( + "LoongArch Linux bootinfo: cmdline={:#x}, systab={:#x}, dtb={:?}, initrd={:?}, \ + boot_stack=[{:#x}, {:#x})", + CMDLINE_GPA, + SYSTAB_GPA, + dtb_addr, + initrd_range, + BOOT_STACK_GPA, + BOOT_STACK_GPA + BOOT_STACK_SIZE + ); + + Ok(()) +} + +fn efi_memory_regions<'a>( + regions: &'a [VMMemoryRegion], + crate_config: &AxVMCrateConfig, +) -> Vec<&'a VMMemoryRegion> { + let configured_region_count = if crate_config.kernel.configured_memory_region_count == 0 { + crate_config.kernel.memory_regions.len() + } else { + crate_config + .kernel + .configured_memory_region_count + .min(crate_config.kernel.memory_regions.len()) + }; + + crate_config + .kernel + .memory_regions + .iter() + .take(configured_region_count) + .filter_map(|cfg| { + let region = regions + .iter() + .find(|region| region.gpa.as_usize() == cfg.gpa && region.size() == cfg.size); + if region.is_none() { + warn!( + "Configured guest memory region [{:#x}, {:#x}) is not mapped; skipping EFI memmap entry", + cfg.gpa, + cfg.gpa + cfg.size + ); + } + region + }) + .collect() +} + +fn has_cmdline_arg(cmdline: &str, name: &str) -> bool { + cmdline + .split_ascii_whitespace() + .any(|arg| arg.split_once('=').is_some_and(|(key, _)| key == name)) +} + +fn write_efi_memory_desc(buf: &mut Vec, phys_addr: u64, num_pages: u64, mem_type: u32) { + write_u32(buf, mem_type); + write_u32(buf, 0); + write_u64(buf, phys_addr); + write_u64(buf, 0); + write_u64(buf, num_pages); + write_u64(buf, EFI_MEMORY_WB); +} + +fn write_guid(buf: &mut Vec, a: u32, b: u16, c: u16, d: &[u8; 8]) { + write_u32(buf, a); + write_u16(buf, b); + write_u16(buf, c); + buf.extend_from_slice(d); +} + +fn write_u16(buf: &mut Vec, value: u16) { + buf.extend_from_slice(&value.to_le_bytes()); +} + +fn write_u32(buf: &mut Vec, value: u32) { + buf.extend_from_slice(&value.to_le_bytes()); +} + +fn write_u64(buf: &mut Vec, value: u64) { + buf.extend_from_slice(&value.to_le_bytes()); +} diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index 1456c8d862..02c118c201 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -25,6 +25,10 @@ use axvm::{AxVMRef, GuestPhysAddr, VMMemoryRegion}; use crate::config::{get_vm_dtb_arc, vmcfg}; mod linux; +#[cfg(target_arch = "loongarch64")] +mod loongarch_elf; +#[cfg(target_arch = "loongarch64")] +mod loongarch_linux; #[cfg(target_arch = "x86_64")] mod x86; #[cfg(target_arch = "x86_64")] @@ -160,7 +164,7 @@ impl ImageLoader { ); } - load_vm_image_from_memory(vm_imags.kernel, self.kernel_load_gpa, self.vm.clone())?; + self.load_kernel_from_memory(vm_imags.kernel)?; // Load Ramdisk image and record its size before regenerating the DTB. if let Some(buffer) = vm_imags.ramdisk { @@ -208,6 +212,9 @@ impl ImageLoader { } } + #[cfg(target_arch = "loongarch64")] + loongarch_linux::setup_bootinfo(self.vm.clone(), &self.config)?; + self.load_boot_image_from_memory(vm_imags.bios)?; Ok(()) @@ -312,6 +319,29 @@ impl ImageLoader { Ok(()) } + fn load_kernel_from_memory(&self, kernel: &[u8]) -> AxResult { + #[cfg(target_arch = "loongarch64")] + if let Some(info) = loongarch_elf::try_load(kernel, self.vm.clone())? { + self.vm.with_config(|config| { + config.cpu_config.bsp_entry = info.entry; + config.cpu_config.ap_entry = info.entry; + }); + info!( + "LoongArch ELF kernel entry set to {:#x}", + info.entry.as_usize() + ); + return Ok(()); + } + + load_vm_image_from_memory(kernel, self.kernel_load_gpa, self.vm.clone()) + } + + #[cfg(all(feature = "fs", target_arch = "loongarch64"))] + fn load_kernel_from_filesystem(&self, kernel_path: &str) -> AxResult { + let kernel = fs::read_full_image(kernel_path)?; + self.load_kernel_from_memory(&kernel) + } + #[cfg(target_arch = "x86_64")] fn should_load_default_x86_boot_image(&self) -> bool { self.config.kernel.enable_bios @@ -619,6 +649,29 @@ pub fn load_vm_image_from_memory( } } +#[cfg(target_arch = "loongarch64")] +pub fn zero_vm_memory(load_addr: GuestPhysAddr, size: usize, vm: AxVMRef) -> AxResult { + let image_load_regions = vm.get_image_load_region(load_addr, size)?; + let mut zeroed_size = 0; + + for region in image_load_regions { + unsafe { + core::ptr::write_bytes(region.as_mut_ptr(), 0, region.len()); + } + axvm::clean_dcache_range((region.as_ptr() as usize).into(), region.len()); + zeroed_size += region.len(); + } + + if zeroed_size == size { + Ok(()) + } else { + ax_err!( + InvalidData, + format!("VM memory was only partially zeroed: {zeroed_size}/{size} bytes") + ) + } +} + #[cfg(feature = "fs")] pub mod fs { use alloc::vec::Vec; @@ -652,6 +705,9 @@ pub mod fs { } } // Load kernel image. + #[cfg(target_arch = "loongarch64")] + loader.load_kernel_from_filesystem(&loader.config.kernel.kernel_path)?; + #[cfg(not(target_arch = "loongarch64"))] load_vm_image( &loader.config.kernel.kernel_path, loader.kernel_load_gpa, @@ -722,6 +778,9 @@ pub mod fs { } } + #[cfg(target_arch = "loongarch64")] + loongarch_linux::setup_bootinfo(loader.vm.clone(), &loader.config)?; + Ok(()) } diff --git a/virtualization/axvcpu/src/vcpu.rs b/virtualization/axvcpu/src/vcpu.rs index 0b9656cdc1..70e92e9e13 100644 --- a/virtualization/axvcpu/src/vcpu.rs +++ b/virtualization/axvcpu/src/vcpu.rs @@ -328,18 +328,6 @@ impl AxVCpu { pub fn set_return_value(&self, val: usize) { self.get_arch_vcpu().set_return_value(val); } - - /// Handles an already-resolved nested page mapping in architecture-specific hardware state. - pub fn handle_nested_page_mapping( - &self, - gpa: GuestPhysAddr, - hpa: HostPhysAddr, - access_flags: axaddrspace::MappingFlags, - page_size: ax_page_table_multiarch::PageSize, - ) -> AxResult { - self.get_arch_vcpu() - .handle_nested_page_mapping(gpa, hpa, access_flags, page_size) - } } #[ax_percpu::def_percpu] diff --git a/virtualization/axvm/src/config.rs b/virtualization/axvm/src/config.rs index abb8860ca4..26d955edfc 100644 --- a/virtualization/axvm/src/config.rs +++ b/virtualization/axvm/src/config.rs @@ -32,6 +32,12 @@ pub struct AxVCpuConfig { pub bsp_entry: GuestPhysAddr, /// The entry address in GPA for the Application Processor (AP). pub ap_entry: GuestPhysAddr, + /// LoongArch Linux EFI-style boot arguments (a0, a1, a2). + #[cfg(target_arch = "loongarch64")] + pub boot_args: [usize; 3], + /// LoongArch Linux boot stack top. + #[cfg(target_arch = "loongarch64")] + pub boot_stack_top: usize, } /// Ramdisk image information. diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index 7bb8f40eea..ab4ac5c69f 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -267,6 +267,8 @@ impl AxVM { let arch_config = AxVCpuCreateConfig { cpu_id: vcpu_id, dtb_addr: dtb_addr.unwrap_or_default().as_usize(), + boot_args: inner_mut.config.cpu_config.boot_args, + boot_stack_top: inner_mut.config.cpu_config.boot_stack_top, }; // FIXME: VCpu is neither `Send` nor `Sync` by design, check whether diff --git a/virtualization/loongarch_vcpu/src/vcpu.rs b/virtualization/loongarch_vcpu/src/vcpu.rs index 3dc983ade4..90382bd88c 100644 --- a/virtualization/loongarch_vcpu/src/vcpu.rs +++ b/virtualization/loongarch_vcpu/src/vcpu.rs @@ -17,8 +17,9 @@ use crate::{ registers::{ CSR_PGDH, CSR_PGDL, CSR_PWCH, CSR_PWCL, CSR_STLBPS, CSR_TLBRENTRY, INT_TIMER, csr_read, csr_write, gcfg_set_gpm_num, gcfg_set_matc, gcfg_set_toci, gcfg_set_toe, gcfg_set_tohu, - gcfg_set_top, gcfg_set_topi, gcfg_set_toti, get_ecfg_vs, gintc_set_hwip, gstat_set_gid, - gstat_set_pgm, gtlbc_set_tgid, gtlbc_set_use_tgid, set_ecfg_line_enabled, set_ecfg_vs, + gcfg_set_top, gcfg_set_topi, gcfg_set_toti, get_ecfg_vs, gintc_set_hwi_passthrough, + gstat_set_gid, gstat_set_pvm, gtlbc_set_tgid, gtlbc_set_use_tgid, set_ecfg_line_enabled, + set_ecfg_vs, }, }; @@ -104,6 +105,8 @@ const GUEST_BOOT_DMW: usize = pub struct LoongArchVCpuCreateConfig { pub cpu_id: usize, pub dtb_addr: usize, + pub boot_args: [usize; 3], + pub boot_stack_top: usize, } #[derive(Clone, Debug, Default)] @@ -118,8 +121,17 @@ impl AxArchVCpu for LoongArchVCpu { fn new(_vm_id: usize, _vcpu_id: usize, config: Self::CreateConfig) -> AxResult { let mut ctx = LoongArchContextFrame::default(); - ctx.set_argument(config.cpu_id); - ctx.set_a1(config.dtb_addr); + if config.boot_args != [0; 3] { + ctx.set_argument(config.boot_args[0]); + ctx.set_a1(config.boot_args[1]); + ctx.set_a2(config.boot_args[2]); + if config.boot_stack_top != 0 { + ctx.set_gpr(3, config.boot_stack_top); + } + } else { + ctx.set_argument(config.cpu_id); + ctx.set_a1(config.dtb_addr); + } Ok(Self { ctx, @@ -342,7 +354,7 @@ impl LoongArchVCpu { unsafe fn enable_guest_mode(&self) { let guest_id = self.vm_id + 1; gstat_set_gid(guest_id); - gstat_set_pgm(true); + gstat_set_pvm(true); gtlbc_set_use_tgid(true); gtlbc_set_tgid(guest_id); gcfg_set_matc(0x1); @@ -353,7 +365,7 @@ impl LoongArchVCpu { gcfg_set_tohu(false); gcfg_set_toci(0x2); gcfg_set_gpm_num(0); - gintc_set_hwip(0xff); + gintc_set_hwi_passthrough(0xff); set_ecfg_line_enabled(INT_TIMER, false); prmd::set_pie(true); } From e4f32262b9133b767211d0887dde160df2f7294a Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 4 Jun 2026 14:25:02 +0800 Subject: [PATCH 08/50] opt --- ...ootfs.toml => qemu-loongarch64-linux.toml} | 0 .../vms/linux-loongarch64-qemu-smp1.dts | 174 ------------------ .../vms/linux-loongarch64-qemu-smp1.toml | 70 ------- .../loongarch64/linux-rootfs-smp1.dts} | 0 .../loongarch64/linux-rootfs-smp1.toml} | 2 +- .../loongarch/linux-direct-boot-analysis.md | 10 +- os/axvisor/doc/loongarch/rootfs-virtio-blk.md | 4 +- os/axvisor/doc/qemu-quickstart.md | 2 + os/axvisor/doc/qemu-quickstart_cn.md | 2 + os/axvisor/scripts/quick-start.sh | 24 +-- 10 files changed, 25 insertions(+), 263 deletions(-) rename os/axvisor/configs/board/{qemu-loongarch64-guest-rootfs.toml => qemu-loongarch64-linux.toml} (100%) delete mode 100644 os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.dts delete mode 100644 os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.toml rename os/axvisor/configs/vms/{linux-loongarch64-qemu-rootfs-smp1.dts => qemu/loongarch64/linux-rootfs-smp1.dts} (100%) rename os/axvisor/configs/vms/{linux-loongarch64-qemu-rootfs-smp1.toml => qemu/loongarch64/linux-rootfs-smp1.toml} (96%) diff --git a/os/axvisor/configs/board/qemu-loongarch64-guest-rootfs.toml b/os/axvisor/configs/board/qemu-loongarch64-linux.toml similarity index 100% rename from os/axvisor/configs/board/qemu-loongarch64-guest-rootfs.toml rename to os/axvisor/configs/board/qemu-loongarch64-linux.toml diff --git a/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.dts b/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.dts deleted file mode 100644 index fe674e74b1..0000000000 --- a/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.dts +++ /dev/null @@ -1,174 +0,0 @@ -/dts-v1/; - -/ { - #size-cells = <0x02>; - #address-cells = <0x02>; - compatible = "linux,dummy-loongson3"; - - platform-bus@16000000 { - interrupt-parent = <0x8003>; - ranges = <0x00 0x00 0x16000000 0x2000000>; - #address-cells = <0x01>; - #size-cells = <0x01>; - compatible = "qemu,platform\0simple-bus"; - }; - - poweroff { - value = <0x34>; - offset = <0x00>; - regmap = <0x8005>; - compatible = "syscon-poweroff"; - }; - - reboot { - value = <0x42>; - offset = <0x02>; - regmap = <0x8005>; - compatible = "syscon-reboot"; - }; - - ged@100e001c { - phandle = <0x8005>; - reg-io-width = <0x01>; - reg-shift = <0x00>; - reg = <0x00 0x100e001c 0x00 0x03>; - compatible = "syscon"; - }; - - rtc@100d0100 { - interrupt-parent = <0x8003>; - interrupts = <0x06 0x04>; - reg = <0x00 0x100d0100 0x00 0x100>; - compatible = "loongson,ls7a-rtc"; - }; - - serial@1fe001e0 { - interrupt-parent = <0x8003>; - interrupts = <0x02 0x04>; - clock-frequency = <0x5f5e100>; - reg = <0x00 0x1fe001e0 0x00 0x100>; - compatible = "ns16550a"; - }; - - serial@1fe002e0 { - status = "disabled"; - interrupt-parent = <0x8003>; - interrupts = <0x03 0x04>; - clock-frequency = <0x5f5e100>; - reg = <0x00 0x1fe002e0 0x00 0x100>; - compatible = "ns16550a"; - }; - - serial@1fe003e0 { - status = "disabled"; - interrupt-parent = <0x8003>; - interrupts = <0x04 0x04>; - clock-frequency = <0x5f5e100>; - reg = <0x00 0x1fe003e0 0x00 0x100>; - compatible = "ns16550a"; - }; - - serial@1fe004e0 { - status = "disabled"; - interrupt-parent = <0x8003>; - interrupts = <0x05 0x04>; - clock-frequency = <0x5f5e100>; - reg = <0x00 0x1fe004e0 0x00 0x100>; - compatible = "ns16550a"; - }; - - pcie@20000000 { - status = "disabled"; - interrupt-map-mask = <0x1800 0x00 0x00 0x07>; - interrupt-map = <0x00 0x00 0x00 0x01 0x8003 0x10 0x00 0x00 0x00 0x02 0x8003 0x11 0x00 0x00 0x00 0x03 0x8003 0x12 0x00 0x00 0x00 0x04 0x8003 0x13 0x800 0x00 0x00 0x01 0x8003 0x11 0x800 0x00 0x00 0x02 0x8003 0x12 0x800 0x00 0x00 0x03 0x8003 0x13 0x800 0x00 0x00 0x04 0x8003 0x10 0x1000 0x00 0x00 0x01 0x8003 0x12 0x1000 0x00 0x00 0x02 0x8003 0x13 0x1000 0x00 0x00 0x03 0x8003 0x10 0x1000 0x00 0x00 0x04 0x8003 0x11 0x1800 0x00 0x00 0x01 0x8003 0x13 0x1800 0x00 0x00 0x02 0x8003 0x10 0x1800 0x00 0x00 0x03 0x8003 0x11 0x1800 0x00 0x00 0x04 0x8003 0x12>; - msi-map = <0x00 0x8004 0x00 0x10000>; - ranges = <0x1000000 0x00 0x4000 0x00 0x18004000 0x00 0xc000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000>; - reg = <0x00 0x20000000 0x00 0x8000000>; - dma-coherent; - bus-range = <0x00 0x7f>; - linux,pci-domain = <0x00>; - #size-cells = <0x02>; - #address-cells = <0x03>; - device_type = "pci"; - compatible = "pci-host-ecam-generic"; - }; - - msi@2ff00000 { - loongson,msi-num-vecs = <0xe0>; - loongson,msi-base-vec = <0x20>; - interrupt-parent = <0x8002>; - interrupt-controller; - reg = <0x00 0x2ff00000 0x00 0x08>; - compatible = "loongson,pch-msi-1.0"; - phandle = <0x8004>; - }; - - platic@10000000 { - loongson,pic-base-vec = <0x00>; - interrupt-parent = <0x8002>; - #interrupt-cells = <0x02>; - interrupt-controller; - reg = <0x00 0x10000000 0x00 0x400>; - compatible = "loongson,pch-pic-1.0"; - phandle = <0x8003>; - }; - - eiointc@1400 { - reg = <0x00 0x1400 0x00 0x800>; - interrupts = <0x03>; - interrupt-parent = <0x8001>; - #interrupt-cells = <0x01>; - interrupt-controller; - compatible = "loongson,ls2k2000-eiointc"; - phandle = <0x8002>; - }; - - cpuic { - #interrupt-cells = <0x01>; - interrupt-controller; - compatible = "loongson,cpu-interrupt-controller"; - phandle = <0x8001>; - }; - - flash@1c000000 { - bank-width = <0x04>; - reg = <0x00 0x1c000000 0x00 0x1000000 0x00 0x1d000000 0x00 0x1000000>; - compatible = "cfi-flash"; - }; - - fw_cfg@1e020000 { - dma-coherent; - reg = <0x00 0x1e020000 0x00 0x18>; - compatible = "qemu,fw-cfg-mmio"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00 0x00 0x00 0x08000000>; - }; - - cpus { - #size-cells = <0x00>; - #address-cells = <0x01>; - - cpu-map { - socket0 { - core0 { - cpu = <0x8000>; - }; - }; - }; - - cpu@0 { - phandle = <0x8000>; - reg = <0x00>; - compatible = "loongarch,Loongson-3A5000"; - device_type = "cpu"; - }; - }; - - chosen { - bootargs = "console=ttyS0 root=/dev/ram rw rdinit=/init"; - stdout-path = "/serial@1fe001e0"; - }; -}; diff --git a/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.toml b/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.toml deleted file mode 100644 index 956e8cf6bf..0000000000 --- a/os/axvisor/configs/vms/linux-loongarch64-qemu-smp1.toml +++ /dev/null @@ -1,70 +0,0 @@ -# Vm base info configs -# -[base] -# Guest vm id. -id = 1 -# Guest vm name. -name = "linux-loongarch64-qemu" -# Virtualization type. -vm_type = 1 -# The number of virtual CPUs. -cpu_num = 1 -# Guest vm physical cpu ids. -phys_cpu_ids = [0] - -# -# Vm kernel configs -# -[kernel] -# The entry point is replaced by the LoongArch ELF loader when vmlinux.elf is used. -entry_point = 0x0020_0000 -# The location of image: "memory" | "fs". -image_location = "fs" -# The file path of the kernel image. -kernel_path = "/guest/linux/qemu-loongarch64" -# The ELF LOAD paddr is used by the LoongArch loader; this is a fallback for flat images. -kernel_load_addr = 0x0020_0000 -# The file path of the device tree blob (DTB). -dtb_path = "/guest/linux/linux-loongarch64-qemu-smp1.dtb" -# The load address of the device tree blob (DTB). -dtb_load_addr = 0x0010_0000 -# The file path of the ramdisk image. -ramdisk_path = "/guest/linux/initramfs.cpio.gz" -# The load address of the ramdisk image. -ramdisk_load_addr = 0x0700_0000 -# Kernel command line. -cmdline = "root=/dev/ram rw console=ttyS0 earlycon=uart,mmio,0x1fe001e0 init=/init nokaslr pci=off initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" - -# Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`). -# For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`, 2 means `MAP_RESERVED`. -memory_regions = [ - [0x0008_0000, 0x0018_0000, 0x7, 0], # Low bootinfo/DTB RAM 512K-2M MAP_ALLOC - [0x0020_0000, 0x03e0_0000, 0x7, 0], # System RAM 2-64M MAP_ALLOC - [0x0400_0000, 0x0200_0000, 0x7, 0], # System RAM 64-96M MAP_ALLOC - [0x0600_0000, 0x0200_0000, 0x7, 0], # System RAM 96-128M MAP_ALLOC -] - -# -# Device specifications -# -[devices] -# The interrupt mode. -interrupt_mode = "passthrough" - -# Pass-through devices. -passthrough_devices = [ - ["/"], -] - -# Passthrough addresses. -# Base-GPA Length. -passthrough_addresses = [ -] - -# Devices that are not desired to be passed through to the guest -excluded_devices = [ -] - -# Emu_devices. -emu_devices = [ -] diff --git a/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.dts similarity index 100% rename from os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts rename to os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.dts diff --git a/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml similarity index 96% rename from os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml rename to os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml index db7395dbb9..4c8a3019bd 100644 --- a/os/axvisor/configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml +++ b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml @@ -25,7 +25,7 @@ kernel_path = "/guest/linux/qemu-loongarch64" # The ELF LOAD paddr is used by the LoongArch loader; this is a fallback for flat images. kernel_load_addr = 0x0020_0000 # The file path of the device tree blob (DTB). -dtb_path = "/guest/linux/linux-loongarch64-qemu-rootfs-smp1.dtb" +dtb_path = "/guest/linux/linux-rootfs-smp1.dtb" # The load address of the device tree blob (DTB). dtb_load_addr = 0x0010_0000 # Kernel command line. Rootfs mode intentionally uses virtio-blk /dev/vda. diff --git a/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md b/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md index bdb7e03ef8..7de9c903dd 100644 --- a/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md +++ b/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md @@ -23,10 +23,12 @@ VM TOML 关键代码位置： -- `os/axvisor/src/vmm/images/mod.rs` -- `components/loongarch_vcpu/src/vcpu.rs` -- `components/axvm/src/config.rs` -- `components/axvm/src/vm.rs` +- `os/axvisor/src/images/mod.rs` +- `os/axvisor/src/images/loongarch_elf.rs` +- `os/axvisor/src/images/loongarch_linux.rs` +- `virtualization/loongarch_vcpu/src/vcpu.rs` +- `virtualization/axvm/src/config.rs` +- `virtualization/axvm/src/vm.rs` ## Kernel 格式 diff --git a/os/axvisor/doc/loongarch/rootfs-virtio-blk.md b/os/axvisor/doc/loongarch/rootfs-virtio-blk.md index ec42a5c07d..c39aa292bb 100644 --- a/os/axvisor/doc/loongarch/rootfs-virtio-blk.md +++ b/os/axvisor/doc/loongarch/rootfs-virtio-blk.md @@ -7,7 +7,7 @@ 当前 LoongArch Linux quick-start 只支持 virtio-blk rootfs。VM 配置使用： ```toml -dtb_path = "/guest/linux/linux-loongarch64-qemu-rootfs-smp1.dtb" +dtb_path = "/guest/linux/linux-rootfs-smp1.dtb" cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw init=/init console=ttyS0 ..." ``` @@ -57,7 +57,7 @@ initramfs 曾用于早期 bring-up，用来绕开： - 外部设备中断注入 guest； - guest idle 后等待设备中断唤醒。 -现在 quick-start 已经切换到 rootfs，`--linux` 和 `--linux-rootfs` 都使用 `linux-loongarch64-qemu-rootfs-smp1.toml`。仓库里的通用 ramdisk/initrd 加载逻辑仍可被其他配置使用，但 LoongArch QEMU quick-start 不再维护 initramfs 作为启动模式。 +现在 quick-start 已经切换到 rootfs，`--linux` 和 `--linux-rootfs` 都使用 `configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml`。仓库里的通用 ramdisk/initrd 加载逻辑仍可被其他架构或其他配置使用，但 LoongArch QEMU quick-start 不再维护 initramfs 作为启动模式。 QEMU runtime 配置中挂载： diff --git a/os/axvisor/doc/qemu-quickstart.md b/os/axvisor/doc/qemu-quickstart.md index cf0d628c53..4b06525cc7 100644 --- a/os/axvisor/doc/qemu-quickstart.md +++ b/os/axvisor/doc/qemu-quickstart.md @@ -193,6 +193,8 @@ For the Linux guest flow with a virtio-blk rootfs, run: ./scripts/quick-start.sh qemu-loongarch64 run --linux ``` +The tracked VM template for this flow is `configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml`; quick-start copies it to `tmp/configs/linux-rootfs-smp1.toml` and patches the temporary image paths. + > **Note**: Stock `qemu-system-loongarch64` usually does not expose LoongArch virtualization extensions. Run `./scripts/setup_qemu_lvz.sh` once, or set `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` to a validated virtualization-capable binary. ## 5. What Does setup_qemu.sh Do? diff --git a/os/axvisor/doc/qemu-quickstart_cn.md b/os/axvisor/doc/qemu-quickstart_cn.md index 6f5d93292a..8e69cb1764 100644 --- a/os/axvisor/doc/qemu-quickstart_cn.md +++ b/os/axvisor/doc/qemu-quickstart_cn.md @@ -151,6 +151,8 @@ Linux guest 启动使用 virtio-blk rootfs： ./scripts/quick-start.sh qemu-loongarch64 run --linux ``` +该流程使用的仓库内 VM 模板是 `configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml`；quick-start 会复制到 `tmp/configs/linux-rootfs-smp1.toml`，再只修改临时配置中的镜像路径。 + > **注意**：标准版 `qemu-system-loongarch64` 通常不会暴露 LoongArch 虚拟化扩展。请先运行一次 `./scripts/setup_qemu_lvz.sh`，或者通过 `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` 指向一个已经确认支持虚拟化扩展的二进制。 ## 5. setup_qemu.sh 做了什么 diff --git a/os/axvisor/scripts/quick-start.sh b/os/axvisor/scripts/quick-start.sh index 2902bd5619..52addb94cb 100755 --- a/os/axvisor/scripts/quick-start.sh +++ b/os/axvisor/scripts/quick-start.sh @@ -145,7 +145,7 @@ Examples: $0 qemu-loongarch64 start --axvisor # One-step: prepare + launch AxVisor shell $0 qemu-loongarch64 start --linux # One-step: launch Linux with virtio-blk rootfs $0 qemu-loongarch64 start --linux-rootfs # Same as above - $0 qemu-loongarch64 start # Same as above (default axvisor) + $0 qemu-loongarch64 start # Same as --axvisor (default) # QEMU x86_64 $0 qemu-x86_64 start --nimbos # One-step: prepare + launch NimbOS @@ -321,11 +321,11 @@ setup_qemu_loongarch64() { info "Preparing board config file..." run_cmd cp configs/board/qemu-loongarch64.toml tmp/configs/ - run_cmd cp configs/board/qemu-loongarch64-guest-rootfs.toml tmp/configs/ + run_cmd cp configs/board/qemu-loongarch64-linux.toml tmp/configs/ info "Preparing Linux guest rootfs config file..." - run_cmd cp configs/vms/linux-loongarch64-qemu-rootfs-smp1.toml tmp/configs/ - run_cmd cp configs/vms/linux-loongarch64-qemu-rootfs-smp1.dts tmp/configs/ + run_cmd cp configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml tmp/configs/ + run_cmd cp configs/vms/qemu/loongarch64/linux-rootfs-smp1.dts tmp/configs/ local guest_dir="${AXVISOR_LOONGARCH64_GUEST_DIR:-$(cd ../../.. && pwd)/axvisor-guest/IMAGES/qemu/loongarch64/linux}" if [ -f "$guest_dir/qemu-loongarch64" ]; then @@ -340,15 +340,15 @@ setup_qemu_loongarch64() { fi if ! command -v dtc &> /dev/null; then - error "dtc is required to build linux-loongarch64-qemu-rootfs-smp1.dtb" + error "dtc is required to build linux-rootfs-smp1.dtb" exit 1 fi - run_cmd dtc -I dts -O dtb -o tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dtb tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dts - run_cmd cp tmp/configs/linux-loongarch64-qemu-rootfs-smp1.dtb tmp/images/qemu_loongarch64_linux/ + run_cmd dtc -I dts -O dtb -o tmp/configs/linux-rootfs-smp1.dtb tmp/configs/linux-rootfs-smp1.dts + run_cmd cp tmp/configs/linux-rootfs-smp1.dtb tmp/images/qemu_loongarch64_linux/ - run_cmd sed -i 's|^image_location = "fs"|image_location = "memory"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml - run_cmd sed -i 's|^kernel_path = .*|kernel_path = "../images/qemu_loongarch64_linux/qemu-loongarch64"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml - run_cmd sed -i 's|^dtb_path = .*|dtb_path = "linux-loongarch64-qemu-rootfs-smp1.dtb"|g' tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml + run_cmd sed -i 's|^image_location = "fs"|image_location = "memory"|g' tmp/configs/linux-rootfs-smp1.toml + run_cmd sed -i 's|^kernel_path = .*|kernel_path = "../images/qemu_loongarch64_linux/qemu-loongarch64"|g' tmp/configs/linux-rootfs-smp1.toml + run_cmd sed -i 's|^dtb_path = .*|dtb_path = "linux-rootfs-smp1.dtb"|g' tmp/configs/linux-rootfs-smp1.toml info "Preparing QEMU config file..." run_cmd cp configs/qemu/qemu-loongarch64.toml tmp/configs/qemu-loongarch64-runtime.toml @@ -455,9 +455,9 @@ run_qemu_loongarch64_linux() { run_cmd sed -i 's|virtio-blk-pci,drive=disk0|virtio-blk-pci,drive=disk0,disable-modern=on|g' tmp/configs/qemu-loongarch64-runtime.toml run_axvisor_qemu_with_loongarch64_qemu \ - --config "$(pwd)/tmp/configs/qemu-loongarch64-guest-rootfs.toml" \ + --config "$(pwd)/tmp/configs/qemu-loongarch64-linux.toml" \ --qemu-config "$(pwd)/tmp/configs/qemu-loongarch64-runtime.toml" \ - --vmconfigs "$(pwd)/tmp/configs/linux-loongarch64-qemu-rootfs-smp1.toml" + --vmconfigs "$(pwd)/tmp/configs/linux-rootfs-smp1.toml" } run_qemu_loongarch64_linux_rootfs() { From 47999e1a7e75b8baf6618aaeb6ee778818e8c74d Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 4 Jun 2026 17:13:47 +0800 Subject: [PATCH 09/50] fix: wait time etc --- os/arceos/modules/axhal/Cargo.toml | 1 + os/arceos/modules/axhal/src/lib.rs | 29 ++ os/axvisor/src/fdt/mod.rs | 32 ++ os/axvisor/src/fdt/parser.rs | 320 ++++++++++++++ os/axvisor/src/manager.rs | 54 +++ .../ax-plat-loongarch64-qemu-virt/src/irq.rs | 127 ++++++ .../src/irq/eiointc.rs | 10 - platforms/ax-plat/src/irq.rs | 38 ++ virtualization/axvcpu/src/vcpu.rs | 5 +- virtualization/axvm/src/arch.rs | 33 +- virtualization/axvm/src/host/arceos.rs | 15 +- virtualization/axvm/src/host/traits.rs | 15 +- virtualization/axvm/src/lib.rs | 2 + virtualization/axvm/src/manager.rs | 16 + virtualization/axvm/src/runtime/vcpus.rs | 20 + virtualization/axvm/src/task.rs | 11 +- virtualization/axvm/src/timer.rs | 43 +- virtualization/axvm/src/vm.rs | 35 +- .../loongarch_vcpu/src/exception.rs | 404 ++++++++++++++---- virtualization/loongarch_vcpu/src/host.rs | 53 +++ .../loongarch_vcpu/src/registers.rs | 8 - virtualization/loongarch_vcpu/src/vcpu.rs | 152 ++++--- 22 files changed, 1241 insertions(+), 182 deletions(-) diff --git a/os/arceos/modules/axhal/Cargo.toml b/os/arceos/modules/axhal/Cargo.toml index 0447d6b111..afc7001ccf 100644 --- a/os/arceos/modules/axhal/Cargo.toml +++ b/os/arceos/modules/axhal/Cargo.toml @@ -46,6 +46,7 @@ hv = [ "ax-cpu/arm-el2", "ax-cpu/exception-table", "ax-percpu/arm-el2", + "ax-plat-loongarch64-qemu-virt?/hypervisor", "axplat-dyn?/hv", ] axvisor-linker = [] diff --git a/os/arceos/modules/axhal/src/lib.rs b/os/arceos/modules/axhal/src/lib.rs index c503ed6fc3..0873978fc3 100644 --- a/os/arceos/modules/axhal/src/lib.rs +++ b/os/arceos/modules/axhal/src/lib.rs @@ -50,6 +50,35 @@ pub mod tls; #[cfg(feature = "irq")] pub mod irq; +#[cfg(all( + target_arch = "loongarch64", + feature = "irq", + ax_hal_any_platform_feature +))] +pub mod loongarch64_hv_irq { + pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize)) { + ax_plat::irq::register_loongarch_virtual_irq_injector(injector); + } + + pub fn enable_external_irq_line() { + crate::irq::set_enable(ax_config::devices::EIOINTC_IRQ, true); + } + + pub fn register_guest_irq_route( + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, + ) { + ax_plat::irq::register_loongarch_guest_irq_route( + physical_irq, + vm_id, + vcpu_id, + guest_vector, + ); + } +} + #[cfg(feature = "paging")] pub mod paging; diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index 16e51cb2ee..403da8c0df 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -42,10 +42,22 @@ use crate::config::{get_vm_dtb_arc, vmcfg}; // DTB cache for generated device trees static GENERATED_DTB_CACHE: LazyInit>>> = LazyInit::new(); +#[cfg(target_arch = "loongarch64")] +static LOONGARCH_GUEST_IRQ_ROUTES: LazyInit>>> = + LazyInit::new(); + +#[cfg(target_arch = "loongarch64")] +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub struct LoongArchGuestIrqRoute { + pub physical_irq: usize, + pub guest_vector: usize, +} /// Initialize the DTB cache pub fn init_dtb_cache() { GENERATED_DTB_CACHE.init_once(Mutex::new(BTreeMap::new())); + #[cfg(target_arch = "loongarch64")] + LOONGARCH_GUEST_IRQ_ROUTES.init_once(Mutex::new(BTreeMap::new())); } /// Get reference to the DTB cache @@ -62,6 +74,24 @@ pub fn crate_guest_fdt_with_cache(dtb_data: Vec, crate_config: &AxVMCrateCon cache_lock.insert(crate_config.base.id, dtb_data); } +#[cfg(target_arch = "loongarch64")] +pub fn store_loongarch_guest_irq_routes(vm_id: usize, routes: Vec) { + let mut cache_lock = LOONGARCH_GUEST_IRQ_ROUTES + .get_or_init(|| Mutex::new(BTreeMap::new())) + .lock(); + cache_lock.insert(vm_id, routes); +} + +#[cfg(target_arch = "loongarch64")] +pub fn get_loongarch_guest_irq_routes(vm_id: usize) -> Vec { + LOONGARCH_GUEST_IRQ_ROUTES + .get_or_init(|| Mutex::new(BTreeMap::new())) + .lock() + .get(&vm_id) + .cloned() + .unwrap_or_default() +} + /// Handle all FDT-related operations for guest architectures that boot with DTB. pub fn handle_fdt_operations( vm_config: &mut AxVMConfig, @@ -110,6 +140,8 @@ pub fn handle_fdt_operations( let dtb = dtb_arc.as_ref(); parse_reserved_memory_regions(vm_create_config, dtb)?; parse_passthrough_devices_address(vm_config, vm_create_config, dtb)?; + #[cfg(target_arch = "loongarch64")] + parse_loongarch_guest_irq_routes(vm_config, dtb)?; #[cfg(target_arch = "aarch64")] parse_vm_interrupt(vm_config, dtb)?; } else { diff --git a/os/axvisor/src/fdt/parser.rs b/os/axvisor/src/fdt/parser.rs index e780479886..dbde9b495c 100644 --- a/os/axvisor/src/fdt/parser.rs +++ b/os/axvisor/src/fdt/parser.rs @@ -14,13 +14,19 @@ //! FDT parsing and processing functionality. +#[cfg(target_arch = "loongarch64")] +use alloc::collections::{BTreeMap, BTreeSet}; use alloc::{format, string::ToString, vec, vec::Vec}; use ax_errno::{AxResult, ax_err_type}; use fdt_parser::{Fdt, FdtHeader, PciRange, PciSpace}; +#[cfg(target_arch = "loongarch64")] +use fdt_parser::{Node, Status}; #[cfg(target_arch = "aarch64")] use crate::fdt::create::update_cpu_node; +#[cfg(target_arch = "loongarch64")] +use crate::fdt::{LoongArchGuestIrqRoute, store_loongarch_guest_irq_routes}; use axvm::{MappingFlags, config::AxVMConfig}; use axvmconfig::{AxVMCrateConfig, PassThroughDeviceConfig, VmMemConfig, VmMemMappingType}; @@ -306,6 +312,320 @@ pub fn parse_reserved_memory_regions(crate_cfg: &mut AxVMCrateConfig, dtb: &[u8] Ok(()) } +#[cfg(target_arch = "loongarch64")] +fn property_u32_list(node: &Node<'_>, name: &str) -> Vec { + node.find_property(name) + .map(|prop| prop.u32_list().collect()) + .unwrap_or_default() +} + +#[cfg(target_arch = "loongarch64")] +fn property_u32(node: &Node<'_>, name: &str) -> Option { + node.find_property(name) + .and_then(|prop| prop.u32_list().next()) +} + +#[cfg(target_arch = "loongarch64")] +fn node_phandle(node: &Node<'_>) -> Option { + node.phandle().map(|phandle| phandle.as_usize()) +} + +#[cfg(target_arch = "loongarch64")] +fn interrupt_parent_phandle(node: &Node<'_>) -> Option { + node.interrupt_parent() + .and_then(|parent| node_phandle(&parent.node)) +} + +#[cfg(target_arch = "loongarch64")] +fn node_interrupt_cells(node: &Node<'_>) -> usize { + property_u32(node, "#interrupt-cells").unwrap_or(1) as usize +} + +#[cfg(target_arch = "loongarch64")] +fn node_address_cells(node: &Node<'_>) -> usize { + property_u32(node, "#address-cells").unwrap_or(2) as usize +} + +#[cfg(target_arch = "loongarch64")] +fn has_compatible(node: &Node<'_>, needle: &str) -> bool { + node.compatibles().any(|compatible| compatible == needle) +} + +#[cfg(target_arch = "loongarch64")] +fn has_compatible_part(node: &Node<'_>, needle: &str) -> bool { + node.compatibles() + .any(|compatible| compatible.contains(needle)) +} + +#[cfg(target_arch = "loongarch64")] +fn is_interrupt_controller(node: &Node<'_>) -> bool { + node.find_property("interrupt-controller").is_some() +} + +#[cfg(target_arch = "loongarch64")] +fn is_enabled_node(node: &Node<'_>) -> bool { + !matches!(node.status(), Some(Status::Disabled)) +} + +#[cfg(target_arch = "loongarch64")] +fn interrupt_ids_for_parent(node: &Node<'_>, parent_phandle: usize) -> Vec { + if interrupt_parent_phandle(node) != Some(parent_phandle) { + return Vec::new(); + } + + node.interrupts() + .map(|interrupts| { + interrupts + .filter_map(|mut interrupt| interrupt.next().map(|id| id as usize)) + .collect() + }) + .unwrap_or_default() +} + +#[cfg(target_arch = "loongarch64")] +fn interrupts_extended_for_parent( + node: &Node<'_>, + phandle_nodes: &BTreeMap>, + parent_phandle: usize, +) -> Vec { + let cells = property_u32_list(node, "interrupts-extended"); + if cells.is_empty() { + return Vec::new(); + } + + let mut result = Vec::new(); + let mut index = 0usize; + while index < cells.len() { + let phandle = cells[index] as usize; + index += 1; + + let interrupt_cells = phandle_nodes + .get(&phandle) + .map(node_interrupt_cells) + .unwrap_or(1); + + if index + interrupt_cells > cells.len() { + warn!( + "LoongArch interrupts-extended in node {} has truncated tuple at cell {}", + node.name(), + index - 1 + ); + break; + } + + if phandle == parent_phandle && interrupt_cells > 0 { + result.push(cells[index] as usize); + } + index += interrupt_cells; + } + + result +} + +#[cfg(target_arch = "loongarch64")] +fn direct_interrupt_ids_for_parent( + node: &Node<'_>, + phandle_nodes: &BTreeMap>, + parent_phandle: usize, +) -> Vec { + let mut ids = interrupt_ids_for_parent(node, parent_phandle); + ids.extend(interrupts_extended_for_parent( + node, + phandle_nodes, + parent_phandle, + )); + ids +} + +#[cfg(target_arch = "loongarch64")] +fn first_direct_interrupt_id_for_parent( + node: &Node<'_>, + phandle_nodes: &BTreeMap>, + parent_phandle: usize, +) -> Option { + direct_interrupt_ids_for_parent(node, phandle_nodes, parent_phandle) + .into_iter() + .next() +} + +#[cfg(target_arch = "loongarch64")] +fn add_loongarch_irq_route( + routes: &mut BTreeSet, + physical_irq: usize, + guest_vector: usize, + source: &str, +) { + let route = LoongArchGuestIrqRoute { + physical_irq, + guest_vector, + }; + if routes.insert(route) { + debug!( + "LoongArch guest IRQ route from DTB: physical_irq={}, guest_vector={}, source={}", + physical_irq, guest_vector, source + ); + } +} + +#[cfg(target_arch = "loongarch64")] +fn parse_loongarch_pci_interrupt_map( + node: &Node<'_>, + phandle_nodes: &BTreeMap>, + pch_pic_phandle: usize, + pch_pic_base_vec: usize, + eiointc_guest_vector: usize, + routes: &mut BTreeSet, +) { + let interrupt_map = property_u32_list(node, "interrupt-map"); + if interrupt_map.is_empty() { + return; + } + + let child_address_cells = node_address_cells(node); + let child_interrupt_cells = node_interrupt_cells(node); + let child_cells = child_address_cells + child_interrupt_cells; + let mut index = 0usize; + + while index + child_cells < interrupt_map.len() { + let parent_phandle = interrupt_map[index + child_cells] as usize; + let Some(parent_node) = phandle_nodes.get(&parent_phandle) else { + warn!( + "LoongArch PCI interrupt-map parent phandle {:#x} not found in node {}", + parent_phandle, + node.name() + ); + break; + }; + let parent_interrupt_cells = node_interrupt_cells(parent_node); + let entry_cells = child_cells + 1 + parent_interrupt_cells; + if index + entry_cells > interrupt_map.len() { + warn!( + "LoongArch PCI interrupt-map in node {} has truncated entry at cell {}", + node.name(), + index + ); + break; + } + + if parent_phandle == pch_pic_phandle && parent_interrupt_cells > 0 { + let parent_irq = interrupt_map[index + child_cells + 1] as usize; + add_loongarch_irq_route( + routes, + pch_pic_base_vec + parent_irq, + eiointc_guest_vector, + node.name(), + ); + } + index += entry_cells; + } +} + +#[cfg(target_arch = "loongarch64")] +pub fn parse_loongarch_guest_irq_routes(vm_cfg: &AxVMConfig, dtb: &[u8]) -> AxResult { + let fdt = Fdt::from_bytes(dtb).map_err(|e| { + ax_err_type!( + InvalidData, + format!("Failed to parse DTB image while reading LoongArch IRQ routes: {e:#?}") + ) + })?; + let all_nodes: Vec<_> = fdt.all_nodes().collect(); + let mut phandle_nodes = BTreeMap::new(); + let mut eiointc = None; + let mut pch_pic = None; + + for node in &all_nodes { + if let Some(phandle) = node_phandle(node) { + phandle_nodes.insert(phandle, node.clone()); + } + if has_compatible(node, "loongson,ls2k2000-eiointc") { + eiointc = Some(node.clone()); + } + if has_compatible_part(node, "pch-pic") { + pch_pic = Some(node.clone()); + } + } + + let Some(eiointc) = eiointc else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC node not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + let Some(pch_pic) = pch_pic else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: PCH-PIC node not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + + let Some(pch_pic_phandle) = node_phandle(&pch_pic) else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: PCH-PIC phandle not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + let Some(eiointc_parent_phandle) = interrupt_parent_phandle(&eiointc) else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC interrupt parent not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + let Some(eiointc_guest_vector) = + first_direct_interrupt_id_for_parent(&eiointc, &phandle_nodes, eiointc_parent_phandle) + else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC CPU vector not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + + let pch_pic_base_vec = property_u32(&pch_pic, "loongson,pic-base-vec").unwrap_or(0) as usize; + let mut routes = BTreeSet::new(); + + for node in &all_nodes { + if !is_enabled_node(node) || is_interrupt_controller(node) { + continue; + } + + for physical_irq in direct_interrupt_ids_for_parent(node, &phandle_nodes, pch_pic_phandle) { + add_loongarch_irq_route( + &mut routes, + pch_pic_base_vec + physical_irq, + eiointc_guest_vector, + node.name(), + ); + } + + parse_loongarch_pci_interrupt_map( + node, + &phandle_nodes, + pch_pic_phandle, + pch_pic_base_vec, + eiointc_guest_vector, + &mut routes, + ); + } + + let routes = routes.into_iter().collect::>(); + info!( + "VM[{}] LoongArch guest IRQ routes parsed from DTB: {:?}", + vm_cfg.id(), + routes + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), routes); + Ok(()) +} + #[cfg(test)] mod tests { use super::align_reserved_region_4k; diff --git a/os/axvisor/src/manager.rs b/os/axvisor/src/manager.rs index b306aa8880..fdd5493d1d 100644 --- a/os/axvisor/src/manager.rs +++ b/os/axvisor/src/manager.rs @@ -22,6 +22,13 @@ pub struct AxvmManager { impl AxvmManager { /// Initialize the AxVM runtime services. pub fn new() -> AxResult { + #[cfg(target_arch = "loongarch64")] + { + ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::register_virtual_irq_injector( + inject_loongarch_platform_irq, + ); + ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::enable_external_irq_line(); + } Ok(Self { runtime: AxvmRuntime::new()?, }) @@ -30,6 +37,8 @@ impl AxvmManager { /// Load and initialize the default VM set. pub fn init_default_vms(&self) { crate::config::init_guest_vms(); + #[cfg(target_arch = "loongarch64")] + init_loongarch_passthrough_irq_routes(); self.runtime.init_vms(); self.release_host_filesystem_for_guest_passthrough(); } @@ -210,3 +219,48 @@ impl AxvmManager { Self::read_file_exact(file_name, size) } } + +#[cfg(target_arch = "loongarch64")] +fn inject_loongarch_platform_irq(vm_id: usize, vcpu_id: usize, vector: usize) { + if let Err(err) = axvm::inject_vm_vcpu_interrupt(vm_id, vcpu_id, vector) { + warn!( + "failed to inject LoongArch platform IRQ {vector:#x} for VM[{vm_id}] VCpu[{vcpu_id}]: \ + {err:?}" + ); + } +} + +#[cfg(target_arch = "loongarch64")] +fn init_loongarch_passthrough_irq_routes() { + let mut matched = 0usize; + for vm in axvm::get_vm_list() { + let passthrough = vm.with_config(|cfg| !cfg.pass_through_devices().is_empty()); + if !passthrough { + continue; + } + + matched += 1; + let vcpu_id = 0usize; + let routes = crate::fdt::get_loongarch_guest_irq_routes(vm.id()); + if routes.is_empty() { + warn!( + "VM[{}] has passthrough devices but no LoongArch guest IRQ route parsed from DTB", + vm.id() + ); + continue; + } + + for route in routes { + ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::register_guest_irq_route( + route.physical_irq, + vm.id(), + vcpu_id, + route.guest_vector, + ); + } + } + + if matched > 1 { + warn!("LoongArch passthrough IRQ routing matched {matched} VMs; check per-IRQ ownership"); + } +} diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs index a24172d892..fed51d3cee 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs @@ -1,3 +1,6 @@ +#[cfg(feature = "hypervisor")] +use core::sync::atomic::{AtomicPtr, AtomicUsize, Ordering}; + use ax_plat::irq::{IpiTarget, IrqIf, dispatch_irq}; use loongArch64::{ iocsr::{iocsr_read_w, iocsr_write_w}, @@ -13,6 +16,9 @@ use crate::config::devices::{EIOINTC_IRQ, IPI_IRQ, TIMER_IRQ}; mod eiointc; mod pch_pic; +/// The maximum number of hypervisor-routed IRQs. +#[cfg(feature = "hypervisor")] +pub const MAX_IRQ_COUNT: usize = 256; const IOCSR_IPI_SEND_CPU_SHIFT: u32 = 16; const IOCSR_IPI_SEND_BLOCKING: u32 = 1 << 31; @@ -22,6 +28,21 @@ const IOCSR_IPI_STATUS: usize = 0x1000; const IOCSR_IPI_ENABLE: usize = 0x1004; const IOCSR_IPI_CLEAR: usize = 0x100c; const IOCSR_IPI_SEND: usize = 0x1040; +#[cfg(feature = "hypervisor")] +const IRQ_ROUTE_NONE: usize = 0; +#[cfg(feature = "hypervisor")] +const IRQ_TARGET_NONE: usize = usize::MAX; +#[cfg(feature = "hypervisor")] +const IRQ_TARGET_VM_SHIFT: usize = 32; + +#[cfg(feature = "hypervisor")] +static VIRTUAL_IRQ_INJECTOR: AtomicPtr<()> = AtomicPtr::new(core::ptr::null_mut()); +#[cfg(feature = "hypervisor")] +static GUEST_IRQ_ROUTES: [AtomicUsize; MAX_IRQ_COUNT] = + [const { AtomicUsize::new(IRQ_ROUTE_NONE) }; MAX_IRQ_COUNT]; +#[cfg(feature = "hypervisor")] +static GUEST_IRQ_TARGETS: [AtomicUsize; MAX_IRQ_COUNT] = + [const { AtomicUsize::new(IRQ_TARGET_NONE) }; MAX_IRQ_COUNT]; fn make_ipi_send_value(cpu_id: usize, vector: u32, blocking: bool) -> u32 { let mut value = (cpu_id as u32) << IOCSR_IPI_SEND_CPU_SHIFT | vector; @@ -31,6 +52,70 @@ fn make_ipi_send_value(cpu_id: usize, vector: u32, blocking: bool) -> u32 { value } +/// Registers the virtual interrupt injector used by hypervisor builds. +#[cfg(feature = "hypervisor")] +pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize)) { + VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); + info!("LoongArch platform virtual IRQ injector registered"); +} + +#[cfg(feature = "hypervisor")] +fn encode_guest_vector(vector: usize) -> usize { + vector + 1 +} + +#[cfg(feature = "hypervisor")] +fn decode_guest_vector(encoded: usize) -> Option { + (encoded != IRQ_ROUTE_NONE).then_some(encoded - 1) +} + +#[cfg(feature = "hypervisor")] +fn encode_guest_target(vm_id: usize, vcpu_id: usize) -> usize { + (vm_id << IRQ_TARGET_VM_SHIFT) | vcpu_id +} + +#[cfg(feature = "hypervisor")] +fn decode_guest_target(encoded: usize) -> Option<(usize, usize)> { + (encoded != IRQ_TARGET_NONE).then_some(( + encoded >> IRQ_TARGET_VM_SHIFT, + encoded & ((1usize << IRQ_TARGET_VM_SHIFT) - 1), + )) +} + +#[cfg(feature = "hypervisor")] +fn guest_route(physical_irq: usize) -> Option<(usize, usize, usize)> { + if physical_irq >= MAX_IRQ_COUNT { + return None; + } + let guest_vector = decode_guest_vector(GUEST_IRQ_ROUTES[physical_irq].load(Ordering::Acquire))?; + let (vm_id, vcpu_id) = + decode_guest_target(GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire))?; + Some((vm_id, vcpu_id, guest_vector)) +} + +/// Routes one physical EIOINTC/PCH-PIC IRQ to a guest CPU interrupt vector. +#[cfg(feature = "hypervisor")] +pub fn register_guest_irq_route( + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, +) { + if physical_irq >= MAX_IRQ_COUNT { + warn!("LoongArch guest IRQ route ignored: physical IRQ {physical_irq} out of range"); + return; + } + + GUEST_IRQ_ROUTES[physical_irq].store(encode_guest_vector(guest_vector), Ordering::Release); + GUEST_IRQ_TARGETS[physical_irq].store(encode_guest_target(vm_id, vcpu_id), Ordering::Release); + eiointc::enable_irq(physical_irq); + pch_pic::enable_irq(physical_irq); + debug!( + "LoongArch guest IRQ route: physical_irq={}, target=VM[{}] VCpu[{}], guest_vector={}", + physical_irq, vm_id, vcpu_id, guest_vector + ); +} + pub(crate) fn init() { eiointc::init(); pch_pic::init(); @@ -67,6 +152,7 @@ impl IrqType { match self { IrqType::Timer => Some(LineBasedInterrupt::TIMER), IrqType::Ipi => Some(LineBasedInterrupt::IPI), + IrqType::Io => LineBasedInterrupt::from_bits(1 << EIOINTC_IRQ), _ => None, } } @@ -123,6 +209,30 @@ impl IrqIf for IrqIfImpl { debug!("Spurious external IRQ"); return None; }; + + #[cfg(feature = "hypervisor")] + if let Some((vm_id, vcpu_id, guest_vector)) = guest_route(ex_irq) { + let injector = VIRTUAL_IRQ_INJECTOR.load(Ordering::Acquire); + if injector.is_null() { + warn!( + "LoongArch guest-owned IRQ {ex_irq} has no virtual IRQ injector; leaving \ + it pending for guest" + ); + return Some(ex_irq); + } + + // SAFETY: The injector is registered through + // register_virtual_irq_injector as a valid function pointer. + unsafe { + core::mem::transmute::<*mut (), fn(usize, usize, usize)>(injector)( + vm_id, + vcpu_id, + guest_vector, + ); + } + return Some(ex_irq); + } + irq = IrqType::Ex(ex_irq); } @@ -194,3 +304,20 @@ impl IrqIf for IrqIfImpl { } } } + +#[cfg(feature = "hypervisor")] +#[impl_plat_interface] +impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { + fn register_virtual_irq_injector(injector: fn(usize, usize, usize)) { + register_virtual_irq_injector(injector); + } + + fn register_guest_irq_route( + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, + ) { + register_guest_irq_route(physical_irq, vm_id, vcpu_id, guest_vector); + } +} diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs index d77b0cfa23..3c0579ad29 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs @@ -64,16 +64,6 @@ pub fn enable_irq(irq: usize) { } } -#[cfg(feature = "hypervisor")] -pub fn debug_snapshot(irq: usize) -> (u64, u64, u64) { - let (offset, _) = split_bit(irq); - ( - iocsr_read_d(EIOINTC_REG_ENABLE + offset), - iocsr_read_d(EIOINTC_REG_BOUNCE + offset), - iocsr_read_d(EIOINTC_REG_ISR + offset), - ) -} - pub fn disable_irq(irq: usize) { let (offset, bit) = split_bit(irq); let addr = EIOINTC_REG_ENABLE + offset; diff --git a/platforms/ax-plat/src/irq.rs b/platforms/ax-plat/src/irq.rs index 8c55eef57a..6db9f30975 100644 --- a/platforms/ax-plat/src/irq.rs +++ b/platforms/ax-plat/src/irq.rs @@ -269,3 +269,41 @@ pub trait IrqIf { /// Sends an inter-processor interrupt (IPI) to the specified target CPU or all CPUs. fn send_ipi(irq_num: usize, target: IpiTarget); } + +/// LoongArch hypervisor IRQ routing extension. +#[cfg(target_arch = "loongarch64")] +#[def_plat_interface] +pub trait LoongArchHvIrqIf { + /// Registers the virtual interrupt injector used by hypervisor builds. + fn register_virtual_irq_injector(injector: fn(usize, usize, usize)); + + /// Routes one physical EIOINTC/PCH-PIC IRQ to a guest CPU interrupt vector. + fn register_guest_irq_route( + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, + ); +} + +/// Registers the virtual interrupt injector used by LoongArch hypervisor builds. +#[cfg(target_arch = "loongarch64")] +pub fn register_loongarch_virtual_irq_injector(injector: fn(usize, usize, usize)) { + crate::__priv::call_interface!(LoongArchHvIrqIf::register_virtual_irq_injector(injector)); +} + +/// Routes one physical EIOINTC/PCH-PIC IRQ to a LoongArch guest CPU interrupt vector. +#[cfg(target_arch = "loongarch64")] +pub fn register_loongarch_guest_irq_route( + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, +) { + crate::__priv::call_interface!(LoongArchHvIrqIf::register_guest_irq_route( + physical_irq, + vm_id, + vcpu_id, + guest_vector + )); +} diff --git a/virtualization/axvcpu/src/vcpu.rs b/virtualization/axvcpu/src/vcpu.rs index 70e92e9e13..e52e812edd 100644 --- a/virtualization/axvcpu/src/vcpu.rs +++ b/virtualization/axvcpu/src/vcpu.rs @@ -198,7 +198,7 @@ impl AxVCpu { /// Execute a block with the state of the VCpu transitioned from `from` to `to`. If the current state is not `from`, return an error. /// - /// The state will be set to [`VCpuState::Invalid`] if an error occurs (including the case that the current state is not `from`). + /// The state will be set to [`VCpuState::Invalid`] if the transition body returns an error. /// /// The state will be set to `to` if the block is executed successfully. pub fn with_state_transition(&self, from: VCpuState, to: VCpuState, f: F) -> AxResult @@ -206,10 +206,9 @@ impl AxVCpu { F: FnOnce() -> AxResult, { { - let mut inner_mut = self.inner_mut.lock(); + let inner_mut = self.inner_mut.lock(); if inner_mut.state != from { let current_state = inner_mut.state; - inner_mut.state = VCpuState::Invalid; return ax_err!( BadState, format!("VCpu state is not {from:?}, but {current_state:?}") diff --git a/virtualization/axvm/src/arch.rs b/virtualization/axvm/src/arch.rs index b83c2b29cc..903268f018 100644 --- a/virtualization/axvm/src/arch.rs +++ b/virtualization/axvm/src/arch.rs @@ -189,11 +189,14 @@ pub(crate) fn register_platform_irq_injector() {} #[cfg(target_arch = "loongarch64")] mod loongarch64 { + use alloc::boxed::Box; + use core::time::Duration; + use ax_crate_interface::impl_interface; use ax_memory_addr::{PhysAddr, VirtAddr}; use loongarch_vcpu::host::LoongArchVcpuHostIf; - use crate::host::{HostMemory, default_host}; + use crate::host::{HostMemory, HostTime, default_host}; struct LoongArchVcpuHostIfImpl; @@ -202,6 +205,34 @@ mod loongarch64 { fn virt_to_phys(vaddr: VirtAddr) -> PhysAddr { default_host().virt_to_phys(vaddr) } + + fn current_time_nanos() -> u64 { + default_host().monotonic_time().as_nanos() as u64 + } + + fn ticks_to_nanos(ticks: u64) -> u64 { + ax_std::os::arceos::modules::ax_hal::time::ticks_to_nanos(ticks) + } + + fn register_timer( + deadline: Duration, + callback: Box, + ) -> usize { + default_host().register_timer(deadline.as_nanos() as u64, callback) + } + + fn cancel_timer(token: usize) { + default_host().cancel_timer(token); + } + + fn inject_interrupt(vm_id: usize, vcpu_id: usize, vector: usize) { + if let Err(err) = crate::runtime::vcpus::queue_interrupt(vm_id, vcpu_id, vector) { + warn!( + "failed to queue LoongArch interrupt {vector:#x} for VM[{vm_id}] \ + VCpu[{vcpu_id}]: {err:?}" + ); + } + } } } diff --git a/virtualization/axvm/src/host/arceos.rs b/virtualization/axvm/src/host/arceos.rs index 22a5abbd31..b66d622626 100644 --- a/virtualization/axvm/src/host/arceos.rs +++ b/virtualization/axvm/src/host/arceos.rs @@ -2,7 +2,11 @@ extern crate alloc; -#[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] +#[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" +))] use alloc::boxed::Box; use core::{ sync::atomic::{AtomicUsize, Ordering}, @@ -84,11 +88,16 @@ impl HostTime for ArceOsHost { modules::ax_hal::time::monotonic_time() } + #[cfg(not(target_arch = "loongarch64"))] fn set_oneshot_timer(&self, deadline_ns: u64) { modules::ax_hal::time::set_oneshot_timer(deadline_ns); } - #[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] + #[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" + ))] fn register_timer( &self, deadline_ns: u64, @@ -97,7 +106,7 @@ impl HostTime for ArceOsHost { crate::timer::register_timer(deadline_ns, callback) } - #[cfg(target_arch = "x86_64")] + #[cfg(any(target_arch = "x86_64", target_arch = "loongarch64"))] fn cancel_timer(&self, token: Self::CancelToken) { crate::timer::cancel_timer(token); } diff --git a/virtualization/axvm/src/host/traits.rs b/virtualization/axvm/src/host/traits.rs index c6f711ed11..0e1793fe28 100644 --- a/virtualization/axvm/src/host/traits.rs +++ b/virtualization/axvm/src/host/traits.rs @@ -2,7 +2,11 @@ extern crate alloc; -#[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] +#[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" +))] use alloc::boxed::Box; use core::time::Duration; @@ -47,10 +51,15 @@ pub trait HostTime { fn monotonic_time(&self) -> Duration; /// Program the host one-shot timer. + #[cfg(not(target_arch = "loongarch64"))] fn set_oneshot_timer(&self, deadline_ns: u64); /// Register a VM timer callback. - #[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] + #[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" + ))] fn register_timer( &self, deadline_ns: u64, @@ -58,7 +67,7 @@ pub trait HostTime { ) -> Self::CancelToken; /// Cancel a VM timer callback. - #[cfg(target_arch = "x86_64")] + #[cfg(any(target_arch = "x86_64", target_arch = "loongarch64"))] fn cancel_timer(&self, token: Self::CancelToken); } diff --git a/virtualization/axvm/src/lib.rs b/virtualization/axvm/src/lib.rs index 31a63b254a..37b65f7b0f 100644 --- a/virtualization/axvm/src/lib.rs +++ b/virtualization/axvm/src/lib.rs @@ -47,6 +47,8 @@ pub(crate) use host::{ task::{AxTaskExt, AxTaskRef, TaskInner, WaitQueue, WaitQueueHandle as HostWaitQueueHandle}, }; pub use irq::InterruptFabric; +#[cfg(target_arch = "loongarch64")] +pub use manager::inject_vm_vcpu_interrupt; pub use manager::{ AxvmRuntime, current_vcpu_id, current_vm_id, get_vm_by_id, get_vm_list, inject_current_vcpu_interrupt, register_vm, diff --git a/virtualization/axvm/src/manager.rs b/virtualization/axvm/src/manager.rs index 8b89016c76..779acdeafc 100644 --- a/virtualization/axvm/src/manager.rs +++ b/virtualization/axvm/src/manager.rs @@ -83,6 +83,22 @@ pub(crate) fn inject_interrupt(vm_id: VMId, vcpu_id: usize, vector: usize) -> Ax crate::runtime::vcpus::queue_interrupt(vm_id, vcpu_id, vector) } +/// Inject a virtual interrupt into a VM's vCPU. +#[cfg(target_arch = "loongarch64")] +pub fn inject_vm_vcpu_interrupt(vm_id: VMId, vcpu_id: usize, vector: usize) -> AxResult { + use crate::AsVCpuTask; + + let current = crate::host::task::current_task(); + if let Some(task) = current.try_as_vcpu_task() + && task.vm().id() == vm_id + && task.vcpu.id() == vcpu_id + { + return task.vcpu.inject_interrupt(vector); + } + + crate::runtime::vcpus::queue_interrupt(vm_id, vcpu_id, vector) +} + /// Return the current VM ID from the vCPU currently executing on this CPU. pub fn current_vm_id() -> Option { get_current_vcpu::().map(|vcpu| vcpu.vm_id()) diff --git a/virtualization/axvm/src/runtime/vcpus.rs b/virtualization/axvm/src/runtime/vcpus.rs index 9d2a721f57..531d9908ea 100644 --- a/virtualization/axvm/src/runtime/vcpus.rs +++ b/virtualization/axvm/src/runtime/vcpus.rs @@ -556,6 +556,26 @@ fn vcpu_run() { #[cfg(not(target_arch = "x86_64"))] wait(&vm_vcpus) } + AxVCpuExitReason::Idle => { + trace!("VM[{vm_id}] run VCpu[{vcpu_id}] Idle"); + #[cfg(target_arch = "loongarch64")] + { + crate::check_timer_events(); + if vcpu.get_arch_vcpu().has_enabled_pending_interrupt() { + continue; + } + let idle_timeout = vcpu.get_arch_vcpu().idle_wait_timeout(); + ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(true); + ax_std::os::arceos::modules::ax_hal::asm::enable_irqs(); + ax_std::os::arceos::modules::ax_hal::time::busy_wait(idle_timeout); + ax_std::os::arceos::modules::ax_hal::asm::disable_irqs(); + ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(false); + } + #[cfg(not(target_arch = "loongarch64"))] + { + crate::check_timer_events(); + } + } AxVCpuExitReason::Nothing => {} AxVCpuExitReason::CpuDown { _state } => { warn!("VM[{vm_id}] run VCpu[{vcpu_id}] CpuDown state {_state:#x}"); diff --git a/virtualization/axvm/src/task.rs b/virtualization/axvm/src/task.rs index 57fde4d6e6..ef73fd1464 100644 --- a/virtualization/axvm/src/task.rs +++ b/virtualization/axvm/src/task.rs @@ -42,14 +42,19 @@ impl TaskExt for VCpuTask {} /// Access a vCPU task extension from an ArceOS task. pub trait AsVCpuTask { + /// Return this task's vCPU extension if it has one. + fn try_as_vcpu_task(&self) -> Option<&VCpuTask>; + /// Return this task's vCPU extension. fn as_vcpu_task(&self) -> &VCpuTask; } impl AsVCpuTask for TaskInner { + fn try_as_vcpu_task(&self) -> Option<&VCpuTask> { + self.task_ext().map(|ext| ext.downcast_ref::()) + } + fn as_vcpu_task(&self) -> &VCpuTask { - self.task_ext() - .expect("Not a VCpuTask") - .downcast_ref::() + self.try_as_vcpu_task().expect("Not a VCpuTask") } } diff --git a/virtualization/axvm/src/timer.rs b/virtualization/axvm/src/timer.rs index 25eb1c350a..da674abc30 100644 --- a/virtualization/axvm/src/timer.rs +++ b/virtualization/axvm/src/timer.rs @@ -3,9 +3,17 @@ extern crate alloc; use alloc::boxed::Box; -#[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] +#[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" +))] use core::sync::atomic::{AtomicUsize, Ordering}; -#[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] +#[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" +))] use core::time::Duration; use ax_kspin::SpinNoIrq; @@ -14,25 +22,33 @@ use ax_timer_list::{TimeValue, TimerEvent, TimerList}; use crate::host::{HostTime, default_host}; -#[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] +#[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" +))] static TOKEN: AtomicUsize = AtomicUsize::new(0); struct VmTimerEvent { - #[cfg(target_arch = "x86_64")] + #[cfg(any(target_arch = "x86_64", target_arch = "loongarch64"))] token: usize, callback: Box, } impl VmTimerEvent { - #[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] + #[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" + ))] fn new(token: usize, callback: F) -> Self where F: FnOnce(TimeValue) + Send + 'static, { - #[cfg(not(target_arch = "x86_64"))] + #[cfg(not(any(target_arch = "x86_64", target_arch = "loongarch64")))] let _ = token; Self { - #[cfg(target_arch = "x86_64")] + #[cfg(any(target_arch = "x86_64", target_arch = "loongarch64"))] token, callback: Box::new(callback), } @@ -48,7 +64,11 @@ impl TimerEvent for VmTimerEvent { #[ax_percpu::def_percpu] static TIMER_LIST: LazyInit>> = LazyInit::new(); -#[cfg(any(target_arch = "x86_64", target_arch = "aarch64"))] +#[cfg(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "loongarch64" +))] pub(crate) fn register_timer( deadline_ns: u64, callback: Box, @@ -69,7 +89,7 @@ pub(crate) fn register_timer( token } -#[cfg(target_arch = "x86_64")] +#[cfg(any(target_arch = "x86_64", target_arch = "loongarch64"))] pub(crate) fn cancel_timer(token: usize) { let next_deadline = { // SAFETY: The timer list is initialized for each CPU before VM timer @@ -100,6 +120,9 @@ pub(crate) fn check_events() { } fn rearm_host_timer(next_deadline: Option) { + #[cfg(target_arch = "loongarch64")] + let _ = next_deadline; + #[cfg(not(target_arch = "loongarch64"))] if let Some(deadline) = next_deadline { default_host().set_oneshot_timer(deadline.as_nanos() as u64); } @@ -111,4 +134,6 @@ pub(crate) fn init_percpu() { // CPU can register VM timers. let timer_list = unsafe { TIMER_LIST.current_ref_mut_raw() }; timer_list.init_once(SpinNoIrq::new(TimerList::new())); + #[cfg(target_arch = "loongarch64")] + ax_std::os::arceos::modules::ax_task::register_timer_callback(|_| check_events()); } diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index ab4ac5c69f..03f5ee7dff 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -27,7 +27,7 @@ use axdevice::{ use axdevice_base::AccessWidth; #[cfg(target_arch = "aarch64")] use axdevice_base::DeviceRegistry as _; -use axvcpu::{AxVCpu, AxVCpuExitReason}; +use axvcpu::{AxVCpu, AxVCpuExitReason, VCpuState}; #[cfg(target_arch = "x86_64")] use axvm_types::EmulatedDeviceType; use axvm_types::{GuestPhysAddr, HostPhysAddr, HostVirtAddr}; @@ -611,13 +611,23 @@ impl AxVM { /// ## Returns /// * `AxVCpuExitReason` - the exit reason of the vCPU, wrapped in an `AxResult`. pub fn run_vcpu(&self, vcpu_id: usize) -> AxResult { + let vm_id = self.id(); let vcpu = self .vcpu(vcpu_id) .ok_or_else(|| ax_err_type!(InvalidInput, "Invalid vcpu_id"))?; - vcpu.bind()?; + match vcpu.state() { + VCpuState::Free => vcpu.bind()?, + VCpuState::Ready => {} + state => { + return ax_err!( + BadState, + format!("VCpu state is not Free or Ready, but {state:?}") + ); + } + } - let exit_reason = vcpu.with_current_cpu_set(|| -> AxResult { + let run_result = vcpu.with_current_cpu_set(|| -> AxResult { loop { crate::runtime::vcpus::inject_pending_interrupts(self.id(), vcpu_id, &vcpu); @@ -680,10 +690,23 @@ impl AxVM { exit_reason => break Ok(exit_reason), } } - })?; + }); - vcpu.unbind()?; - Ok(exit_reason) + let unbind_result = vcpu.unbind(); + match run_result { + Ok(exit_reason) => { + unbind_result?; + Ok(exit_reason) + } + Err(err) => { + if let Err(unbind_err) = unbind_result { + warn!( + "VM[{vm_id}] VCpu[{vcpu_id}] unbind after run error failed: {unbind_err:?}" + ); + } + Err(err) + } + } } fn handle_nested_page_fault(&self, addr: GuestPhysAddr, access_flags: MappingFlags) -> bool { diff --git a/virtualization/loongarch_vcpu/src/exception.rs b/virtualization/loongarch_vcpu/src/exception.rs index 7dd5af3a15..368bd33f10 100644 --- a/virtualization/loongarch_vcpu/src/exception.rs +++ b/virtualization/loongarch_vcpu/src/exception.rs @@ -1,7 +1,10 @@ +use alloc::boxed::Box; +use core::time::Duration; + use ax_errno::AxResult; -use axvcpu::{AxVCpuExitReason, GuestPhysAddr, MappingFlags}; +use axvcpu::{AxVCpuExitReason, GuestPhysAddr, MappingFlags, VCpuId, VMId}; -use crate::context_frame::LoongArchContextFrame; +use crate::{context_frame::LoongArchContextFrame, host}; const ECODE_HVC: usize = 0x17; const ECODE_GSPR: usize = 0x16; @@ -24,6 +27,25 @@ const INT_IPI: usize = 12; const TIMER_BIT: usize = 1 << INT_TIMER; const IPI_BIT: usize = 1 << INT_IPI; const HWI_MASK: usize = ((1 << (INT_HWI7 + 1)) - 1) & !((1 << INT_HWI0) - 1); +const CSR_TICLR_TI: usize = 0x1; +const CSR_TCFG_EN: usize = 1 << 0; +const CSR_TCFG_PERIODIC: usize = 1 << 1; +const CSR_TCFG_INITVAL_MASK: usize = !0x3; +const CSR_CRMD_PLV_MASK: usize = 0b11; +const CSR_CRMD_IE: usize = 1 << 2; +const CSR_CRMD_DA: usize = 1 << 3; +const CSR_CRMD_PG: usize = 1 << 4; +const CSR_ESTAT_EXC_MASK: usize = (0x3f << 16) | (0x1ff << 22); +const CSR_ECFG_VS_SHIFT: usize = 16; +const CSR_ECFG_VS_MASK: usize = 0b111 << CSR_ECFG_VS_SHIFT; +const CSR_TLBRERA_ISTLBR: usize = 1; +const CSR_TLBREHI_PS_MASK: usize = 0x3f; +const CSR_TLBREHI_VPPN_MASK: usize = 0x0000_ffff_ffff_e000; +const DEFAULT_TLB_PAGE_SHIFT: usize = 12; +const GUEST_RAM_START: usize = 0x0008_0000; +const QEMU_VIRT_MMIO_START: usize = 0x1000_0000; +const QEMU_VIRT_MMIO_END: usize = 0x8000_0000; +const GUEST_RAM_END: usize = QEMU_VIRT_MMIO_START; #[repr(u8)] #[derive(Debug, Clone, Copy, PartialEq, Eq)] @@ -52,14 +74,141 @@ fn get_exception_subcode(ctx: &LoongArchContextFrame) -> usize { (ctx.host_estat >> 22) & 0x1ff } +fn is_host_tlb_refill(ctx: &LoongArchContextFrame) -> bool { + ctx.host_tlbrera & 0x1 != 0 +} + fn get_guest_pc(ctx: &LoongArchContextFrame) -> usize { - if ctx.host_era != 0 { + if is_host_tlb_refill(ctx) { + ctx.host_tlbrera & !0x1 + } else if ctx.host_era != 0 { ctx.host_era } else { ctx.gcsr_era } } +fn direct_map_guest_addr_to_gpa(addr: usize) -> usize { + if matches!(addr >> 48, 0x8000 | 0x9000 | 0xa000) { + addr & 0x0000_ffff_ffff_ffff + } else if matches!(addr >> 44, 0x8..=0xa) { + addr & 0x0000_0fff_ffff_ffff + } else { + addr + } +} + +fn get_refill_access_flags(ctx: &LoongArchContextFrame) -> MappingFlags { + let badv = direct_map_guest_addr_to_gpa(get_badv(ctx)); + let pc_gpa = direct_map_guest_addr_to_gpa(get_guest_pc(ctx)); + if badv == pc_gpa { + MappingFlags::EXECUTE + } else { + MappingFlags::READ | MappingFlags::WRITE + } +} + +fn guest_paging_enabled(ctx: &LoongArchContextFrame) -> bool { + ctx.gcsr_crmd & CSR_CRMD_PG != 0 +} + +fn is_guest_direct_mapped_va(addr: usize) -> bool { + matches!(addr >> 48, 0x8000 | 0x9000 | 0xa000) || matches!(addr >> 44, 0x8..=0xa) +} + +fn is_known_guest_physical_addr(addr: usize) -> bool { + (GUEST_RAM_START..GUEST_RAM_END).contains(&addr) + || (QEMU_VIRT_MMIO_START..QEMU_VIRT_MMIO_END).contains(&addr) +} + +fn should_inject_guest_virtual_fault( + ctx: &LoongArchContextFrame, + badv: usize, + from_tlb_refill: bool, +) -> bool { + let is_direct = is_guest_direct_mapped_va(badv); + let known_physical = is_known_guest_physical_addr(badv); + + if from_tlb_refill { + if ctx.gcsr_tlbrentry == 0 || is_direct { + false + } else { + !known_physical + } + } else if !guest_paging_enabled(ctx) || is_direct || ctx.gcsr_eentry == 0 { + false + } else { + !known_physical + } +} + +fn guest_exception_vector_size(ctx: &LoongArchContextFrame) -> usize { + let vs = (ctx.gcsr_ectl & CSR_ECFG_VS_MASK) >> CSR_ECFG_VS_SHIFT; + if vs == 0 { 0 } else { (1 << vs) * 4 } +} + +fn guest_pgd(ctx: &LoongArchContextFrame) -> usize { + let badv = if ctx.gcsr_tlbrera & CSR_TLBRERA_ISTLBR != 0 { + ctx.gcsr_tlbrbadv + } else { + ctx.gcsr_badv + }; + + if badv >> (usize::BITS - 1) != 0 { + ctx.gcsr_pgdh + } else { + ctx.gcsr_pgdl + } +} + +fn inject_guest_regular_exception( + ctx: &mut LoongArchContextFrame, + ecode: usize, + esubcode: usize, + badv: usize, +) { + let pc = get_guest_pc(ctx); + ctx.gcsr_badv = badv; + ctx.gcsr_badi = get_badi(ctx); + ctx.gcsr_tlbehi = badv & !0x1fff; + ctx.gcsr_estat = (ctx.gcsr_estat & !CSR_ESTAT_EXC_MASK) + | ((ecode & 0x3f) << 16) + | ((esubcode & 0x1ff) << 22); + ctx.gcsr_prmd = (ctx.gcsr_prmd & !0b111) | (ctx.gcsr_crmd & (CSR_CRMD_PLV_MASK | CSR_CRMD_IE)); + ctx.gcsr_era = pc; + ctx.gcsr_crmd &= !(CSR_CRMD_PLV_MASK | CSR_CRMD_IE); + ctx.sepc = ctx.gcsr_eentry + ecode * guest_exception_vector_size(ctx); +} + +fn inject_guest_interrupt(ctx: &mut LoongArchContextFrame, vector: usize) { + let pc = get_guest_pc(ctx); + ctx.gcsr_prmd = (ctx.gcsr_prmd & !0b111) | (ctx.gcsr_crmd & (CSR_CRMD_PLV_MASK | CSR_CRMD_IE)); + ctx.gcsr_era = pc; + ctx.gcsr_crmd &= !(CSR_CRMD_PLV_MASK | CSR_CRMD_IE); + ctx.sepc = ctx.gcsr_eentry + (64 + vector) * guest_exception_vector_size(ctx); +} + +fn inject_guest_tlb_refill(ctx: &mut LoongArchContextFrame, badv: usize) { + let pc = get_guest_pc(ctx); + let page_shift = match ctx.gcsr_stlbps & CSR_TLBREHI_PS_MASK { + 0 => DEFAULT_TLB_PAGE_SHIFT, + shift => shift, + }; + let pair_mask = (1usize << (page_shift + 1)) - 1; + let vppn = (badv & !pair_mask) & CSR_TLBREHI_VPPN_MASK; + + ctx.gcsr_tlbrbadv = badv; + ctx.gcsr_tlbrehi = + (ctx.gcsr_tlbrehi & !(CSR_TLBREHI_VPPN_MASK | CSR_TLBREHI_PS_MASK)) | vppn | page_shift; + ctx.gcsr_tlbrera = (pc & !0x3) | CSR_TLBRERA_ISTLBR; + ctx.gcsr_tlbrprmd = + (ctx.gcsr_tlbrprmd & !0b111) | (ctx.gcsr_crmd & (CSR_CRMD_PLV_MASK | CSR_CRMD_IE)); + ctx.gcsr_pgd = guest_pgd(ctx); + ctx.gcsr_crmd = + (ctx.gcsr_crmd | CSR_CRMD_DA) & !(CSR_CRMD_PG | CSR_CRMD_PLV_MASK | CSR_CRMD_IE); + ctx.sepc = ctx.gcsr_tlbrentry; +} + fn get_badv(ctx: &LoongArchContextFrame) -> usize { if ctx.host_tlbrera & 0x1 != 0 { ctx.host_tlbrbadv @@ -76,6 +225,13 @@ fn get_guest_interrupt_status(ctx: &LoongArchContextFrame) -> usize { ctx.host_estat & LOCAL_INTERRUPT_MASK } +fn ack_host_timer_interrupt() { + unsafe { + let value = CSR_TICLR_TI; + core::arch::asm!("csrwr {}, 0x44", inout(reg) value => _); + } +} + fn decode_interrupt_vector(is: usize) -> Option { if is & IPI_BIT != 0 { return Some(INT_IPI); @@ -118,13 +274,21 @@ fn emulate_cpucfg(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReas AxVCpuExitReason::Nothing } -fn emulate_csrx(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { +fn emulate_csrx( + ctx: &mut LoongArchContextFrame, + ins: usize, + vm_id: VMId, + vcpu_id: VCpuId, + guest_timer_token: &mut Option, +) -> AxVCpuExitReason { let rd = extract_field(ins, 0, 5); let rj = extract_field(ins, 5, 5); let csr = extract_field(ins, 10, 14); match csr { - CSR_TCFG | CSR_TVAL | CSR_TICLR => emulate_timer_csr(ctx, rd, rj, csr), + CSR_TCFG | CSR_TVAL | CSR_TICLR => { + emulate_timer_csr(ctx, rd, rj, csr, vm_id, vcpu_id, guest_timer_token) + } _ => { match rj { 0 => log::info!("LoongArch GSPR csrrd emulation: csr={:#x}", csr), @@ -143,62 +307,122 @@ const CSR_TCFG: usize = 0x41; const CSR_TVAL: usize = 0x42; const CSR_TICLR: usize = 0x44; -/// Emulate guest timer CSR accesses by passing through to the host hardware -/// timer. In the 1:1 vCPU model the host hardware timer is shared: when the -/// guest writes TCFG/TVAL we program the actual timer so that it fires, and -/// when it fires the IRQ handler injects the interrupt into the guest ESTAT. -fn emulate_timer_csr(ctx: &mut LoongArchContextFrame, rd: usize, rj: usize, csr: usize) { - if rj == 0 { - // csrrd – read the current host hardware timer value. - let value = read_host_timer_csr(csr); - ctx.set_gpr(rd, value); - log::debug!("Timer CSR read: csr={:#x} -> {:#x}", csr, value); - } else { - // csrwr / csrxchg – write guest value to host hardware timer. - let old_value = read_host_timer_csr(csr); - let new_value = ctx.x[rj]; - write_host_timer_csr(csr, new_value); - ctx.set_gpr(rd, old_value); - log::debug!( - "Timer CSR write: csr={:#x} <- {:#x} (old={:#x})", - csr, - new_value, - old_value - ); +fn read_guest_timer_csr(ctx: &LoongArchContextFrame, csr: usize) -> usize { + match csr { + CSR_TCFG => ctx.gcsr_tcfg, + CSR_TVAL => ctx.gcsr_tval, + CSR_TICLR => ctx.gcsr_ticlr, + _ => 0, + } +} - // When the guest clears the timer interrupt via TICLR, also clear the - // injected timer bit in the guest ESTAT so the guest doesn't re-take - // the interrupt on the next VM entry. - if csr == CSR_TICLR && (new_value & 0x1) != 0 { - ctx.gcsr_estat &= !TIMER_BIT; - } +fn guest_timer_periodic(ctx: &LoongArchContextFrame) -> bool { + ctx.gcsr_tcfg & CSR_TCFG_PERIODIC != 0 +} + +fn guest_timer_init_ticks(ctx: &LoongArchContextFrame) -> u64 { + (ctx.gcsr_tcfg & CSR_TCFG_INITVAL_MASK) as u64 +} + +fn cancel_guest_timer(guest_timer_token: &mut Option) { + if let Some(token) = guest_timer_token.take() { + host::cancel_timer(token); } } -/// Read a host hardware timer CSR via inline assembly. -fn read_host_timer_csr(csr: usize) -> usize { - let value: usize; - unsafe { - match csr { - CSR_TCFG => core::arch::asm!("csrrd {}, 0x41", out(reg) value), - CSR_TVAL => core::arch::asm!("csrrd {}, 0x42", out(reg) value), - CSR_TICLR => core::arch::asm!("csrrd {}, 0x44", out(reg) value), - _ => value = 0, - } +fn register_guest_timer( + ctx: &mut LoongArchContextFrame, + vm_id: VMId, + vcpu_id: VCpuId, + guest_timer_token: &mut Option, +) { + cancel_guest_timer(guest_timer_token); + + if ctx.gcsr_tcfg & CSR_TCFG_EN == 0 { + return; + } + + let init_ticks = guest_timer_init_ticks(ctx); + if init_ticks == 0 { + ctx.gcsr_tval = 0; + ctx.gcsr_estat |= TIMER_BIT; + return; } - value + + ctx.gcsr_tval = init_ticks as usize; + let delay_ns = host::ticks_to_nanos(init_ticks); + let deadline_ns = host::current_time_nanos().saturating_add(delay_ns); + let token = host::register_timer( + Duration::from_nanos(deadline_ns), + Box::new(move |_| host::inject_interrupt(vm_id, vcpu_id, INT_TIMER)), + ); + *guest_timer_token = Some(token); } -/// Write a host hardware timer CSR via inline assembly. -fn write_host_timer_csr(csr: usize, value: usize) { - unsafe { - match csr { - CSR_TCFG => core::arch::asm!("csrwr {}, 0x41", in(reg) value), - CSR_TVAL => core::arch::asm!("csrwr {}, 0x42", in(reg) value), - CSR_TICLR => core::arch::asm!("csrwr {}, 0x44", in(reg) value), - _ => {} +fn write_guest_timer_csr( + ctx: &mut LoongArchContextFrame, + csr: usize, + value: usize, + vm_id: VMId, + vcpu_id: VCpuId, + guest_timer_token: &mut Option, +) { + match csr { + CSR_TCFG => { + ctx.gcsr_tcfg = value; + register_guest_timer(ctx, vm_id, vcpu_id, guest_timer_token); + } + CSR_TVAL => { + ctx.gcsr_tval = value; + } + CSR_TICLR => { + ctx.gcsr_ticlr = value; + if value & CSR_TICLR_TI != 0 { + ctx.gcsr_estat &= !TIMER_BIT; + if guest_timer_periodic(ctx) { + register_guest_timer(ctx, vm_id, vcpu_id, guest_timer_token); + } else { + ctx.gcsr_tcfg &= !CSR_TCFG_EN; + cancel_guest_timer(guest_timer_token); + } + } } + _ => {} + } +} + +fn emulate_timer_csr( + ctx: &mut LoongArchContextFrame, + rd: usize, + rj: usize, + csr: usize, + vm_id: VMId, + vcpu_id: VCpuId, + guest_timer_token: &mut Option, +) { + let old_value = read_guest_timer_csr(ctx, csr); + let mut return_value = old_value; + + if rj != 0 { + let new_value = if rj == 1 { + ctx.x[rd] + } else { + let mask = ctx.x[rj]; + return_value &= mask; + (old_value & !mask) | (ctx.x[rd] & mask) + }; + write_guest_timer_csr(ctx, csr, new_value, vm_id, vcpu_id, guest_timer_token); + log::debug!( + "Timer CSR emulation: csr={:#x} <- {:#x} (old={:#x})", + csr, + new_value, + old_value + ); + } else { + log::debug!("Timer CSR emulation: csr={:#x} -> {:#x}", csr, old_value); } + + ctx.set_gpr(rd, return_value); } fn emulate_cacop(ctx: &mut LoongArchContextFrame, _ins: usize) -> AxVCpuExitReason { @@ -213,11 +437,16 @@ fn emulate_cacop(ctx: &mut LoongArchContextFrame, _ins: usize) -> AxVCpuExitReas fn emulate_idle(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { let level = extract_field(ins, 0, 15); log::debug!("LoongArch guest idle request: level={:#x}", level); + let pending_enabled = ctx.gcsr_estat & ctx.gcsr_ectl & LOCAL_INTERRUPT_MASK; + if ctx.gcsr_eentry != 0 + && ctx.gcsr_crmd & CSR_CRMD_IE != 0 + && let Some(vector) = decode_interrupt_vector(pending_enabled) + { + inject_guest_interrupt(ctx, vector); + return AxVCpuExitReason::Nothing; + } advance_guest_pc(ctx); - // Return Nothing instead of Halt so the guest busy-loops in its idle - // handler. A Halt exit would permanently block the vCPU task because - // there is no timer-based wakeup mechanism yet. - AxVCpuExitReason::Nothing + AxVCpuExitReason::Idle } fn emulate_iocsr(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { @@ -274,7 +503,12 @@ fn emulate_iocsr(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReaso AxVCpuExitReason::Nothing } -fn emulate_gspr(ctx: &mut LoongArchContextFrame) -> AxVCpuExitReason { +fn emulate_gspr( + ctx: &mut LoongArchContextFrame, + vm_id: VMId, + vcpu_id: VCpuId, + guest_timer_token: &mut Option, +) -> AxVCpuExitReason { let ins = get_badi(ctx) as u32 as usize; const OPCODE_CPUCFG: usize = 0b0000000000000000011011; const OPCODE_CPUCFG_LEN: usize = 22; @@ -302,7 +536,7 @@ fn emulate_gspr(ctx: &mut LoongArchContextFrame) -> AxVCpuExitReason { return emulate_idle(ctx, ins); } if matches(OPCODE_CSRX, OPCODE_CSRX_LEN) { - return emulate_csrx(ctx, ins); + return emulate_csrx(ctx, ins, vm_id, vcpu_id, guest_timer_token); } if matches(OPCODE_IOCSR, OPCODE_IOCSR_LEN) { return emulate_iocsr(ctx, ins); @@ -315,7 +549,12 @@ fn emulate_gspr(ctx: &mut LoongArchContextFrame) -> AxVCpuExitReason { ); } -pub fn handle_exception_sync(ctx: &mut LoongArchContextFrame) -> AxResult { +pub fn handle_exception_sync( + ctx: &mut LoongArchContextFrame, + vm_id: VMId, + vcpu_id: VCpuId, + guest_timer_token: &mut Option, +) -> AxResult { let ecode = get_exception_code(ctx); let esubcode = get_exception_subcode(ctx); @@ -333,6 +572,23 @@ pub fn handle_exception_sync(ctx: &mut LoongArchContextFrame) -> AxResult { let nr = ctx.get_a0() as u64; @@ -347,9 +603,13 @@ pub fn handle_exception_sync(ctx: &mut LoongArchContextFrame) -> AxResult Ok(emulate_gspr(ctx)), + ECODE_GSPR => Ok(emulate_gspr(ctx, vm_id, vcpu_id, guest_timer_token)), ECODE_PIL | ECODE_PIS | ECODE_PIF | ECODE_PME | ECODE_PNR | ECODE_PNX | ECODE_PPI => { let badv = get_badv(ctx); + if should_inject_guest_virtual_fault(ctx, badv, false) { + inject_guest_regular_exception(ctx, ecode, esubcode, badv); + return Ok(AxVCpuExitReason::Nothing); + } let mut access_flags = MappingFlags::empty(); if matches!(ecode, ECODE_PIS | ECODE_PME) { access_flags |= MappingFlags::WRITE; @@ -393,16 +653,10 @@ pub fn handle_exception_sync(ctx: &mut LoongArchContextFrame) -> AxResult AxResult AxResult AxResult PhysAddr; + + /// Read monotonic host time in nanoseconds. + fn current_time_nanos() -> u64; + + /// Convert LoongArch timer ticks to nanoseconds. + fn ticks_to_nanos(ticks: u64) -> u64; + + /// Register a guest timer callback at an absolute host deadline. + fn register_timer( + deadline: Duration, + callback: Box, + ) -> usize; + + /// Cancel a guest timer callback. + fn cancel_timer(token: usize); + + /// Queue an interrupt for a vCPU. + fn inject_interrupt(vm_id: usize, vcpu_id: usize, vector: usize); } #[cfg(target_arch = "loongarch64")] pub(crate) fn virt_to_phys(vaddr: VirtAddr) -> PhysAddr { ax_crate_interface::call_interface!(LoongArchVcpuHostIf::virt_to_phys(vaddr)) } + +#[cfg(target_arch = "loongarch64")] +pub(crate) fn current_time_nanos() -> u64 { + ax_crate_interface::call_interface!(LoongArchVcpuHostIf::current_time_nanos()) +} + +#[cfg(target_arch = "loongarch64")] +pub(crate) fn ticks_to_nanos(ticks: u64) -> u64 { + ax_crate_interface::call_interface!(LoongArchVcpuHostIf::ticks_to_nanos(ticks)) +} + +#[cfg(target_arch = "loongarch64")] +pub(crate) fn register_timer( + deadline: Duration, + callback: Box, +) -> usize { + ax_crate_interface::call_interface!(LoongArchVcpuHostIf::register_timer(deadline, callback)) +} + +#[cfg(target_arch = "loongarch64")] +pub(crate) fn cancel_timer(token: usize) { + ax_crate_interface::call_interface!(LoongArchVcpuHostIf::cancel_timer(token)) +} + +#[cfg(target_arch = "loongarch64")] +pub(crate) fn inject_interrupt(vm_id: usize, vcpu_id: usize, vector: usize) { + ax_crate_interface::call_interface!(LoongArchVcpuHostIf::inject_interrupt( + vm_id, vcpu_id, vector + )) +} diff --git a/virtualization/loongarch_vcpu/src/registers.rs b/virtualization/loongarch_vcpu/src/registers.rs index 5cd14a4a88..fccc39c8a8 100644 --- a/virtualization/loongarch_vcpu/src/registers.rs +++ b/virtualization/loongarch_vcpu/src/registers.rs @@ -6,10 +6,6 @@ pub const CSR_GSTAT: u16 = 0x50; pub const CSR_CRMD: u16 = 0x0; pub const CSR_PRMD: u16 = 0x1; pub const CSR_EENTRY: u16 = 0x0c; -pub const CSR_TLBIDX: u16 = 0x10; -pub const CSR_TLBEHI: u16 = 0x11; -pub const CSR_TLBELO0: u16 = 0x12; -pub const CSR_TLBELO1: u16 = 0x13; pub const CSR_ASID: u16 = 0x18; pub const CSR_GCTL: u16 = 0x51; pub const CSR_GTLBC: u16 = 0x15; @@ -20,10 +16,6 @@ pub const CSR_PWCL: u16 = 0x1c; pub const CSR_PWCH: u16 = 0x1d; pub const CSR_STLBPS: u16 = 0x1e; pub const CSR_TLBRENTRY: u16 = 0x88; -pub const CSR_TLBRELO0: u16 = 0x8c; -pub const CSR_TLBRELO1: u16 = 0x8d; -pub const CSR_TLBREHI: u16 = 0x8e; -pub const CSR_TLBRERA: u16 = 0x8a; pub const CSR_ECFG: u16 = 0x4; pub const CSR_KSAVE_KSP: u16 = 0x30; diff --git a/virtualization/loongarch_vcpu/src/vcpu.rs b/virtualization/loongarch_vcpu/src/vcpu.rs index 90382bd88c..4e19b9bd16 100644 --- a/virtualization/loongarch_vcpu/src/vcpu.rs +++ b/virtualization/loongarch_vcpu/src/vcpu.rs @@ -15,17 +15,18 @@ use crate::{ context_frame::LoongArchContextFrame, host, registers::{ - CSR_PGDH, CSR_PGDL, CSR_PWCH, CSR_PWCL, CSR_STLBPS, CSR_TLBRENTRY, INT_TIMER, csr_read, - csr_write, gcfg_set_gpm_num, gcfg_set_matc, gcfg_set_toci, gcfg_set_toe, gcfg_set_tohu, - gcfg_set_top, gcfg_set_topi, gcfg_set_toti, get_ecfg_vs, gintc_set_hwi_passthrough, - gstat_set_gid, gstat_set_pvm, gtlbc_set_tgid, gtlbc_set_use_tgid, set_ecfg_line_enabled, - set_ecfg_vs, + CSR_ASID, CSR_CRMD, CSR_KSAVE_KSP, CSR_PGDH, CSR_PGDL, CSR_PRMD, CSR_PWCH, CSR_PWCL, + CSR_STLBPS, CSR_TLBRENTRY, INT_HWI0, INT_HWI7, INT_IPI, INT_TIMER, csr_read, csr_write, + gcfg_set_gpm_num, gcfg_set_matc, gcfg_set_toci, gcfg_set_toe, gcfg_set_tohu, gcfg_set_top, + gcfg_set_topi, gcfg_set_toti, get_ecfg_vs, gintc_set_hwi_passthrough, gstat_set_gid, + gstat_set_pvm, gtlbc_set_tgid, gtlbc_set_use_tgid, set_ecfg_line_enabled, set_ecfg_vs, }, }; #[cfg(target_arch = "loongarch64")] unsafe extern "C" { fn _run_guest(ctx: *mut LoongArchContextFrame) -> !; + fn _guest_tlb_refill_vector(); static _exception_vectors: u8; } @@ -50,6 +51,7 @@ pub struct LoongArchVCpu { vm_id: VMId, vcpu_id: VCpuId, cpu_id: usize, + guest_timer_token: Option, } #[cfg(target_arch = "loongarch64")] @@ -72,18 +74,22 @@ static HOST_STAGE2_STLBPS: usize = 0; static HOST_STAGE2_TLBRENTRY: usize = 0; #[cfg(target_arch = "loongarch64")] #[ax_percpu::def_percpu] -static HOST_GUEST_EXIT_EENTRY: usize = 0; +static HOST_STAGE2_ASID: usize = 0; #[cfg(target_arch = "loongarch64")] #[ax_percpu::def_percpu] -static HOST_ECFG_VS: usize = 0; - -/// Host CSR number for TCFG (Timer Configuration). +static HOST_CRMD: usize = 0; #[cfg(target_arch = "loongarch64")] -const CSR_HOST_TCFG: u16 = 0x41; - -/// TCFG.EN bit: timer enable. +#[ax_percpu::def_percpu] +static HOST_PRMD: usize = 0; #[cfg(target_arch = "loongarch64")] -const TCFG_EN: usize = 0x1; +#[ax_percpu::def_percpu] +static HOST_KSAVE_KSP: usize = 0; +#[cfg(target_arch = "loongarch64")] +#[ax_percpu::def_percpu] +static HOST_GUEST_EXIT_EENTRY: usize = 0; +#[cfg(target_arch = "loongarch64")] +#[ax_percpu::def_percpu] +static HOST_ECFG_VS: usize = 0; #[cfg(target_arch = "loongarch64")] const GUEST_RESET_CRMD_DIRECT: usize = 1 << 3; @@ -100,6 +106,12 @@ const GUEST_BOOT_VSEG: usize = 0x9000; #[cfg(target_arch = "loongarch64")] const GUEST_BOOT_DMW: usize = (GUEST_BOOT_VSEG << GUEST_DMW_DA_BITS) | GUEST_DMW_PLV0 | GUEST_DMW_MAT_CC; +#[cfg(target_arch = "loongarch64")] +const STAGE2_ASID: usize = 1; +#[cfg(target_arch = "loongarch64")] +const CSR_CRMD_IE: usize = 1 << 2; +#[cfg(target_arch = "loongarch64")] +const LOCAL_INTERRUPT_MASK: usize = (1 << (INT_IPI + 1)) - 1; #[derive(Clone, Debug, Default)] pub struct LoongArchVCpuCreateConfig { @@ -140,11 +152,13 @@ impl AxArchVCpu for LoongArchVCpu { vm_id: _vm_id, vcpu_id: _vcpu_id, cpu_id: config.cpu_id, + guest_timer_token: None, }) } fn set_entry(&mut self, entry: GuestPhysAddr) -> AxResult { self.ctx.sepc = entry.as_usize(); + self.ctx.gcsr_era = entry.as_usize(); Ok(()) } @@ -161,13 +175,9 @@ impl AxArchVCpu for LoongArchVCpu { fn run(&mut self) -> AxResult { #[cfg(target_arch = "loongarch64")] { - // Before entering the guest, program the host hardware timer with the - // guest's requested TCFG value. In LVZ the guest's timer CSR writes go - // to GCSR TCFG transparently (no GSPR trap), so the only place we can - // observe the guest's timer configuration is in ctx.gcsr_tcfg, which is - // updated by SAVE_GUEST_REGS on each VM exit. - self.sync_guest_timer_to_host(); - + unsafe { + self.enable_guest_mode(); + } log::debug!("LoongArch guest entry context:\n{}", self.ctx); let exit_reason = unsafe { save_host_sp(); @@ -216,7 +226,13 @@ impl AxArchVCpu for LoongArchVCpu { } fn inject_interrupt(&mut self, vector: usize) -> AxResult { - crate::registers::inject_interrupt(vector); + if (INT_HWI0..=INT_HWI7).contains(&vector) { + crate::registers::inject_interrupt(vector); + } else if vector <= INT_IPI { + self.ctx.gcsr_estat |= 1usize << vector; + } else { + log::warn!("Ignoring unsupported LoongArch interrupt vector {vector}"); + } Ok(()) } @@ -226,8 +242,44 @@ impl AxArchVCpu for LoongArchVCpu { } impl LoongArchVCpu { + #[cfg(target_arch = "loongarch64")] + pub fn has_enabled_pending_interrupt(&self) -> bool { + self.ctx.gcsr_eentry != 0 + && self.ctx.gcsr_crmd & CSR_CRMD_IE != 0 + && self.ctx.gcsr_estat & self.ctx.gcsr_ectl & LOCAL_INTERRUPT_MASK != 0 + } + + #[cfg(target_arch = "loongarch64")] + pub fn idle_wait_timeout(&self) -> core::time::Duration { + const TIMER_ENABLE: usize = 1 << 0; + const TIMER_INIT_MASK: usize = !0x3; + const MIN_WAIT: core::time::Duration = core::time::Duration::from_micros(50); + const MAX_WAIT: core::time::Duration = core::time::Duration::from_millis(10); + + if self.ctx.gcsr_ectl & (1usize << INT_TIMER) == 0 || self.ctx.gcsr_tcfg & TIMER_ENABLE == 0 + { + return MAX_WAIT; + } + + let ticks = if self.ctx.gcsr_tval == 0 { + self.ctx.gcsr_tcfg & TIMER_INIT_MASK + } else { + self.ctx.gcsr_tval + }; + if ticks == 0 { + return MIN_WAIT; + } + + let nanos = host::ticks_to_nanos(ticks as u64); + core::time::Duration::from_nanos(nanos).clamp(MIN_WAIT, MAX_WAIT) + } + fn init_hv(&mut self, config: LoongArchVCpuSetupConfig) { self.init_vm_context(config); + #[cfg(target_arch = "loongarch64")] + unsafe { + gintc_set_hwi_passthrough(0xff); + } } fn init_vm_context(&mut self, config: LoongArchVCpuSetupConfig) { @@ -241,38 +293,7 @@ impl LoongArchVCpu { self.ctx.gcsr_asid = self.vcpu_id; self.ctx.gcsr_cpuid = self.cpu_id; - if config.passthrough_timer { - self.ctx.gcsr_tcfg = 0x1; - } - } - - /// Program the host hardware timer to match the guest's requested timer - /// configuration. In LVZ, guest timer CSR writes (TCFG/TVAL/TICLR) are - /// transparent (GCSR-swappable) and do NOT trap, so the guest's virtual - /// timer state is only observable via `ctx.gcsr_tcfg` which is updated by - /// SAVE_GUEST_REGS on each VM exit. - /// - /// By programming the host timer to match, the hardware timer fires at the - /// guest's requested time, causing an IRQ VM exit. The IRQ handler then - /// injects the timer interrupt into the guest via `gcsr_estat`. - /// - /// **Limitation**: This direct passthrough is only correct in the 1:1 vCPU - /// model where each vCPU exclusively owns a physical CPU. In SMP or - /// shared-CPU scenarios, a software-emulated timer (maintaining per-guest - /// virtual TCFG/TVAL) will be needed. - #[cfg(target_arch = "loongarch64")] - fn sync_guest_timer_to_host(&self) { - let guest_tcfg = self.ctx.gcsr_tcfg; - // Only program the host timer when the guest has set a non-zero - // init value. With init_val=0 the timer fires immediately on - // every VM entry, preventing the guest from making progress. - let init_val = guest_tcfg >> 2; - if guest_tcfg & TCFG_EN != 0 && init_val != 0 { - log::debug!("Sync guest timer to host: gcsr_tcfg={:#x}", guest_tcfg); - unsafe { - csr_write::(guest_tcfg); - } - } + let _ = config.passthrough_timer; } /// Set guest architectural boot state: CRMD (DA mode), PRMD (PIE), EUEN, DMW0-3. @@ -312,6 +333,9 @@ impl LoongArchVCpu { /// Save host translation CSRs to per-CPU storage before switching to stage2. #[cfg(target_arch = "loongarch64")] unsafe fn save_host_translation_state(&self) { + HOST_CRMD.write_current_raw(csr_read::()); + HOST_PRMD.write_current_raw(csr_read::()); + HOST_KSAVE_KSP.write_current_raw(csr_read::()); HOST_GUEST_EXIT_EENTRY.write_current_raw(csr_read::<{ crate::registers::CSR_EENTRY }>()); HOST_ECFG_VS.write_current_raw(get_ecfg_vs()); HOST_STAGE2_PGDL.write_current_raw(csr_read::()); @@ -320,6 +344,7 @@ impl LoongArchVCpu { HOST_STAGE2_PWCH.write_current_raw(csr_read::()); HOST_STAGE2_STLBPS.write_current_raw(csr_read::()); HOST_STAGE2_TLBRENTRY.write_current_raw(csr_read::()); + HOST_STAGE2_ASID.write_current_raw(csr_read::()); } /// Program stage2 page-walk CSRs from the VM's stage2 root. @@ -331,16 +356,14 @@ impl LoongArchVCpu { csr_write::(12); csr_write::(root); csr_write::(root); + csr_write::(STAGE2_ASID); } /// Install host exit vector table (CSR.EENTRY) and TLB refill handler /// (CSR.TLBRENTRY), then flush stale TLB entries. #[cfg(target_arch = "loongarch64")] unsafe fn install_host_exit_vectors(&self) { - unsafe extern "C" { - fn handle_tlb_refill(); - } - let tlbrentry_vaddr = VirtAddr::from_ptr_of(handle_tlb_refill as *const ()); + let tlbrentry_vaddr = VirtAddr::from_ptr_of(_guest_tlb_refill_vector as *const ()); let tlbrentry_paddr = host::virt_to_phys(tlbrentry_vaddr).as_usize(); let guest_exit_eentry = core::ptr::addr_of!(_exception_vectors) as usize; @@ -352,7 +375,7 @@ impl LoongArchVCpu { /// Enable LVZ guest-mode hardware: GID, TGID, PGM, GCFG, GINTC, PRMD.PIE. #[cfg(target_arch = "loongarch64")] unsafe fn enable_guest_mode(&self) { - let guest_id = self.vm_id + 1; + let guest_id = 0; gstat_set_gid(guest_id); gstat_set_pvm(true); gtlbc_set_use_tgid(true); @@ -365,8 +388,6 @@ impl LoongArchVCpu { gcfg_set_tohu(false); gcfg_set_toci(0x2); gcfg_set_gpm_num(0); - gintc_set_hwi_passthrough(0xff); - set_ecfg_line_enabled(INT_TIMER, false); prmd::set_pie(true); } @@ -381,6 +402,10 @@ impl LoongArchVCpu { csr_write::(HOST_STAGE2_PWCH.read_current_raw()); csr_write::(HOST_STAGE2_STLBPS.read_current_raw()); csr_write::(HOST_STAGE2_TLBRENTRY.read_current_raw()); + csr_write::(HOST_STAGE2_ASID.read_current_raw()); + csr_write::(HOST_KSAVE_KSP.read_current_raw()); + csr_write::(HOST_PRMD.read_current_raw()); + csr_write::(HOST_CRMD.read_current_raw()); core::arch::asm!("invtlb 0x0, $r0, $r0"); } @@ -422,7 +447,12 @@ impl LoongArchVCpu { #[cfg(target_arch = "loongarch64")] fn vmexit_handler(&mut self, exit_reason: TrapKind) -> AxResult { match exit_reason { - TrapKind::Synchronous => handle_exception_sync(&mut self.ctx), + TrapKind::Synchronous => handle_exception_sync( + &mut self.ctx, + self.vm_id, + self.vcpu_id, + &mut self.guest_timer_token, + ), TrapKind::Irq => handle_exception_irq(&mut self.ctx), } } From ad345c0bc8a2ae74e015b9ef81d58a0a5c09c60b Mon Sep 17 00:00:00 2001 From: szy Date: Tue, 9 Jun 2026 11:15:56 +0800 Subject: [PATCH 10/50] fix(axvisor): support LoongArch Linux rootfs boot with standard images --- Cargo.lock | 1 + os/axvisor/Cargo.toml | 1 + .../configs/board/qemu-loongarch64-linux.toml | 3 + .../qemu/loongarch64/linux-rootfs-smp1.toml | 13 +- os/axvisor/doc/qemu-quickstart.md | 6 +- os/axvisor/scripts/qemu-lvz.version | 1 - os/axvisor/scripts/quick-start.sh | 65 +-- os/axvisor/scripts/setup_qemu_lvz.sh | 23 +- os/axvisor/src/config.rs | 30 +- os/axvisor/src/fdt/create.rs | 80 +++- os/axvisor/src/fdt/mod.rs | 6 +- os/axvisor/src/fdt/parser.rs | 49 +- os/axvisor/src/images/loongarch_image.rs | 80 ++++ os/axvisor/src/images/loongarch_linux.rs | 18 +- os/axvisor/src/images/loongarch_zboot.rs | 111 +++++ os/axvisor/src/images/mod.rs | 48 +- os/axvisor/src/manager.rs | 10 +- scripts/axbuild/src/axvisor/rootfs.rs | 70 ++- scripts/axbuild/src/context/mod.rs | 36 +- scripts/axbuild/src/context/tests/arceos.rs | 40 +- scripts/axbuild/src/rootfs/inject.rs | 41 ++ virtualization/axvm/src/host/arceos.rs | 5 +- virtualization/axvm/src/lib.rs | 5 +- virtualization/axvm/src/vm.rs | 2 + .../loongarch_vcpu/src/exception.rs | 435 +++++++++++++++--- virtualization/loongarch_vcpu/src/vcpu.rs | 10 + 26 files changed, 986 insertions(+), 203 deletions(-) create mode 100644 os/axvisor/src/images/loongarch_image.rs create mode 100644 os/axvisor/src/images/loongarch_zboot.rs diff --git a/Cargo.lock b/Cargo.lock index 2bf3488575..a822563323 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1541,6 +1541,7 @@ dependencies = [ "prettyplease", "proc-macro2", "quote", + "ruzstd", "spin 0.12.0", "syn 2.0.117", "tokio", diff --git a/os/axvisor/Cargo.toml b/os/axvisor/Cargo.toml index bd56011b3d..e6c6862f7f 100644 --- a/os/axvisor/Cargo.toml +++ b/os/axvisor/Cargo.toml @@ -62,6 +62,7 @@ log = "0.4" byte-unit = { version = "5", default-features = false, features = ["byte"] } fdt-parser = "0.4" hashbrown = "0.14" +ruzstd = { version = "0.8", default-features = false, features = ["hash"] } # System dependent modules provided by ArceOS. ax-std = { workspace = true, features = ["ext-ld", "paging", "irq", "multitask", "task-ext", "smp", "hv"] } diff --git a/os/axvisor/configs/board/qemu-loongarch64-linux.toml b/os/axvisor/configs/board/qemu-loongarch64-linux.toml index 2a6f04e109..06e413dfe1 100644 --- a/os/axvisor/configs/board/qemu-loongarch64-linux.toml +++ b/os/axvisor/configs/board/qemu-loongarch64-linux.toml @@ -1,7 +1,10 @@ env = {AX_IP = "10.0.2.15", AX_GW = "10.0.2.2"} features = [ "ax-hal/loongarch64-qemu-virt", + "ax-driver/virtio-blk", + "ax-driver/plat-static", "ept-level-4", + "fs", ] log = "Info" max_cpu_num = 1 diff --git a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml index 4c8a3019bd..d8c3746f7a 100644 --- a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml +++ b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml @@ -21,24 +21,23 @@ entry_point = 0x0020_0000 # The location of image: "memory" | "fs". image_location = "fs" # The file path of the kernel image. -kernel_path = "/guest/linux/qemu-loongarch64" +kernel_path = "/guest/linux/linux-qemu" # The ELF LOAD paddr is used by the LoongArch loader; this is a fallback for flat images. kernel_load_addr = 0x0020_0000 # The file path of the device tree blob (DTB). -dtb_path = "/guest/linux/linux-rootfs-smp1.dtb" +# When omitted, AxVisor generates a guest DTB from the host FDT. +# dtb_path = "/guest/linux/linux-rootfs-smp1.dtb" # The load address of the device tree blob (DTB). dtb_load_addr = 0x0010_0000 # Kernel command line. Rootfs mode intentionally uses virtio-blk /dev/vda. -cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw init=/init console=ttyS0 earlycon=uart,mmio,0x1fe001e0 keep_bootcon nokaslr loglevel=8 ignore_loglevel pci=nomsi swiotlb=1024 initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" +cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw init=/bin/sh console=ttyS0 earlycon=uart,mmio,0x1fe001e0 nokaslr loglevel=8 ignore_loglevel swiotlb=1024 initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" # Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`). # For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`, 2 means `MAP_RESERVED`. memory_regions = [ [0x0008_0000, 0x0018_0000, 0x7, 2], # Low bootinfo/DTB RAM 512K-2M MAP_RESERVED - [0x0020_0000, 0x03e0_0000, 0x7, 2], # System RAM 2-64M MAP_RESERVED - [0x0400_0000, 0x0200_0000, 0x7, 2], # System RAM 64-96M MAP_RESERVED - [0x0600_0000, 0x0200_0000, 0x7, 2], # System RAM 96-128M MAP_RESERVED - [0x0800_0000, 0x0200_0000, 0x7, 2], # System RAM 128-160M MAP_RESERVED + [0x0020_0000, 0x0fe0_0000, 0x7, 2], # Low System RAM 2-256M MAP_RESERVED + [0x8000_0000, 0x2000_0000, 0x7, 0], # High System RAM kept mapped but hidden from Linux memory map ] # diff --git a/os/axvisor/doc/qemu-quickstart.md b/os/axvisor/doc/qemu-quickstart.md index 4b06525cc7..1a8741a621 100644 --- a/os/axvisor/doc/qemu-quickstart.md +++ b/os/axvisor/doc/qemu-quickstart.md @@ -171,13 +171,13 @@ Success indicator: `Hello, world!` appears in the output. ### AxVisor Shell (LoongArch64, requires QEMU-LVZ) -Install the pinned QEMU-LVZ once: +Install QEMU-LVZ once. The script reuses the local cache if it exists; otherwise it fetches the latest QEMU-LVZ source and builds it: ```bash ./scripts/setup_qemu_lvz.sh ``` -After that, quick-start auto-detects the cached binary: +After that, quick-start and `cargo xtask axvisor qemu` auto-detect the cached binary: ```bash ./scripts/quick-start.sh qemu-loongarch64 start @@ -193,7 +193,7 @@ For the Linux guest flow with a virtio-blk rootfs, run: ./scripts/quick-start.sh qemu-loongarch64 run --linux ``` -The tracked VM template for this flow is `configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml`; quick-start copies it to `tmp/configs/linux-rootfs-smp1.toml` and patches the temporary image paths. +The tracked VM template for this flow is `configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml`; quick-start copies it to `tmp/configs/linux-rootfs-smp1.toml`. The managed rootfs path is `tmp/axbuild/rootfs/rootfs-loongarch64-alpine.img`: if it is already present it is reused, otherwise `cargo xtask` downloads the latest matching archive from `rcore-os/tgosimages`. > **Note**: Stock `qemu-system-loongarch64` usually does not expose LoongArch virtualization extensions. Run `./scripts/setup_qemu_lvz.sh` once, or set `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` to a validated virtualization-capable binary. diff --git a/os/axvisor/scripts/qemu-lvz.version b/os/axvisor/scripts/qemu-lvz.version index f10b8b0b56..f9b23d5cf6 100644 --- a/os/axvisor/scripts/qemu-lvz.version +++ b/os/axvisor/scripts/qemu-lvz.version @@ -1,4 +1,3 @@ QEMU_LVZ_REPO=https://github.com/Hengyu-Yu/QEMU-LVZ.git -QEMU_LVZ_COMMIT=360a7753d3df618b3cceddc82dc8e1ff363ff846 QEMU_LVZ_VERSION=9.0.50 QEMU_LVZ_TARGET_LIST=loongarch64-softmmu diff --git a/os/axvisor/scripts/quick-start.sh b/os/axvisor/scripts/quick-start.sh index 52addb94cb..18166856d7 100755 --- a/os/axvisor/scripts/quick-start.sh +++ b/os/axvisor/scripts/quick-start.sh @@ -26,20 +26,14 @@ error() { echo -e "${RED}[ERROR]${NC} $1" } -qemu_lvz_version_value() { - local key="$1" - local version_file="scripts/qemu-lvz.version" - if [[ -f "$version_file" ]]; then - sed -n "s/^${key}=//p" "$version_file" | tail -n 1 - fi -} - qemu_lvz_cache_binary() { - local commit - commit="$(qemu_lvz_version_value QEMU_LVZ_COMMIT)" - if [[ -n "$commit" ]]; then - printf '%s\n' "${AXVISOR_QEMU_LVZ_CACHE:-$HOME/.cache/axvisor/qemu-lvz}/$commit/bin/qemu-system-loongarch64" + local cache_root="${AXVISOR_QEMU_LVZ_CACHE:-$HOME/.cache/axvisor/qemu-lvz}" + local latest="$cache_root/latest/bin/qemu-system-loongarch64" + if [[ -x "$latest" ]]; then + printf '%s\n' "$latest" + return 0 fi + find "$cache_root" -mindepth 3 -maxdepth 3 -path '*/bin/qemu-system-loongarch64' -type f -executable 2>/dev/null | sort | head -n 1 } # Execute command and display it @@ -317,7 +311,7 @@ run_qemu_riscv64_arceos() { setup_qemu_loongarch64() { info "=== QEMU LoongArch64 Preparation ===" - run_cmd mkdir -p tmp/{configs,images/qemu_loongarch64_linux} + run_cmd mkdir -p tmp/configs info "Preparing board config file..." run_cmd cp configs/board/qemu-loongarch64.toml tmp/configs/ @@ -325,30 +319,6 @@ setup_qemu_loongarch64() { info "Preparing Linux guest rootfs config file..." run_cmd cp configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml tmp/configs/ - run_cmd cp configs/vms/qemu/loongarch64/linux-rootfs-smp1.dts tmp/configs/ - - local guest_dir="${AXVISOR_LOONGARCH64_GUEST_DIR:-$(cd ../../.. && pwd)/axvisor-guest/IMAGES/qemu/loongarch64/linux}" - if [ -f "$guest_dir/qemu-loongarch64" ]; then - info "Using LoongArch Linux guest artifacts from: $guest_dir" - run_cmd cp "$guest_dir/qemu-loongarch64" tmp/images/qemu_loongarch64_linux/ - if [ -f "$guest_dir/rootfs.img" ]; then - run_cmd cp "$guest_dir/rootfs.img" tmp/images/qemu_loongarch64_linux/ - fi - else - warn "LoongArch Linux guest artifacts not found in: $guest_dir" - warn "Build them first in axvisor-guest, or set AXVISOR_LOONGARCH64_GUEST_DIR." - fi - - if ! command -v dtc &> /dev/null; then - error "dtc is required to build linux-rootfs-smp1.dtb" - exit 1 - fi - run_cmd dtc -I dts -O dtb -o tmp/configs/linux-rootfs-smp1.dtb tmp/configs/linux-rootfs-smp1.dts - run_cmd cp tmp/configs/linux-rootfs-smp1.dtb tmp/images/qemu_loongarch64_linux/ - - run_cmd sed -i 's|^image_location = "fs"|image_location = "memory"|g' tmp/configs/linux-rootfs-smp1.toml - run_cmd sed -i 's|^kernel_path = .*|kernel_path = "../images/qemu_loongarch64_linux/qemu-loongarch64"|g' tmp/configs/linux-rootfs-smp1.toml - run_cmd sed -i 's|^dtb_path = .*|dtb_path = "linux-rootfs-smp1.dtb"|g' tmp/configs/linux-rootfs-smp1.toml info "Preparing QEMU config file..." run_cmd cp configs/qemu/qemu-loongarch64.toml tmp/configs/qemu-loongarch64-runtime.toml @@ -359,7 +329,7 @@ setup_qemu_loongarch64() { if [[ -n "${AXBUILD_QEMU_SYSTEM_LOONGARCH64:-}" ]]; then info "Using explicit LoongArch QEMU override: ${AXBUILD_QEMU_SYSTEM_LOONGARCH64}" elif [[ -n "$cached_qemu" && -x "$cached_qemu" ]]; then - info "Detected pinned QEMU-LVZ cache at $cached_qemu" + info "Detected cached QEMU-LVZ at $cached_qemu" elif command -v qemu-system-loongarch64 &> /dev/null; then warn "Using qemu-system-loongarch64 from PATH. Stock QEMU usually lacks LoongArch virtualization extensions; prefer QEMU-LVZ." else @@ -423,25 +393,13 @@ ensure_loongarch64_host_rootfs() { ensure_loongarch64_guest_rootfs() { local workspace_root="$1" local rootfs="$workspace_root/tmp/axbuild/rootfs/rootfs-loongarch64-alpine.img" - local source_rootfs="${AXVISOR_LOONGARCH64_ROOTFS:-$(pwd)/tmp/images/qemu_loongarch64_linux/rootfs.img}" - - run_cmd mkdir -p "$(dirname "$rootfs")" - if [[ -f "$source_rootfs" ]]; then - info "Using LoongArch Linux guest rootfs image: $source_rootfs" - if [[ "$(realpath -m "$source_rootfs")" != "$(realpath -m "$rootfs")" ]]; then - run_cmd cp "$source_rootfs" "$rootfs" - fi + if [[ -f "$rootfs" ]]; then + info "Using cached LoongArch managed rootfs: $rootfs" return 0 fi - error "LoongArch Linux rootfs image not found." - echo "Expected one of:" - echo " $source_rootfs" - echo " AXVISOR_LOONGARCH64_ROOTFS=/path/to/rootfs.img" - echo "" - echo "Build or provide rootfs.img in AXVISOR_LOONGARCH64_GUEST_DIR before using --linux." - exit 1 + info "LoongArch managed rootfs is missing; cargo xtask will download the latest tgosimages rootfs." } run_qemu_loongarch64_linux() { @@ -452,7 +410,6 @@ run_qemu_loongarch64_linux() { workspace_root="$(cd ../.. && pwd)" ensure_loongarch64_guest_rootfs "$workspace_root" - run_cmd sed -i 's|virtio-blk-pci,drive=disk0|virtio-blk-pci,drive=disk0,disable-modern=on|g' tmp/configs/qemu-loongarch64-runtime.toml run_axvisor_qemu_with_loongarch64_qemu \ --config "$(pwd)/tmp/configs/qemu-loongarch64-linux.toml" \ diff --git a/os/axvisor/scripts/setup_qemu_lvz.sh b/os/axvisor/scripts/setup_qemu_lvz.sh index a3d4f991b3..59f6a70152 100755 --- a/os/axvisor/scripts/setup_qemu_lvz.sh +++ b/os/axvisor/scripts/setup_qemu_lvz.sh @@ -1,6 +1,6 @@ #!/bin/bash # -# Build and install the pinned QEMU-LVZ used by LoongArch64 AxVisor runs. +# Build and install QEMU-LVZ used by LoongArch64 AxVisor runs. set -euo pipefail @@ -16,12 +16,12 @@ fi source "$VERSION_FILE" : "${QEMU_LVZ_REPO:?missing QEMU_LVZ_REPO in $VERSION_FILE}" -: "${QEMU_LVZ_COMMIT:?missing QEMU_LVZ_COMMIT in $VERSION_FILE}" : "${QEMU_LVZ_TARGET_LIST:?missing QEMU_LVZ_TARGET_LIST in $VERSION_FILE}" CACHE_ROOT="${AXVISOR_QEMU_LVZ_CACHE:-$HOME/.cache/axvisor/qemu-lvz}" -SRC_DIR="$CACHE_ROOT/src/$QEMU_LVZ_COMMIT" -INSTALL_DIR="$CACHE_ROOT/$QEMU_LVZ_COMMIT" +VERSION_KEY="${QEMU_LVZ_COMMIT:-latest}" +SRC_DIR="$CACHE_ROOT/src/$VERSION_KEY" +INSTALL_DIR="$CACHE_ROOT/$VERSION_KEY" QEMU_BIN="$INSTALL_DIR/bin/qemu-system-loongarch64" PYTHON_VENV="$CACHE_ROOT/python-venv" @@ -32,7 +32,7 @@ case "${1:-}" in cat <&2 @@ -113,12 +113,17 @@ else mkdir -p "$CACHE_ROOT/src" if [[ ! -d "$SRC_DIR/.git" ]]; then - info "Cloning QEMU-LVZ $QEMU_LVZ_COMMIT" + info "Cloning QEMU-LVZ $VERSION_KEY" git_run clone "$QEMU_LVZ_REPO" "$SRC_DIR" fi - git_run -C "$SRC_DIR" fetch --depth 1 origin "$QEMU_LVZ_COMMIT" - git_run -C "$SRC_DIR" checkout --detach "$QEMU_LVZ_COMMIT" + if [[ -n "${QEMU_LVZ_COMMIT:-}" ]]; then + git_run -C "$SRC_DIR" fetch --depth 1 origin "$QEMU_LVZ_COMMIT" + git_run -C "$SRC_DIR" checkout --detach "$QEMU_LVZ_COMMIT" + else + git_run -C "$SRC_DIR" fetch --depth 1 origin + git_run -C "$SRC_DIR" checkout --detach FETCH_HEAD + fi mkdir -p "$INSTALL_DIR" diff --git a/os/axvisor/src/config.rs b/os/axvisor/src/config.rs index c5088a46f3..83098819c4 100644 --- a/os/axvisor/src/config.rs +++ b/os/axvisor/src/config.rs @@ -14,7 +14,10 @@ use alloc::{format, sync::Arc}; use core::alloc::Layout; -#[cfg(all(feature = "fs", target_arch = "x86_64"))] +#[cfg(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") +))] use core::sync::atomic::{AtomicBool, Ordering}; use ax_errno::{AxResult, ax_err_type}; @@ -39,7 +42,10 @@ use crate::images::ImageLoader; #[cfg(target_arch = "x86_64")] const DEFAULT_X86_BIOS_LOAD_GPA: usize = 0x8000; -#[cfg(all(feature = "fs", target_arch = "x86_64"))] +#[cfg(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") +))] static HOST_FILESYSTEM_RELEASE_REQUIRED: AtomicBool = AtomicBool::new(false); #[allow(dead_code)] @@ -133,7 +139,10 @@ pub fn init_guest_vm(raw_cfg: &str) -> AxResult { let mut vm_create_config = AxVMCrateConfig::from_toml(raw_cfg) .map_err(|e| ax_err_type!(InvalidData, format!("Failed to resolve VM config: {e:?}")))?; - #[cfg(all(feature = "fs", target_arch = "x86_64"))] + #[cfg(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") + ))] let release_host_filesystem = vm_config_needs_host_filesystem_release(&vm_create_config); if let Some(linux) = super::images::get_image_header(&vm_create_config) { @@ -200,7 +209,10 @@ pub fn init_guest_vm(raw_cfg: &str) -> AxResult { )); } - #[cfg(all(feature = "fs", target_arch = "x86_64"))] + #[cfg(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") + ))] if release_host_filesystem { HOST_FILESYSTEM_RELEASE_REQUIRED.store(true, Ordering::Release); } @@ -263,14 +275,20 @@ fn configured_bios_load_gpa(cfg: &AxVMCrateConfig) -> Option { None } -#[cfg(all(feature = "fs", target_arch = "x86_64"))] +#[cfg(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") +))] fn vm_config_needs_host_filesystem_release(config: &AxVMCrateConfig) -> bool { config.kernel.image_location.as_deref() == Some("fs") && (!config.devices.passthrough_devices.is_empty() || !config.devices.passthrough_addresses.is_empty()) } -#[cfg(all(feature = "fs", target_arch = "x86_64"))] +#[cfg(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") +))] pub fn host_filesystem_release_required() -> bool { HOST_FILESYSTEM_RELEASE_REQUIRED.load(Ordering::Acquire) } diff --git a/os/axvisor/src/fdt/create.rs b/os/axvisor/src/fdt/create.rs index aa67892d5c..4f913618c1 100644 --- a/os/axvisor/src/fdt/create.rs +++ b/os/axvisor/src/fdt/create.rs @@ -17,22 +17,48 @@ use alloc::{ string::{String, ToString}, vec::Vec, }; -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64" +))] use core::ptr::NonNull; use ax_errno::{AxError, AxResult, ax_err_type}; -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64" +))] use ax_memory_addr::MemoryAddr; use fdt_parser::{Fdt, Node}; use super::vm_fdt::{FdtWriter, FdtWriterNode}; -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64" +))] use crate::images::load_vm_image_from_memory; -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64" +))] use axvm::AxVMRef; -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64", test))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64", + test +))] use axvm::GuestPhysAddr; -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64", test))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64", + test +))] use axvm::VMMemoryRegion; use axvmconfig::AxVMCrateConfig; @@ -120,6 +146,10 @@ pub fn crate_guest_fdt( previous_node_level = node.level; + #[cfg(target_arch = "loongarch64")] + let add_pci_interrupt_cells = + is_loongarch_pci_host_node(node) && node.find_property("#interrupt-cells").is_none(); + // Copy all properties of the node for prop in node.propertys() { if node_path.starts_with("/cpus") && should_skip_guest_cpu_prop(prop.name) { @@ -129,6 +159,13 @@ pub fn crate_guest_fdt( .property(prop.name, prop.raw_value()) .map_err(fdt_write_err)?; } + + #[cfg(target_arch = "loongarch64")] + if add_pci_interrupt_cells { + fdt_writer + .property_u32("#interrupt-cells", 1) + .map_err(fdt_write_err)?; + } } // End all unclosed nodes @@ -145,6 +182,14 @@ pub fn crate_guest_fdt( fdt_writer.finish().map_err(fdt_write_err) } +#[cfg(target_arch = "loongarch64")] +fn is_loongarch_pci_host_node(node: &Node<'_>) -> bool { + node.name().starts_with("pcie@") + && node + .compatibles() + .any(|compatible| compatible == "pci-host-ecam-generic") +} + /// Node processing action enumeration enum NodeAction { /// Skip node, not included in guest FDT @@ -291,7 +336,12 @@ fn need_cpu_node(phys_cpu_ids: &[usize], node: &Node, node_path: &str) -> bool { } /// Add memory node -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64", test))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64", + test +))] fn add_memory_node( new_memory: &[VMMemoryRegion], crate_config: &AxVMCrateConfig, @@ -325,12 +375,16 @@ fn add_memory_node( ) { let gpa = mem.gpa.as_usize() as u64; let size = mem.size() as u64; + #[cfg(target_arch = "loongarch64")] + if gpa >= 0x1000_0000 { + continue; + } new_value.push((gpa >> 32) as u32); new_value.push((gpa & 0xFFFFFFFF) as u32); new_value.push((size >> 32) as u32); new_value.push((size & 0xFFFFFFFF) as u32); } - info!("Adding memory node with value: {new_value:x?}"); + debug!("Adding memory node with value: {new_value:x?}"); new_fdt .property_array_u32("reg", new_value.as_ref()) .map_err(fdt_write_err)?; @@ -529,7 +583,7 @@ pub fn update_fdt( Ok(()) } -#[cfg(target_arch = "riscv64")] +#[cfg(any(target_arch = "riscv64", target_arch = "loongarch64"))] pub fn update_fdt( fdt_src: NonNull, dtb_size: usize, @@ -653,7 +707,11 @@ mod tests { } } -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64" +))] pub(crate) fn calculate_dtb_load_addr(vm: AxVMRef, fdt_size: usize) -> AxResult { const MB: usize = 1024 * 1024; @@ -685,7 +743,7 @@ pub(crate) fn calculate_dtb_load_addr(vm: AxVMRef, fdt_size: usize) -> AxResult< Ok(dtb_addr) } -#[cfg(target_arch = "riscv64")] +#[cfg(any(target_arch = "riscv64", target_arch = "loongarch64"))] pub(crate) fn patch_guest_fdt_for_runtime( fdt: &Fdt, memory_regions: &[VMMemoryRegion], diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index 403da8c0df..0a77a5ef25 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -29,7 +29,11 @@ use ax_errno::{AxResult, ax_err_type}; use ax_kspin::SpinNoIrq as Mutex; use ax_lazyinit::LazyInit; // pub use print::print_fdt; -#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +#[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64" +))] pub use create::update_fdt; pub use device::build_all_node_paths; use fdt_parser::Fdt; diff --git a/os/axvisor/src/fdt/parser.rs b/os/axvisor/src/fdt/parser.rs index dbde9b495c..7dd69be0a2 100644 --- a/os/axvisor/src/fdt/parser.rs +++ b/os/axvisor/src/fdt/parser.rs @@ -484,6 +484,13 @@ fn parse_loongarch_pci_interrupt_map( let child_address_cells = node_address_cells(node); let child_interrupt_cells = node_interrupt_cells(node); let child_cells = child_address_cells + child_interrupt_cells; + if child_cells == 0 { + warn!( + "LoongArch PCI interrupt-map in node {} has invalid child cell count", + node.name() + ); + return; + } let mut index = 0usize; while index + child_cells < interrupt_map.len() { @@ -496,7 +503,8 @@ fn parse_loongarch_pci_interrupt_map( ); break; }; - let parent_interrupt_cells = node_interrupt_cells(parent_node); + let parent_interrupt_cells = + pci_interrupt_map_parent_cells(&interrupt_map, child_cells, parent_node); let entry_cells = child_cells + 1 + parent_interrupt_cells; if index + entry_cells > interrupt_map.len() { warn!( @@ -520,6 +528,26 @@ fn parse_loongarch_pci_interrupt_map( } } +#[cfg(target_arch = "loongarch64")] +fn pci_interrupt_map_parent_cells( + interrupt_map: &[u32], + child_cells: usize, + parent_node: &Node<'_>, +) -> usize { + let default_parent_cells = node_interrupt_cells(parent_node); + let default_entry_cells = child_cells + 1 + default_parent_cells; + let one_cell_entry_cells = child_cells + 2; + + if default_parent_cells > 1 + && interrupt_map.len() % default_entry_cells != 0 + && interrupt_map.len() % one_cell_entry_cells == 0 + { + 1 + } else { + default_parent_cells + } +} + #[cfg(target_arch = "loongarch64")] pub fn parse_loongarch_guest_irq_routes(vm_cfg: &AxVMConfig, dtb: &[u8]) -> AxResult { let fdt = Fdt::from_bytes(dtb).map_err(|e| { @@ -532,6 +560,7 @@ pub fn parse_loongarch_guest_irq_routes(vm_cfg: &AxVMConfig, dtb: &[u8]) -> AxRe let mut phandle_nodes = BTreeMap::new(); let mut eiointc = None; let mut pch_pic = None; + let mut pch_msi_nodes = Vec::new(); for node in &all_nodes { if let Some(phandle) = node_phandle(node) { @@ -543,6 +572,9 @@ pub fn parse_loongarch_guest_irq_routes(vm_cfg: &AxVMConfig, dtb: &[u8]) -> AxRe if has_compatible_part(node, "pch-pic") { pch_pic = Some(node.clone()); } + if has_compatible(node, "loongson,pch-msi-1.0") { + pch_msi_nodes.push(node.clone()); + } } let Some(eiointc) = eiointc else { @@ -616,9 +648,22 @@ pub fn parse_loongarch_guest_irq_routes(vm_cfg: &AxVMConfig, dtb: &[u8]) -> AxRe ); } + for node in pch_msi_nodes { + let base_vec = property_u32(&node, "loongson,msi-base-vec").unwrap_or(0) as usize; + let num_vecs = property_u32(&node, "loongson,msi-num-vecs").unwrap_or(0) as usize; + for physical_irq in base_vec..base_vec.saturating_add(num_vecs) { + add_loongarch_irq_route(&mut routes, physical_irq, eiointc_guest_vector, node.name()); + } + } + let routes = routes.into_iter().collect::>(); info!( - "VM[{}] LoongArch guest IRQ routes parsed from DTB: {:?}", + "VM[{}] parsed {} LoongArch guest IRQ route(s) from DTB", + vm_cfg.id(), + routes.len() + ); + debug!( + "VM[{}] LoongArch guest IRQ routes: {:?}", vm_cfg.id(), routes ); diff --git a/os/axvisor/src/images/loongarch_image.rs b/os/axvisor/src/images/loongarch_image.rs new file mode 100644 index 0000000000..6f935b3a7c --- /dev/null +++ b/os/axvisor/src/images/loongarch_image.rs @@ -0,0 +1,80 @@ +use ax_errno::{AxResult, ax_err_type}; +use axvm::{AxVMRef, GuestPhysAddr}; + +use crate::images::load_vm_image_from_memory; + +const LOONGARCH_IMAGE_MAGIC: &[u8; 8] = b"MZ\0\0\0\0\0\0"; +const HEADER_SIZE: usize = 0x40; +const KERNEL_ENTRY_OFFSET: usize = 0x8; +const IMAGE_SIZE_OFFSET: usize = 0x10; +const LOAD_OFFSET_OFFSET: usize = 0x18; +const PE_POINTER_OFFSET: usize = 0x3c; +const PE_HEADER_OFFSET: u32 = 0x40; + +#[derive(Clone, Copy, Debug)] +pub struct ImageInfo { + pub entry: GuestPhysAddr, +} + +pub fn try_load(image: &[u8], vm: AxVMRef) -> AxResult> { + let Some(header) = Header::parse(image)? else { + return Ok(None); + }; + + let image = &image[..header.image_size]; + load_vm_image_from_memory(image, GuestPhysAddr::from(header.load_offset), vm)?; + Ok(Some(ImageInfo { + entry: GuestPhysAddr::from(header.entry), + })) +} + +struct Header { + entry: usize, + image_size: usize, + load_offset: usize, +} + +impl Header { + fn parse(image: &[u8]) -> AxResult> { + if image.len() < HEADER_SIZE + || &image[..LOONGARCH_IMAGE_MAGIC.len()] != LOONGARCH_IMAGE_MAGIC + { + return Ok(None); + } + if read_u32(image, PE_POINTER_OFFSET)? != PE_HEADER_OFFSET { + return Ok(None); + } + + let image_size = read_u64(image, IMAGE_SIZE_OFFSET)? as usize; + if image_size == 0 || image.len() < image_size { + return Err(ax_err_type!( + InvalidInput, + format!( + "LoongArch Linux Image size is invalid: image={:#x}, header={:#x}", + image.len(), + image_size + ) + )); + } + + Ok(Some(Self { + entry: read_u64(image, KERNEL_ENTRY_OFFSET)? as usize, + image_size, + load_offset: read_u64(image, LOAD_OFFSET_OFFSET)? as usize, + })) + } +} + +fn read_u32(image: &[u8], offset: usize) -> AxResult { + let bytes = image + .get(offset..offset + 4) + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch Image u32 read out of range"))?; + Ok(u32::from_le_bytes(bytes.try_into().unwrap())) +} + +fn read_u64(image: &[u8], offset: usize) -> AxResult { + let bytes = image + .get(offset..offset + 8) + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch Image u64 read out of range"))?; + Ok(u64::from_le_bytes(bytes.try_into().unwrap())) +} diff --git a/os/axvisor/src/images/loongarch_linux.rs b/os/axvisor/src/images/loongarch_linux.rs index a155b467eb..dbc8fecb77 100644 --- a/os/axvisor/src/images/loongarch_linux.rs +++ b/os/axvisor/src/images/loongarch_linux.rs @@ -23,6 +23,7 @@ const EFI_MEMORY_DESCRIPTOR_VERSION: u32 = 1; const EFI_LOADER_DATA: u32 = 2; const EFI_CONVENTIONAL_MEMORY: u32 = 7; const EFI_MEMORY_DESC_SIZE: usize = 40; +const DMA_IDENTITY_RAM_END: usize = 0x1000_0000; pub fn setup_bootinfo(vm: AxVMRef, crate_config: &AxVMCrateConfig) -> AxResult { let bootargs = crate_config @@ -61,7 +62,11 @@ pub fn setup_bootinfo(vm: AxVMRef, crate_config: &AxVMCrateConfig) -> AxResult { let vm_regions = vm.memory_regions(); let regions = efi_memory_regions(&vm_regions, crate_config); - let map_size = regions.len() * EFI_MEMORY_DESC_SIZE; + let efi_region_count = regions + .iter() + .filter(|region| region.gpa.as_usize() < DMA_IDENTITY_RAM_END) + .count(); + let map_size = efi_region_count * EFI_MEMORY_DESC_SIZE; let mut boot_memmap = Vec::new(); write_u64(&mut boot_memmap, map_size as u64); write_u64(&mut boot_memmap, EFI_MEMORY_DESC_SIZE as u64); @@ -71,10 +76,15 @@ pub fn setup_bootinfo(vm: AxVMRef, crate_config: &AxVMCrateConfig) -> AxResult { write_u64(&mut boot_memmap, map_size as u64); for region in ®ions { let gpa = region.gpa.as_usize() as u64; + if region.gpa.as_usize() >= DMA_IDENTITY_RAM_END { + continue; + } let pages = (region.size() as u64).div_ceil(4096); - let mem_type = match region.gpa.as_usize() { - BOOTINFO_GPA | DTB_GPA => EFI_LOADER_DATA, - _ => EFI_CONVENTIONAL_MEMORY, + let mem_type = if region.gpa.as_usize() == BOOTINFO_GPA || region.gpa.as_usize() == DTB_GPA + { + EFI_LOADER_DATA + } else { + EFI_CONVENTIONAL_MEMORY }; write_efi_memory_desc(&mut boot_memmap, gpa, pages, mem_type); } diff --git a/os/axvisor/src/images/loongarch_zboot.rs b/os/axvisor/src/images/loongarch_zboot.rs new file mode 100644 index 0000000000..4351123b13 --- /dev/null +++ b/os/axvisor/src/images/loongarch_zboot.rs @@ -0,0 +1,111 @@ +use alloc::vec::Vec; + +use ax_errno::{AxResult, ax_err_type}; +use ruzstd::{decoding::StreamingDecoder, io::Read}; + +const ZBOOT_MAGIC: &[u8; 8] = b"MZ\0\0zimg"; +const HEADER_SIZE: usize = 0x40; +const PAYLOAD_INFO_OFFSET: usize = 0x8; +const PAYLOAD_OFFSET_BITS: u64 = 32; +const PAYLOAD_OFFSET_MASK: u64 = (1 << PAYLOAD_OFFSET_BITS) - 1; +const FORMAT_OFFSET: usize = 0x18; +const FORMAT_ZSTD: &[u8; 4] = b"zstd"; + +#[derive(Debug)] +pub struct ZbootImage { + pub payload: Vec, +} + +pub fn decompress(image: &[u8]) -> AxResult> { + let Some(header) = Header::parse(image)? else { + return Ok(None); + }; + + let compressed = image + .get(header.payload_offset..header.payload_end()) + .ok_or_else(|| { + ax_err_type!( + InvalidInput, + format!( + "LoongArch zboot payload range [{:#x}, {:#x}) exceeds image size {:#x}", + header.payload_offset, + header.payload_end(), + image.len() + ) + ) + })?; + + let mut decoder = StreamingDecoder::new(compressed).map_err(|err| { + ax_err_type!( + InvalidInput, + format!("failed to initialize LoongArch zboot zstd decoder: {err:?}") + ) + })?; + let mut payload = Vec::with_capacity(header.payload_size); + decoder.read_to_end(&mut payload).map_err(|err| { + ax_err_type!( + InvalidInput, + format!("failed to decompress LoongArch zboot zstd payload: {err}") + ) + })?; + + info!( + "Decompressed LoongArch zboot image: payload_offset={:#x}, compressed={:#x}, decompressed={:#x}", + header.payload_offset, + header.payload_size, + payload.len() + ); + + Ok(Some(ZbootImage { payload })) +} + +struct Header { + payload_offset: usize, + payload_size: usize, +} + +impl Header { + fn parse(image: &[u8]) -> AxResult> { + if image.len() < HEADER_SIZE || &image[..ZBOOT_MAGIC.len()] != ZBOOT_MAGIC { + return Ok(None); + } + if image + .get(FORMAT_OFFSET..FORMAT_OFFSET + FORMAT_ZSTD.len()) + .is_none_or(|format| format != FORMAT_ZSTD) + { + return Err(ax_err_type!( + InvalidInput, + "unsupported LoongArch zboot compression format" + )); + } + + let payload_info = read_u64(image, PAYLOAD_INFO_OFFSET)?; + let payload_offset = (payload_info & PAYLOAD_OFFSET_MASK) as usize; + let payload_size = (payload_info >> PAYLOAD_OFFSET_BITS) as usize; + if payload_offset < HEADER_SIZE || payload_size == 0 { + return Err(ax_err_type!( + InvalidInput, + format!( + "invalid LoongArch zboot payload metadata: offset={:#x}, size={:#x}", + payload_offset, payload_size + ) + )); + } + + Ok(Some(Self { + payload_offset, + payload_size, + })) + } + + fn payload_end(&self) -> usize { + self.payload_offset.saturating_add(self.payload_size) + } +} + +fn read_u64(image: &[u8], offset: usize) -> AxResult { + let bytes = image + .get(offset..offset + 8) + .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch zboot u64 read out of range"))?; + Ok(u64::from_le_bytes(bytes.try_into().unwrap())) +} diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index 02c118c201..704b1f69a1 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -28,7 +28,11 @@ mod linux; #[cfg(target_arch = "loongarch64")] mod loongarch_elf; #[cfg(target_arch = "loongarch64")] +mod loongarch_image; +#[cfg(target_arch = "loongarch64")] mod loongarch_linux; +#[cfg(target_arch = "loongarch64")] +mod loongarch_zboot; #[cfg(target_arch = "x86_64")] mod x86; #[cfg(target_arch = "x86_64")] @@ -175,7 +179,11 @@ impl ImageLoader { if let Some(dtb_arc) = get_vm_dtb_arc(&vm_config) { let _dtb_slice: &[u8] = &dtb_arc; - #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] + #[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64" + ))] { if let Some(dtb_src) = core::ptr::NonNull::new(_dtb_slice.as_ptr() as *mut u8) { crate::fdt::update_fdt( @@ -188,13 +196,6 @@ impl ImageLoader { return ax_err!(InvalidData, "Guest DTB pointer is null"); } } - #[cfg(target_arch = "loongarch64")] - { - let dtb_load_gpa = self - .dtb_load_gpa - .ok_or_else(|| ax_err_type!(NotFound, "DTB load address is missing"))?; - load_vm_image_from_memory(_dtb_slice, dtb_load_gpa, self.vm.clone())?; - } } else { #[cfg(any(target_arch = "loongarch64", target_arch = "riscv64"))] if let Some(buffer) = vm_imags.dtb { @@ -320,6 +321,11 @@ impl ImageLoader { } fn load_kernel_from_memory(&self, kernel: &[u8]) -> AxResult { + #[cfg(target_arch = "loongarch64")] + if let Some(image) = loongarch_zboot::decompress(kernel)? { + return self.load_kernel_from_memory(&image.payload); + } + #[cfg(target_arch = "loongarch64")] if let Some(info) = loongarch_elf::try_load(kernel, self.vm.clone())? { self.vm.with_config(|config| { @@ -333,6 +339,19 @@ impl ImageLoader { return Ok(()); } + #[cfg(target_arch = "loongarch64")] + if let Some(info) = loongarch_image::try_load(kernel, self.vm.clone())? { + self.vm.with_config(|config| { + config.cpu_config.bsp_entry = info.entry; + config.cpu_config.ap_entry = info.entry; + }); + info!( + "LoongArch Linux Image entry set to {:#x}", + info.entry.as_usize() + ); + return Ok(()); + } + load_vm_image_from_memory(kernel, self.kernel_load_gpa, self.vm.clone()) } @@ -758,7 +777,11 @@ pub mod fs { let vm_config = crate::config::build_axvm_config(&loader.config); if let Some(dtb_arc) = get_vm_dtb_arc(&vm_config) { let _dtb_slice: &[u8] = &dtb_arc; - #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] + #[cfg(any( + target_arch = "aarch64", + target_arch = "riscv64", + target_arch = "loongarch64" + ))] { let dtb_src = core::ptr::NonNull::new(_dtb_slice.as_ptr() as *mut u8) .ok_or_else(|| ax_err_type!(InvalidData, "Guest DTB pointer is null"))?; @@ -769,13 +792,6 @@ pub mod fs { &loader.config, )?; } - #[cfg(target_arch = "loongarch64")] - { - let dtb_load_gpa = loader - .dtb_load_gpa - .ok_or_else(|| ax_err_type!(NotFound, "DTB load address is missing"))?; - load_vm_image_from_memory(_dtb_slice, dtb_load_gpa, loader.vm.clone())?; - } } #[cfg(target_arch = "loongarch64")] diff --git a/os/axvisor/src/manager.rs b/os/axvisor/src/manager.rs index fdd5493d1d..a1bb6dd5d8 100644 --- a/os/axvisor/src/manager.rs +++ b/os/axvisor/src/manager.rs @@ -88,7 +88,10 @@ impl AxvmManager { axvm::get_vm_by_id(vm_id) } - #[cfg(all(feature = "fs", target_arch = "x86_64"))] + #[cfg(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") + ))] fn release_host_filesystem_for_guest_passthrough(&self) { if !crate::config::host_filesystem_release_required() { return; @@ -100,7 +103,10 @@ impl AxvmManager { info!("Host filesystem cleanly unmounted before guest passthrough devices start"); } - #[cfg(not(all(feature = "fs", target_arch = "x86_64")))] + #[cfg(not(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") + )))] fn release_host_filesystem_for_guest_passthrough(&self) {} /// Read VM config files from an Axvisor-owned directory. diff --git a/scripts/axbuild/src/axvisor/rootfs.rs b/scripts/axbuild/src/axvisor/rootfs.rs index 14143686b7..29ce1ac620 100644 --- a/scripts/axbuild/src/axvisor/rootfs.rs +++ b/scripts/axbuild/src/axvisor/rootfs.rs @@ -11,21 +11,20 @@ use std::{ path::{Path, PathBuf}, }; -use anyhow::anyhow; +use anyhow::{Context, anyhow}; use ostool::{build::config::Cargo, run::qemu::QemuConfig}; use super::{Axvisor, build}; use crate::{context::ResolvedAxvisorRequest, rootfs, test::qemu as qemu_test}; pub(super) async fn qemu(axvisor: &mut Axvisor, args: super::ArgsQemu) -> anyhow::Result<()> { - let request = axvisor.prepare_request( + let mut request = axvisor.prepare_request( (&args.build).into(), args.qemu_config, None, crate::context::SnapshotPersistence::Store, )?; axvisor.app.set_debug_mode(request.debug)?; - let cargo = build::load_cargo_config(&request)?; let explicit_rootfs = args .rootfs .map(|rootfs| { @@ -42,6 +41,12 @@ pub(super) async fn qemu(axvisor: &mut Axvisor, args: super::ArgsQemu) -> anyhow explicit_rootfs.as_deref(), ) .await?; + prepare_loongarch_linux_memory_vmconfigs( + &mut request, + axvisor.app.workspace_root(), + explicit_rootfs.as_deref(), + )?; + let cargo = build::load_cargo_config(&request)?; let qemu = load_patched_qemu_config(axvisor, &request, &cargo, explicit_rootfs.as_deref()).await?; axvisor @@ -50,6 +55,65 @@ pub(super) async fn qemu(axvisor: &mut Axvisor, args: super::ArgsQemu) -> anyhow .await } +fn prepare_loongarch_linux_memory_vmconfigs( + request: &mut ResolvedAxvisorRequest, + workspace_root: &Path, + explicit_rootfs: Option<&Path>, +) -> anyhow::Result<()> { + if request.arch != "loongarch64" || request.vmconfigs.is_empty() { + return Ok(()); + } + + let rootfs_path = qemu_rootfs_path(request, workspace_root, explicit_rootfs)?; + let out_dir = workspace_root.join("tmp/axbuild/axvisor/loongarch64"); + let kernel_path = out_dir.join("linux-qemu"); + let mut prepared_vmconfigs = Vec::with_capacity(request.vmconfigs.len()); + + for vmconfig in &request.vmconfigs { + let content = fs::read_to_string(vmconfig) + .map_err(|e| anyhow!("failed to read vm config {}: {e}", vmconfig.display()))?; + let value: toml::Value = toml::from_str(&content) + .map_err(|e| anyhow!("failed to parse vm config {}: {e}", vmconfig.display()))?; + let guest_kernel = value + .get("kernel") + .and_then(|kernel| kernel.get("kernel_path")) + .and_then(|path| path.as_str()); + + if guest_kernel != Some("/guest/linux/linux-qemu") { + prepared_vmconfigs.push(vmconfig.clone()); + continue; + } + + rootfs::inject::extract_file(&rootfs_path, "/guest/linux/linux-qemu", &kernel_path) + .with_context(|| { + format!( + "failed to prepare LoongArch Linux kernel from {}", + rootfs_path.display() + ) + })?; + + let prepared_vmconfig = out_dir.join( + vmconfig + .file_name() + .unwrap_or_else(|| std::ffi::OsStr::new("linux-rootfs-smp1.toml")), + ); + fs::create_dir_all(&out_dir) + .with_context(|| format!("failed to create {}", out_dir.display()))?; + let patched = content + .replace("image_location = \"fs\"", "image_location = \"memory\"") + .replace( + "kernel_path = \"/guest/linux/linux-qemu\"", + &format!("kernel_path = \"{}\"", kernel_path.display()), + ); + fs::write(&prepared_vmconfig, patched) + .with_context(|| format!("failed to write {}", prepared_vmconfig.display()))?; + prepared_vmconfigs.push(prepared_vmconfig); + } + + request.vmconfigs = prepared_vmconfigs; + Ok(()) +} + pub(super) async fn load_patched_qemu_config( axvisor: &mut Axvisor, request: &ResolvedAxvisorRequest, diff --git a/scripts/axbuild/src/context/mod.rs b/scripts/axbuild/src/context/mod.rs index 108b462143..aa87d7a7b0 100644 --- a/scripts/axbuild/src/context/mod.rs +++ b/scripts/axbuild/src/context/mod.rs @@ -556,20 +556,42 @@ fn find_loongarch_qemu_dir(workspace_root: &Path) -> Option { fn loongarch_qemu_dir_candidates(workspace_root: &Path) -> Vec { let mut candidates = Vec::new(); - if let Some(commit) = pinned_qemu_lvz_commit(workspace_root) { - let cache_root = env::var_os("AXVISOR_QEMU_LVZ_CACHE") - .map(PathBuf::from) - .or_else(|| { - env::var_os("HOME").map(|home| PathBuf::from(home).join(".cache/axvisor/qemu-lvz")) - }); - if let Some(cache_root) = cache_root { + let cache_root = env::var_os("AXVISOR_QEMU_LVZ_CACHE") + .map(PathBuf::from) + .or_else(|| { + env::var_os("HOME").map(|home| PathBuf::from(home).join(".cache/axvisor/qemu-lvz")) + }); + if let Some(cache_root) = cache_root { + candidates.push(cache_root.join("latest").join("bin")); + if let Some(commit) = pinned_qemu_lvz_commit(workspace_root) { candidates.push(cache_root.join(commit).join("bin")); } + candidates.extend(cached_loongarch_qemu_dirs(&cache_root)); } candidates } +fn cached_loongarch_qemu_dirs(cache_root: &Path) -> Vec { + let Ok(entries) = std::fs::read_dir(cache_root) else { + return Vec::new(); + }; + + let mut dirs: Vec<_> = entries + .filter_map(Result::ok) + .filter_map(|entry| { + let path = entry.path(); + if path.file_name().is_some_and(|name| name == "src") { + return None; + } + let bin_dir = path.join("bin"); + is_loongarch_qemu_dir(&bin_dir).then_some(bin_dir) + }) + .collect(); + dirs.sort(); + dirs +} + fn pinned_qemu_lvz_commit(workspace_root: &Path) -> Option { let version_file = workspace_root.join("os/axvisor/scripts/qemu-lvz.version"); let content = std::fs::read_to_string(version_file).ok()?; diff --git a/scripts/axbuild/src/context/tests/arceos.rs b/scripts/axbuild/src/context/tests/arceos.rs index 7c2ea6d91c..76e0fd31eb 100644 --- a/scripts/axbuild/src/context/tests/arceos.rs +++ b/scripts/axbuild/src/context/tests/arceos.rs @@ -216,23 +216,16 @@ fn find_loongarch_qemu_dir_prefers_explicit_env_override() { } #[test] -fn find_loongarch_qemu_dir_uses_pinned_cache() { +fn find_loongarch_qemu_dir_uses_latest_cache() { let _lock = ENV_LOCK.lock().unwrap(); let home = tempdir().unwrap(); let workspace = tempdir().unwrap(); - let commit = "1234567890abcdef"; let qemu_dir = home .path() .join(".cache/axvisor/qemu-lvz") - .join(commit) + .join("latest") .join("bin"); - fs::create_dir_all(workspace.path().join("os/axvisor/scripts")).unwrap(); - fs::write( - workspace.path().join("os/axvisor/scripts/qemu-lvz.version"), - format!("QEMU_LVZ_COMMIT={commit}\n"), - ) - .unwrap(); fs::create_dir_all(&qemu_dir).unwrap(); fs::write(qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); @@ -244,19 +237,30 @@ fn find_loongarch_qemu_dir_uses_pinned_cache() { } #[test] -fn find_loongarch_qemu_dir_honors_custom_pinned_cache_root() { +fn find_loongarch_qemu_dir_honors_custom_latest_cache_root() { let _lock = ENV_LOCK.lock().unwrap(); let cache = tempdir().unwrap(); let workspace = tempdir().unwrap(); - let commit = "abcdef1234567890"; - let qemu_dir = cache.path().join(commit).join("bin"); + let qemu_dir = cache.path().join("latest").join("bin"); + + fs::create_dir_all(&qemu_dir).unwrap(); + fs::write(qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); + + let _qemu_dir = TempEnvVar::unset("AXBUILD_QEMU_DIR"); + let _qemu_bin = TempEnvVar::unset("AXBUILD_QEMU_SYSTEM_LOONGARCH64"); + let _home = TempEnvVar::unset("HOME"); + let _cache = TempEnvVar::set("AXVISOR_QEMU_LVZ_CACHE", cache.path()); + + assert_eq!(find_loongarch_qemu_dir(workspace.path()), Some(qemu_dir)); +} + +#[test] +fn find_loongarch_qemu_dir_uses_existing_cached_version() { + let _lock = ENV_LOCK.lock().unwrap(); + let cache = tempdir().unwrap(); + let workspace = tempdir().unwrap(); + let qemu_dir = cache.path().join("abcdef1234567890").join("bin"); - fs::create_dir_all(workspace.path().join("os/axvisor/scripts")).unwrap(); - fs::write( - workspace.path().join("os/axvisor/scripts/qemu-lvz.version"), - format!("QEMU_LVZ_COMMIT={commit}\n"), - ) - .unwrap(); fs::create_dir_all(&qemu_dir).unwrap(); fs::write(qemu_dir.join("qemu-system-loongarch64"), "").unwrap(); diff --git a/scripts/axbuild/src/rootfs/inject.rs b/scripts/axbuild/src/rootfs/inject.rs index 6cffb3c47f..72d739728c 100644 --- a/scripts/axbuild/src/rootfs/inject.rs +++ b/scripts/axbuild/src/rootfs/inject.rs @@ -55,6 +55,47 @@ pub(crate) fn read_text_file( .with_context(|| format!("{}:{guest_path} is not valid UTF-8", rootfs_img.display())) } +/// Extracts one regular file from a rootfs image with `debugfs`. +pub(crate) fn extract_file( + rootfs_img: &Path, + guest_path: &str, + output_path: &Path, +) -> anyhow::Result<()> { + ensure!( + guest_path.starts_with('/'), + "guest path must be absolute: `{guest_path}`" + ); + + if let Some(parent) = output_path.parent() { + fs::create_dir_all(parent) + .with_context(|| format!("failed to create {}", parent.display()))?; + } + if output_path.exists() { + fs::remove_file(output_path) + .with_context(|| format!("failed to remove {}", output_path.display()))?; + } + + let output = Command::new("debugfs") + .arg("-R") + .arg(format!("dump {guest_path} {}", output_path.display())) + .arg(rootfs_img) + .output() + .with_context(|| format!("failed to spawn debugfs for {}", rootfs_img.display()))?; + if !output.status.success() { + bail!( + "failed to extract {guest_path} from {}: {}", + rootfs_img.display(), + String::from_utf8_lossy(&output.stderr).trim() + ); + } + ensure!( + output_path.exists(), + "debugfs did not create {} while extracting {guest_path}", + output_path.display() + ); + Ok(()) +} + /// Replaces one regular file inside a rootfs image with a host file. pub(crate) fn replace_file( rootfs_img: &Path, diff --git a/virtualization/axvm/src/host/arceos.rs b/virtualization/axvm/src/host/arceos.rs index b66d622626..8b56192b0b 100644 --- a/virtualization/axvm/src/host/arceos.rs +++ b/virtualization/axvm/src/host/arceos.rs @@ -223,7 +223,10 @@ pub(crate) fn phys_to_virt(paddr: ax_memory_addr::PhysAddr) -> ax_memory_addr::V modules::ax_hal::mem::phys_to_virt(paddr) } -#[cfg(all(any(feature = "fs", feature = "host-fs"), target_arch = "x86_64"))] +#[cfg(all( + any(feature = "fs", feature = "host-fs"), + any(target_arch = "x86_64", target_arch = "loongarch64") +))] pub(crate) fn shutdown_host_filesystems() -> AxResult { modules::ax_fs_ng::shutdown_filesystems() } diff --git a/virtualization/axvm/src/lib.rs b/virtualization/axvm/src/lib.rs index 37b65f7b0f..61a5868c45 100644 --- a/virtualization/axvm/src/lib.rs +++ b/virtualization/axvm/src/lib.rs @@ -90,7 +90,10 @@ pub fn host_phys_to_virt(paddr: ax_memory_addr::PhysAddr) -> ax_memory_addr::Vir } /// Shut down ArceOS filesystems so guest passthrough can take ownership. -#[cfg(all(any(feature = "fs", feature = "host-fs"), target_arch = "x86_64"))] +#[cfg(all( + any(feature = "fs", feature = "host-fs"), + any(target_arch = "x86_64", target_arch = "loongarch64") +))] pub fn shutdown_host_filesystems() -> ax_errno::AxResult { host::arceos::shutdown_host_filesystems() } diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index 03f5ee7dff..4c4fc0e106 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -426,6 +426,8 @@ impl AxVM { crate::vcpu::AxVCpuSetupConfig { passthrough_interrupt: passthrough, passthrough_timer: passthrough, + boot_args: inner_mut.config.cpu_config.boot_args, + boot_stack_top: inner_mut.config.cpu_config.boot_stack_top, } }; #[cfg(not(any( diff --git a/virtualization/loongarch_vcpu/src/exception.rs b/virtualization/loongarch_vcpu/src/exception.rs index 368bd33f10..e46a782e64 100644 --- a/virtualization/loongarch_vcpu/src/exception.rs +++ b/virtualization/loongarch_vcpu/src/exception.rs @@ -1,5 +1,8 @@ use alloc::boxed::Box; -use core::time::Duration; +use core::{ + sync::atomic::{AtomicUsize, Ordering}, + time::Duration, +}; use ax_errno::AxResult; use axvcpu::{AxVCpuExitReason, GuestPhysAddr, MappingFlags, VCpuId, VMId}; @@ -27,6 +30,47 @@ const INT_IPI: usize = 12; const TIMER_BIT: usize = 1 << INT_TIMER; const IPI_BIT: usize = 1 << INT_IPI; const HWI_MASK: usize = ((1 << (INT_HWI7 + 1)) - 1) & !((1 << INT_HWI0) - 1); +const CPUCFG2_CRYPTO: usize = 1 << 9; +const CSR_CRMD: usize = 0x0; +const CSR_PRMD: usize = 0x1; +const CSR_EUEN: usize = 0x2; +const CSR_MISC: usize = 0x3; +const CSR_ECFG: usize = 0x4; +const CSR_ESTAT: usize = 0x5; +const CSR_ERA: usize = 0x6; +const CSR_BADV: usize = 0x7; +const CSR_BADI: usize = 0x8; +const CSR_EENTRY: usize = 0xc; +const CSR_TLBIDX: usize = 0x10; +const CSR_TLBEHI: usize = 0x11; +const CSR_TLBELO0: usize = 0x12; +const CSR_TLBELO1: usize = 0x13; +const CSR_ASID: usize = 0x18; +const CSR_PGDL: usize = 0x19; +const CSR_PGDH: usize = 0x1a; +const CSR_PGD: usize = 0x1b; +const CSR_PWCL: usize = 0x1c; +const CSR_PWCH: usize = 0x1d; +const CSR_STLBPS: usize = 0x1e; +const CSR_RAVCFG: usize = 0x1f; +const CSR_CPUID: usize = 0x20; +const CSR_PRCFG1: usize = 0x21; +const CSR_PRCFG2: usize = 0x22; +const CSR_PRCFG3: usize = 0x23; +const CSR_TID: usize = 0x40; +const CSR_LLBCTL: usize = 0x60; +const CSR_TLBRENTRY: usize = 0x88; +const CSR_TLBRBADV: usize = 0x89; +const CSR_TLBRERA: usize = 0x8a; +const CSR_TLBRSAVE: usize = 0x8b; +const CSR_TLBRELO0: usize = 0x8c; +const CSR_TLBRELO1: usize = 0x8d; +const CSR_TLBREHI: usize = 0x8e; +const CSR_TLBRPRMD: usize = 0x8f; +const CSR_DMW0: usize = 0x180; +const CSR_DMW1: usize = 0x181; +const CSR_DMW2: usize = 0x182; +const CSR_DMW3: usize = 0x183; const CSR_TICLR_TI: usize = 0x1; const CSR_TCFG_EN: usize = 1 << 0; const CSR_TCFG_PERIODIC: usize = 1 << 1; @@ -43,9 +87,29 @@ const CSR_TLBREHI_PS_MASK: usize = 0x3f; const CSR_TLBREHI_VPPN_MASK: usize = 0x0000_ffff_ffff_e000; const DEFAULT_TLB_PAGE_SHIFT: usize = 12; const GUEST_RAM_START: usize = 0x0008_0000; +const GUEST_HIGH_RAM_START: usize = 0x8000_0000; +const GUEST_HIGH_RAM_END: usize = 0xb000_0000; const QEMU_VIRT_MMIO_START: usize = 0x1000_0000; const QEMU_VIRT_MMIO_END: usize = 0x8000_0000; const GUEST_RAM_END: usize = QEMU_VIRT_MMIO_START; +const EIOINTC_ISR_BASE: usize = 0x1800; +const EIOINTC_ISR_REG_COUNT: usize = 4; +const EIOINTC_ISR_END: usize = EIOINTC_ISR_BASE + EIOINTC_ISR_REG_COUNT * 8; +const MAX_IOCSR_VMS: usize = 16; +const MAX_IOCSR_CPUS: usize = 16; +const LOONGARCH_IOCSR_IPI_STATUS: usize = 0x1000; +const LOONGARCH_IOCSR_IPI_EN: usize = 0x1004; +const LOONGARCH_IOCSR_IPI_SET: usize = 0x1008; +const LOONGARCH_IOCSR_IPI_CLEAR: usize = 0x100c; +const LOONGARCH_IOCSR_IPI_SEND: usize = 0x1040; +const IOCSR_SEND_CPU_SHIFT: usize = 16; +const IOCSR_SEND_CPU_MASK: usize = 0x3ff; +const IOCSR_IPI_ACTION_MASK: usize = 0x1f; + +static IOCSR_IPI_STATUS_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS]; +static IOCSR_IPI_ENABLE_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS]; #[repr(u8)] #[derive(Debug, Clone, Copy, PartialEq, Eq)] @@ -118,9 +182,94 @@ fn is_guest_direct_mapped_va(addr: usize) -> bool { fn is_known_guest_physical_addr(addr: usize) -> bool { (GUEST_RAM_START..GUEST_RAM_END).contains(&addr) + || (GUEST_HIGH_RAM_START..GUEST_HIGH_RAM_END).contains(&addr) || (QEMU_VIRT_MMIO_START..QEMU_VIRT_MMIO_END).contains(&addr) } +fn is_eiointc_isr_addr(addr: usize) -> bool { + (EIOINTC_ISR_BASE..EIOINTC_ISR_END).contains(&addr) && addr.is_multiple_of(8) +} + +fn host_eiointc_has_pending() -> bool { + for reg in 0..EIOINTC_ISR_REG_COUNT { + let addr = EIOINTC_ISR_BASE + reg * 8; + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.d {}, {}", out(reg) value, in(reg) addr); + } + if value != 0 { + return true; + } + } + + false +} + +fn iocsr_vcpu_index(vm_id: VMId, vcpu_id: VCpuId) -> Option { + if vm_id < MAX_IOCSR_VMS && vcpu_id < MAX_IOCSR_CPUS { + Some(vm_id * MAX_IOCSR_CPUS + vcpu_id) + } else { + None + } +} + +fn read_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId, addr: usize) -> Option { + let index = iocsr_vcpu_index(vm_id, vcpu_id)?; + match addr { + LOONGARCH_IOCSR_IPI_STATUS => Some(IOCSR_IPI_STATUS_WORDS[index].load(Ordering::Acquire)), + LOONGARCH_IOCSR_IPI_EN => Some(IOCSR_IPI_ENABLE_WORDS[index].load(Ordering::Acquire)), + LOONGARCH_IOCSR_IPI_SET | LOONGARCH_IOCSR_IPI_CLEAR | LOONGARCH_IOCSR_IPI_SEND => Some(0), + _ => None, + } +} + +fn write_guest_iocsr( + ctx: &mut LoongArchContextFrame, + vm_id: VMId, + vcpu_id: VCpuId, + addr: usize, + value: usize, +) -> Option { + let index = iocsr_vcpu_index(vm_id, vcpu_id)?; + match addr { + LOONGARCH_IOCSR_IPI_STATUS => Some(AxVCpuExitReason::Nothing), + LOONGARCH_IOCSR_IPI_EN => { + IOCSR_IPI_ENABLE_WORDS[index].store(value, Ordering::Release); + Some(AxVCpuExitReason::Nothing) + } + LOONGARCH_IOCSR_IPI_SET => { + IOCSR_IPI_STATUS_WORDS[index].fetch_or(value, Ordering::AcqRel); + ctx.gcsr_estat |= IPI_BIT; + Some(AxVCpuExitReason::Nothing) + } + LOONGARCH_IOCSR_IPI_CLEAR => { + let new_status = + IOCSR_IPI_STATUS_WORDS[index].fetch_and(!value, Ordering::AcqRel) & !value; + if new_status == 0 { + ctx.gcsr_estat &= !IPI_BIT; + } + Some(AxVCpuExitReason::Nothing) + } + LOONGARCH_IOCSR_IPI_SEND => { + let target_cpu = (value >> IOCSR_SEND_CPU_SHIFT) & IOCSR_SEND_CPU_MASK; + let action = value & IOCSR_IPI_ACTION_MASK; + if target_cpu == vcpu_id { + IOCSR_IPI_STATUS_WORDS[index].fetch_or(1usize << action, Ordering::AcqRel); + ctx.gcsr_estat |= IPI_BIT; + } else { + log::debug!( + "LoongArch guest IOCSR IPI_SEND ignored for unsupported target_cpu={} \ + action={}", + target_cpu, + action + ); + } + Some(AxVCpuExitReason::Nothing) + } + _ => None, + } +} + fn should_inject_guest_virtual_fault( ctx: &LoongArchContextFrame, badv: usize, @@ -260,7 +409,7 @@ fn emulate_cpucfg(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReas let rd = extract_field(ins, 0, 5); let rj = extract_field(ins, 5, 5); let cpucfg_idx = ctx.x[rj]; - let value = if cpucfg_idx > 20 { + let mut value = if cpucfg_idx > 20 { 0 } else { let result: usize; @@ -269,6 +418,9 @@ fn emulate_cpucfg(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReas } result }; + if cpucfg_idx == 2 { + value &= !CPUCFG2_CRYPTO; + } ctx.set_gpr(rd, value); advance_guest_pc(ctx); AxVCpuExitReason::Nothing @@ -285,19 +437,7 @@ fn emulate_csrx( let rj = extract_field(ins, 5, 5); let csr = extract_field(ins, 10, 14); - match csr { - CSR_TCFG | CSR_TVAL | CSR_TICLR => { - emulate_timer_csr(ctx, rd, rj, csr, vm_id, vcpu_id, guest_timer_token) - } - _ => { - match rj { - 0 => log::info!("LoongArch GSPR csrrd emulation: csr={:#x}", csr), - _ => log::info!("LoongArch GSPR csrwr/csrxchg emulation: csr={:#x}", csr), - } - ctx.set_gpr(rd, 0); - } - } - + emulate_guest_csr(ctx, rd, rj, csr, vm_id, vcpu_id, guest_timer_token); advance_guest_pc(ctx); AxVCpuExitReason::Nothing } @@ -307,15 +447,149 @@ const CSR_TCFG: usize = 0x41; const CSR_TVAL: usize = 0x42; const CSR_TICLR: usize = 0x44; -fn read_guest_timer_csr(ctx: &LoongArchContextFrame, csr: usize) -> usize { +fn read_guest_csr(ctx: &LoongArchContextFrame, csr: usize) -> usize { match csr { + CSR_CRMD => ctx.gcsr_crmd, + CSR_PRMD => ctx.gcsr_prmd, + CSR_EUEN => ctx.gcsr_euen, + CSR_MISC => ctx.gcsr_misc, + CSR_ECFG => ctx.gcsr_ectl, + CSR_ESTAT => ctx.gcsr_estat, + CSR_ERA => ctx.gcsr_era, + CSR_BADV => ctx.gcsr_badv, + CSR_BADI => ctx.gcsr_badi, + CSR_EENTRY => ctx.gcsr_eentry, + CSR_TLBIDX => ctx.gcsr_tlbidx, + CSR_TLBEHI => ctx.gcsr_tlbehi, + CSR_TLBELO0 => ctx.gcsr_tlbelo0, + CSR_TLBELO1 => ctx.gcsr_tlbelo1, + CSR_ASID => ctx.gcsr_asid, + CSR_PGDL => ctx.gcsr_pgdl, + CSR_PGDH => ctx.gcsr_pgdh, + CSR_PGD => guest_pgd(ctx), + CSR_PWCL => ctx.gcsr_pwcl, + CSR_PWCH => ctx.gcsr_pwch, + CSR_STLBPS => ctx.gcsr_stlbps, + CSR_RAVCFG => ctx.gcsr_ravcfg, + CSR_CPUID => ctx.gcsr_cpuid, + CSR_PRCFG1 => ctx.gcsr_prcfg1, + CSR_PRCFG2 => ctx.gcsr_prcfg2, + CSR_PRCFG3 => ctx.gcsr_prcfg3, + 0x30 => ctx.gcsr_save0, + 0x31 => ctx.gcsr_save1, + 0x32 => ctx.gcsr_save2, + 0x33 => ctx.gcsr_save3, + 0x34 => ctx.gcsr_save4, + 0x35 => ctx.gcsr_save5, + 0x36 => ctx.gcsr_save6, + 0x37 => ctx.gcsr_save7, + 0x38 => ctx.gcsr_save8, + 0x39 => ctx.gcsr_save9, + 0x3a => ctx.gcsr_save10, + 0x3b => ctx.gcsr_save11, + 0x3c => ctx.gcsr_save12, + 0x3d => ctx.gcsr_save13, + 0x3e => ctx.gcsr_save14, + 0x3f => ctx.gcsr_save15, + CSR_TID => ctx.gcsr_tid, CSR_TCFG => ctx.gcsr_tcfg, CSR_TVAL => ctx.gcsr_tval, CSR_TICLR => ctx.gcsr_ticlr, + CSR_LLBCTL => ctx.gcsr_llbctl, + CSR_TLBRENTRY => ctx.gcsr_tlbrentry, + CSR_TLBRBADV => ctx.gcsr_tlbrbadv, + CSR_TLBRERA => ctx.gcsr_tlbrera, + CSR_TLBRSAVE => ctx.gcsr_tlbrsave, + CSR_TLBRELO0 => ctx.gcsr_tlbrelo0, + CSR_TLBRELO1 => ctx.gcsr_tlbrelo1, + CSR_TLBREHI => ctx.gcsr_tlbrehi, + CSR_TLBRPRMD => ctx.gcsr_tlbrprmd, + CSR_DMW0 => ctx.gcsr_dmw0, + CSR_DMW1 => ctx.gcsr_dmw1, + CSR_DMW2 => ctx.gcsr_dmw2, + CSR_DMW3 => ctx.gcsr_dmw3, _ => 0, } } +fn write_guest_csr( + ctx: &mut LoongArchContextFrame, + csr: usize, + value: usize, + vm_id: VMId, + vcpu_id: VCpuId, + guest_timer_token: &mut Option, +) { + match csr { + CSR_CRMD => ctx.gcsr_crmd = value, + CSR_PRMD => ctx.gcsr_prmd = value, + CSR_EUEN => ctx.gcsr_euen = value, + CSR_MISC => ctx.gcsr_misc = value, + CSR_ECFG => ctx.gcsr_ectl = value, + CSR_ESTAT => { + ctx.gcsr_estat = (ctx.gcsr_estat & !0x3) | (value & 0x3); + } + CSR_ERA => ctx.gcsr_era = value, + CSR_BADV => ctx.gcsr_badv = value, + CSR_BADI => ctx.gcsr_badi = value, + CSR_EENTRY => ctx.gcsr_eentry = value, + CSR_TLBIDX => ctx.gcsr_tlbidx = value, + CSR_TLBEHI => ctx.gcsr_tlbehi = value, + CSR_TLBELO0 => ctx.gcsr_tlbelo0 = value, + CSR_TLBELO1 => ctx.gcsr_tlbelo1 = value, + CSR_ASID => ctx.gcsr_asid = value, + CSR_PGDL => ctx.gcsr_pgdl = value, + CSR_PGDH => ctx.gcsr_pgdh = value, + CSR_PGD => ctx.gcsr_pgd = value, + CSR_PWCL => ctx.gcsr_pwcl = value, + CSR_PWCH => ctx.gcsr_pwch = value, + CSR_STLBPS => ctx.gcsr_stlbps = value, + CSR_RAVCFG => ctx.gcsr_ravcfg = value, + CSR_CPUID => ctx.gcsr_cpuid = value, + CSR_PRCFG1 => ctx.gcsr_prcfg1 = value, + CSR_PRCFG2 => ctx.gcsr_prcfg2 = value, + CSR_PRCFG3 => ctx.gcsr_prcfg3 = value, + 0x30 => ctx.gcsr_save0 = value, + 0x31 => ctx.gcsr_save1 = value, + 0x32 => ctx.gcsr_save2 = value, + 0x33 => ctx.gcsr_save3 = value, + 0x34 => ctx.gcsr_save4 = value, + 0x35 => ctx.gcsr_save5 = value, + 0x36 => ctx.gcsr_save6 = value, + 0x37 => ctx.gcsr_save7 = value, + 0x38 => ctx.gcsr_save8 = value, + 0x39 => ctx.gcsr_save9 = value, + 0x3a => ctx.gcsr_save10 = value, + 0x3b => ctx.gcsr_save11 = value, + 0x3c => ctx.gcsr_save12 = value, + 0x3d => ctx.gcsr_save13 = value, + 0x3e => ctx.gcsr_save14 = value, + 0x3f => ctx.gcsr_save15 = value, + CSR_TID => ctx.gcsr_tid = value, + CSR_TCFG | CSR_TVAL | CSR_TICLR => { + write_guest_timer_csr(ctx, csr, value, vm_id, vcpu_id, guest_timer_token) + } + CSR_LLBCTL => ctx.gcsr_llbctl = value, + CSR_TLBRENTRY => ctx.gcsr_tlbrentry = value, + CSR_TLBRBADV => ctx.gcsr_tlbrbadv = value, + CSR_TLBRERA => ctx.gcsr_tlbrera = value, + CSR_TLBRSAVE => ctx.gcsr_tlbrsave = value, + CSR_TLBRELO0 => ctx.gcsr_tlbrelo0 = value, + CSR_TLBRELO1 => ctx.gcsr_tlbrelo1 = value, + CSR_TLBREHI => ctx.gcsr_tlbrehi = value, + CSR_TLBRPRMD => ctx.gcsr_tlbrprmd = value, + CSR_DMW0 => ctx.gcsr_dmw0 = value, + CSR_DMW1 => ctx.gcsr_dmw1 = value, + CSR_DMW2 => ctx.gcsr_dmw2 = value, + CSR_DMW3 => ctx.gcsr_dmw3 = value, + _ => log::debug!( + "LoongArch GSPR CSR write ignored: csr={:#x}, value={:#x}", + csr, + value + ), + } +} + fn guest_timer_periodic(ctx: &LoongArchContextFrame) -> bool { ctx.gcsr_tcfg & CSR_TCFG_PERIODIC != 0 } @@ -391,7 +665,7 @@ fn write_guest_timer_csr( } } -fn emulate_timer_csr( +fn emulate_guest_csr( ctx: &mut LoongArchContextFrame, rd: usize, rj: usize, @@ -400,7 +674,7 @@ fn emulate_timer_csr( vcpu_id: VCpuId, guest_timer_token: &mut Option, ) { - let old_value = read_guest_timer_csr(ctx, csr); + let old_value = read_guest_csr(ctx, csr); let mut return_value = old_value; if rj != 0 { @@ -411,15 +685,7 @@ fn emulate_timer_csr( return_value &= mask; (old_value & !mask) | (ctx.x[rd] & mask) }; - write_guest_timer_csr(ctx, csr, new_value, vm_id, vcpu_id, guest_timer_token); - log::debug!( - "Timer CSR emulation: csr={:#x} <- {:#x} (old={:#x})", - csr, - new_value, - old_value - ); - } else { - log::debug!("Timer CSR emulation: csr={:#x} -> {:#x}", csr, old_value); + write_guest_csr(ctx, csr, new_value, vm_id, vcpu_id, guest_timer_token); } ctx.set_gpr(rd, return_value); @@ -449,7 +715,12 @@ fn emulate_idle(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason AxVCpuExitReason::Idle } -fn emulate_iocsr(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { +fn emulate_iocsr( + ctx: &mut LoongArchContextFrame, + ins: usize, + vm_id: VMId, + vcpu_id: VCpuId, +) -> AxVCpuExitReason { let ty = extract_field(ins, 10, 3); let rd = extract_field(ins, 0, 5); let rj = extract_field(ins, 5, 5); @@ -457,45 +728,95 @@ fn emulate_iocsr(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReaso match ty { 0 => { - let value: usize; - unsafe { - core::arch::asm!("iocsrrd.b {}, {}", out(reg) value, in(reg) rj_value); - } + let value = read_guest_iocsr(vm_id, vcpu_id, rj_value).unwrap_or_else(|| { + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.b {}, {}", out(reg) value, in(reg) rj_value); + } + value + }); ctx.set_gpr(rd, (value as i8) as isize as usize); } 1 => { - let value: usize; - unsafe { - core::arch::asm!("iocsrrd.h {}, {}", out(reg) value, in(reg) rj_value); - } + let value = read_guest_iocsr(vm_id, vcpu_id, rj_value).unwrap_or_else(|| { + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.h {}, {}", out(reg) value, in(reg) rj_value); + } + value + }); ctx.set_gpr(rd, (value as i16) as isize as usize); } 2 => { - let value: usize; - unsafe { - core::arch::asm!("iocsrrd.w {}, {}", out(reg) value, in(reg) rj_value); - } + let value = read_guest_iocsr(vm_id, vcpu_id, rj_value).unwrap_or_else(|| { + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.w {}, {}", out(reg) value, in(reg) rj_value); + } + value + }); ctx.set_gpr(rd, (value as i32) as isize as usize); } 3 => { - let value: usize; - unsafe { - core::arch::asm!("iocsrrd.d {}, {}", out(reg) value, in(reg) rj_value); - } + let value = read_guest_iocsr(vm_id, vcpu_id, rj_value).unwrap_or_else(|| { + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.d {}, {}", out(reg) value, in(reg) rj_value); + } + value + }); ctx.set_gpr(rd, value); } - 4 => unsafe { - core::arch::asm!("iocsrwr.b {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); - }, - 5 => unsafe { - core::arch::asm!("iocsrwr.h {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); - }, - 6 => unsafe { - core::arch::asm!("iocsrwr.w {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); - }, - 7 => unsafe { - core::arch::asm!("iocsrwr.d {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); - }, + 4 => { + if let Some(reason) = + write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, ctx.x[rd] as u8 as usize) + { + advance_guest_pc(ctx); + return reason; + } else { + unsafe { + core::arch::asm!("iocsrwr.b {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); + } + } + } + 5 => { + if let Some(reason) = + write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, ctx.x[rd] as u16 as usize) + { + advance_guest_pc(ctx); + return reason; + } else { + unsafe { + core::arch::asm!("iocsrwr.h {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); + } + } + } + 6 => { + if let Some(reason) = + write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, ctx.x[rd] as u32 as usize) + { + advance_guest_pc(ctx); + return reason; + } else { + unsafe { + core::arch::asm!("iocsrwr.w {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); + } + } + } + 7 => { + if let Some(reason) = write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, ctx.x[rd]) { + advance_guest_pc(ctx); + return reason; + } else { + let is_eiointc_complete = is_eiointc_isr_addr(rj_value); + unsafe { + core::arch::asm!("iocsrwr.d {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); + } + if is_eiointc_complete && !host_eiointc_has_pending() { + ctx.gcsr_estat &= !HWI_MASK; + } + } + } _ => panic!("invalid LoongArch IOCSR opcode type: {ty}"), } @@ -539,7 +860,7 @@ fn emulate_gspr( return emulate_csrx(ctx, ins, vm_id, vcpu_id, guest_timer_token); } if matches(OPCODE_IOCSR, OPCODE_IOCSR_LEN) { - return emulate_iocsr(ctx, ins); + return emulate_iocsr(ctx, ins, vm_id, vcpu_id); } panic!( diff --git a/virtualization/loongarch_vcpu/src/vcpu.rs b/virtualization/loongarch_vcpu/src/vcpu.rs index 4e19b9bd16..03eb3544e4 100644 --- a/virtualization/loongarch_vcpu/src/vcpu.rs +++ b/virtualization/loongarch_vcpu/src/vcpu.rs @@ -125,6 +125,8 @@ pub struct LoongArchVCpuCreateConfig { pub struct LoongArchVCpuSetupConfig { pub passthrough_interrupt: bool, pub passthrough_timer: bool, + pub boot_args: [usize; 3], + pub boot_stack_top: usize, } impl AxArchVCpu for LoongArchVCpu { @@ -168,6 +170,14 @@ impl AxArchVCpu for LoongArchVCpu { } fn setup(&mut self, config: Self::SetupConfig) -> AxResult { + if config.boot_args != [0; 3] { + self.ctx.set_argument(config.boot_args[0]); + self.ctx.set_a1(config.boot_args[1]); + self.ctx.set_a2(config.boot_args[2]); + if config.boot_stack_top != 0 { + self.ctx.set_gpr(3, config.boot_stack_top); + } + } self.init_hv(config); Ok(()) } From 225f5874e96ce0f0c5fd39d57d262c97dee75168 Mon Sep 17 00:00:00 2001 From: szy Date: Tue, 9 Jun 2026 17:19:55 +0800 Subject: [PATCH 11/50] use init --- .../configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml index d8c3746f7a..cf7230645b 100644 --- a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml +++ b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml @@ -30,14 +30,14 @@ kernel_load_addr = 0x0020_0000 # The load address of the device tree blob (DTB). dtb_load_addr = 0x0010_0000 # Kernel command line. Rootfs mode intentionally uses virtio-blk /dev/vda. -cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw init=/bin/sh console=ttyS0 earlycon=uart,mmio,0x1fe001e0 nokaslr loglevel=8 ignore_loglevel swiotlb=1024 initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" +cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw console=ttyS0 earlycon=uart,mmio,0x1fe001e0 nokaslr loglevel=8 ignore_loglevel swiotlb=1024 initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" # Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`). # For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`, 2 means `MAP_RESERVED`. memory_regions = [ [0x0008_0000, 0x0018_0000, 0x7, 2], # Low bootinfo/DTB RAM 512K-2M MAP_RESERVED [0x0020_0000, 0x0fe0_0000, 0x7, 2], # Low System RAM 2-256M MAP_RESERVED - [0x8000_0000, 0x2000_0000, 0x7, 0], # High System RAM kept mapped but hidden from Linux memory map + [0x8000_0000, 0x2400_0000, 0x7, 0], # High System RAM kept mapped but hidden from Linux memory map ] # From 03a71203b0a9e433dda2df541f1ec62bcfba2968 Mon Sep 17 00:00:00 2001 From: szy Date: Wed, 10 Jun 2026 09:09:58 +0800 Subject: [PATCH 12/50] rebase --- os/arceos/modules/axhal/build.rs | 4 ++ os/axvisor/src/images/loongarch_image.rs | 39 ++++++++--- os/axvisor/src/images/loongarch_zboot.rs | 88 ++++++++++++++++++++++-- os/axvisor/src/images/mod.rs | 13 ++++ scripts/axbuild/src/axvisor/rootfs.rs | 69 +++++++++++++++++++ scripts/axbuild/src/context/mod.rs | 3 - 6 files changed, 198 insertions(+), 18 deletions(-) diff --git a/os/arceos/modules/axhal/build.rs b/os/arceos/modules/axhal/build.rs index 4411c54baf..0052c2393d 100644 --- a/os/arceos/modules/axhal/build.rs +++ b/os/arceos/modules/axhal/build.rs @@ -36,6 +36,7 @@ const DEFAULT_PLATFORMS: &[(&str, &str)] = &[("loongarch64", "ax_plat_loongarch6 fn main() { println!("cargo:rustc-check-cfg=cfg(plat_dyn)"); + println!("cargo:rustc-check-cfg=cfg(ax_hal_any_platform_feature)"); println!("cargo:rerun-if-changed={LINKER_TEMPLATE_NAME}"); println!("cargo:rerun-if-env-changed=AX_CONFIG_PATH"); println!("cargo:rerun-if-env-changed={}", feature_env("host-test")); @@ -133,6 +134,9 @@ fn gen_selected_platform(arch: &str, platform: Option<&PlatformFeature>) -> Resu if crate_name == Some("axplat_dyn") { println!("cargo:rustc-cfg=plat_dyn"); } + if crate_name.is_some() { + println!("cargo:rustc-cfg=ax_hal_any_platform_feature"); + } let content = crate_name .map(|crate_name| format!("extern crate {crate_name} as _;\n")) diff --git a/os/axvisor/src/images/loongarch_image.rs b/os/axvisor/src/images/loongarch_image.rs index 6f935b3a7c..0c39860e17 100644 --- a/os/axvisor/src/images/loongarch_image.rs +++ b/os/axvisor/src/images/loongarch_image.rs @@ -14,17 +14,30 @@ const PE_HEADER_OFFSET: u32 = 0x40; #[derive(Clone, Copy, Debug)] pub struct ImageInfo { pub entry: GuestPhysAddr, + pub image_size: usize, + pub load_offset: GuestPhysAddr, } pub fn try_load(image: &[u8], vm: AxVMRef) -> AxResult> { + let Some(info) = parse_info(image)? else { + return Ok(None); + }; + + validate_image_size(image, info.image_size)?; + let image = &image[..info.image_size]; + load_vm_image_from_memory(image, info.load_offset, vm)?; + Ok(Some(info)) +} + +pub fn parse_info(image: &[u8]) -> AxResult> { let Some(header) = Header::parse(image)? else { return Ok(None); }; - let image = &image[..header.image_size]; - load_vm_image_from_memory(image, GuestPhysAddr::from(header.load_offset), vm)?; Ok(Some(ImageInfo { entry: GuestPhysAddr::from(header.entry), + image_size: header.image_size, + load_offset: GuestPhysAddr::from(header.load_offset), })) } @@ -46,14 +59,10 @@ impl Header { } let image_size = read_u64(image, IMAGE_SIZE_OFFSET)? as usize; - if image_size == 0 || image.len() < image_size { + if image_size == 0 { return Err(ax_err_type!( InvalidInput, - format!( - "LoongArch Linux Image size is invalid: image={:#x}, header={:#x}", - image.len(), - image_size - ) + format!("LoongArch Linux Image size is invalid: header={image_size:#x}") )); } @@ -65,6 +74,20 @@ impl Header { } } +fn validate_image_size(image: &[u8], image_size: usize) -> AxResult { + if image.len() < image_size { + return Err(ax_err_type!( + InvalidInput, + format!( + "LoongArch Linux Image size is invalid: image={:#x}, header={:#x}", + image.len(), + image_size + ) + )); + } + Ok(()) +} + fn read_u32(image: &[u8], offset: usize) -> AxResult { let bytes = image .get(offset..offset + 4) diff --git a/os/axvisor/src/images/loongarch_zboot.rs b/os/axvisor/src/images/loongarch_zboot.rs index 4351123b13..a1e25c4944 100644 --- a/os/axvisor/src/images/loongarch_zboot.rs +++ b/os/axvisor/src/images/loongarch_zboot.rs @@ -1,7 +1,10 @@ use alloc::vec::Vec; use ax_errno::{AxResult, ax_err_type}; -use ruzstd::{decoding::StreamingDecoder, io::Read}; +use axvm::{AxVMRef, GuestPhysAddr}; +use ruzstd::{decoding::StreamingDecoder, decoding::errors::FrameDecoderError, io::Read}; + +use super::{load_vm_image_from_memory, loongarch_image}; const ZBOOT_MAGIC: &[u8; 8] = b"MZ\0\0zimg"; const HEADER_SIZE: usize = 0x40; @@ -10,6 +13,7 @@ const PAYLOAD_OFFSET_BITS: u64 = 32; const PAYLOAD_OFFSET_MASK: u64 = (1 << PAYLOAD_OFFSET_BITS) - 1; const FORMAT_OFFSET: usize = 0x18; const FORMAT_ZSTD: &[u8; 4] = b"zstd"; +const STREAM_CHUNK_SIZE: usize = 64 * 1024; #[derive(Debug)] pub struct ZbootImage { @@ -35,12 +39,7 @@ pub fn decompress(image: &[u8]) -> AxResult> { ) })?; - let mut decoder = StreamingDecoder::new(compressed).map_err(|err| { - ax_err_type!( - InvalidInput, - format!("failed to initialize LoongArch zboot zstd decoder: {err:?}") - ) - })?; + let mut decoder = StreamingDecoder::new(compressed).map_err(decoder_error)?; let mut payload = Vec::with_capacity(header.payload_size); decoder.read_to_end(&mut payload).map_err(|err| { ax_err_type!( @@ -59,6 +58,81 @@ pub fn decompress(image: &[u8]) -> AxResult> { Ok(Some(ZbootImage { payload })) } +pub fn try_load_streamed_image( + image: &[u8], + vm: AxVMRef, +) -> AxResult> { + let Some(header) = Header::parse(image)? else { + return Ok(None); + }; + + let compressed = compressed_payload(image, &header)?; + let mut decoder = StreamingDecoder::new(compressed).map_err(decoder_error)?; + let mut image_header = [0u8; HEADER_SIZE]; + decoder.read_exact(&mut image_header).map_err(|err| { + ax_err_type!( + InvalidInput, + format!("failed to decompress LoongArch zboot image header: {err}") + ) + })?; + + let Some(info) = loongarch_image::parse_info(&image_header)? else { + return Ok(None); + }; + load_vm_image_from_memory(&image_header, info.load_offset, vm.clone())?; + + let mut chunk = [0u8; STREAM_CHUNK_SIZE]; + let mut written = image_header.len(); + while written < info.image_size { + let read_len = (info.image_size - written).min(chunk.len()); + decoder.read_exact(&mut chunk[..read_len]).map_err(|err| { + ax_err_type!( + InvalidInput, + format!("failed to stream LoongArch zboot payload: {err}") + ) + })?; + load_vm_image_from_memory( + &chunk[..read_len], + GuestPhysAddr::from(info.load_offset.as_usize() + written), + vm.clone(), + )?; + written += read_len; + } + + info!( + "Streamed LoongArch zboot Image: payload_offset={:#x}, compressed={:#x}, image_size={:#x}, load_offset={:#x}", + header.payload_offset, + header.payload_size, + info.image_size, + info.load_offset.as_usize() + ); + + Ok(Some(info)) +} + +fn compressed_payload<'a>(image: &'a [u8], header: &Header) -> AxResult<&'a [u8]> { + image + .get(header.payload_offset..header.payload_end()) + .ok_or_else(|| { + ax_err_type!( + InvalidInput, + format!( + "LoongArch zboot payload range [{:#x}, {:#x}) exceeds image size {:#x}", + header.payload_offset, + header.payload_end(), + image.len() + ) + ) + }) +} + +fn decoder_error(err: FrameDecoderError) -> ax_errno::AxError { + ax_err_type!( + InvalidInput, + format!("failed to initialize LoongArch zboot zstd decoder: {err:?}") + ) +} + struct Header { payload_offset: usize, payload_size: usize, diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index 704b1f69a1..fb50688674 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -321,6 +321,19 @@ impl ImageLoader { } fn load_kernel_from_memory(&self, kernel: &[u8]) -> AxResult { + #[cfg(target_arch = "loongarch64")] + if let Some(info) = loongarch_zboot::try_load_streamed_image(kernel, self.vm.clone())? { + self.vm.with_config(|config| { + config.cpu_config.bsp_entry = info.entry; + config.cpu_config.ap_entry = info.entry; + }); + info!( + "LoongArch zboot Image entry set to {:#x}", + info.entry.as_usize() + ); + return Ok(()); + } + #[cfg(target_arch = "loongarch64")] if let Some(image) = loongarch_zboot::decompress(kernel)? { return self.load_kernel_from_memory(&image.payload); diff --git a/scripts/axbuild/src/axvisor/rootfs.rs b/scripts/axbuild/src/axvisor/rootfs.rs index 29ce1ac620..85d9787b65 100644 --- a/scripts/axbuild/src/axvisor/rootfs.rs +++ b/scripts/axbuild/src/axvisor/rootfs.rs @@ -8,7 +8,9 @@ use std::{ fs, + io::Write, path::{Path, PathBuf}, + process::Command, }; use anyhow::{Context, anyhow}; @@ -84,6 +86,7 @@ fn prepare_loongarch_linux_memory_vmconfigs( continue; } + ensure_loongarch_busybox_serial_init(&rootfs_path, &out_dir)?; rootfs::inject::extract_file(&rootfs_path, "/guest/linux/linux-qemu", &kernel_path) .with_context(|| { format!( @@ -114,6 +117,72 @@ fn prepare_loongarch_linux_memory_vmconfigs( Ok(()) } +fn ensure_loongarch_busybox_serial_init(rootfs_path: &Path, out_dir: &Path) -> anyhow::Result<()> { + let Some(inittab) = rootfs::inject::read_text_file(rootfs_path, "/etc/inittab")? else { + return Ok(()); + }; + let replacement_content = loongarch_busybox_inittab(); + if inittab == replacement_content + || (!inittab.contains("/sbin/openrc") && !inittab.contains("/etc/init.d/rcS")) + || rootfs_file_exists(rootfs_path, "/sbin/openrc")? + { + return Ok(()); + } + + fs::create_dir_all(out_dir) + .with_context(|| format!("failed to create {}", out_dir.display()))?; + let replacement = out_dir.join("inittab.busybox"); + write_text_file(&replacement, replacement_content)?; + rootfs::inject::replace_file(rootfs_path, "/etc/inittab", &replacement) + .with_context(|| format!("failed to patch /etc/inittab in {}", rootfs_path.display()))?; + Ok(()) +} + +fn loongarch_busybox_inittab() -> &'static str { + concat!( + "# /etc/inittab - BusyBox init for LoongArch AxVisor rootfs\n", + "::sysinit:/bin/mount -t proc proc /proc\n", + "::sysinit:/bin/mount -t sysfs sysfs /sys\n", + "::sysinit:/bin/mount -t devtmpfs devtmpfs /dev\n", + "ttyS0::respawn:/bin/sh\n", + "::ctrlaltdel:/sbin/reboot\n", + "::shutdown:/bin/umount -a -r\n", + ) +} + +fn rootfs_file_exists(rootfs_path: &Path, guest_path: &str) -> anyhow::Result { + let output = Command::new("debugfs") + .arg("-R") + .arg(format!("stat {guest_path}")) + .arg(rootfs_path) + .output() + .with_context(|| format!("failed to spawn debugfs for {}", rootfs_path.display()))?; + let stdout = String::from_utf8_lossy(&output.stdout); + let stderr = String::from_utf8_lossy(&output.stderr); + if stdout.contains("File not found") + || stdout.contains("File not found by ext2_lookup") + || stderr.contains("File not found") + || stderr.contains("File not found by ext2_lookup") + { + return Ok(false); + } + if output.status.success() { + return Ok(true); + } + Err(anyhow!( + "failed to stat {guest_path} in {}: {}", + rootfs_path.display(), + stderr.trim() + )) +} + +fn write_text_file(path: &Path, content: &str) -> anyhow::Result<()> { + let mut file = + fs::File::create(path).with_context(|| format!("failed to create {}", path.display()))?; + file.write_all(content.as_bytes()) + .with_context(|| format!("failed to write {}", path.display())) +} + pub(super) async fn load_patched_qemu_config( axvisor: &mut Axvisor, request: &ResolvedAxvisorRequest, diff --git a/scripts/axbuild/src/context/mod.rs b/scripts/axbuild/src/context/mod.rs index aa87d7a7b0..62e02b6329 100644 --- a/scripts/axbuild/src/context/mod.rs +++ b/scripts/axbuild/src/context/mod.rs @@ -22,8 +22,6 @@ use ostool::{ }, }; -use crate::support::process::ProcessExt; - mod arch; mod resolve; mod snapshot; @@ -184,7 +182,6 @@ impl AppContext { qemu, debug: self.debug, dtb_dump: false, - show_output: true, })), ) .await; From 4e6e94a28930b131a896c0f4a1403418df3b37ea Mon Sep 17 00:00:00 2001 From: szy Date: Wed, 10 Jun 2026 09:40:34 +0800 Subject: [PATCH 13/50] add loongarch CI --- scripts/axbuild/src/axvisor/rootfs.rs | 2 +- scripts/axbuild/src/axvisor/test/qemu.rs | 10 ++++++++-- .../qemu/build-loongarch64-unknown-none-softfloat.toml | 2 +- .../axvisor/normal/qemu/smoke/qemu-loongarch64.toml | 6 +++--- 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/scripts/axbuild/src/axvisor/rootfs.rs b/scripts/axbuild/src/axvisor/rootfs.rs index 85d9787b65..d611b7481e 100644 --- a/scripts/axbuild/src/axvisor/rootfs.rs +++ b/scripts/axbuild/src/axvisor/rootfs.rs @@ -57,7 +57,7 @@ pub(super) async fn qemu(axvisor: &mut Axvisor, args: super::ArgsQemu) -> anyhow .await } -fn prepare_loongarch_linux_memory_vmconfigs( +pub(crate) fn prepare_loongarch_linux_memory_vmconfigs( request: &mut ResolvedAxvisorRequest, workspace_root: &Path, explicit_rootfs: Option<&Path>, diff --git a/scripts/axbuild/src/axvisor/test/qemu.rs b/scripts/axbuild/src/axvisor/test/qemu.rs index a72dd56e5b..931dd87dce 100644 --- a/scripts/axbuild/src/axvisor/test/qemu.rs +++ b/scripts/axbuild/src/axvisor/test/qemu.rs @@ -117,15 +117,21 @@ impl Axvisor { let mut summary = test_qemu::QemuTestSummary::default(); let asset_config = axvisor_case_asset_config(); - let build_groups = test_qemu::prepare_case_build_groups(&cases, |build_config_path| { + let mut build_groups = test_qemu::prepare_case_build_groups(&cases, |build_config_path| { Self::qemu_group_build_context(&request, build_config_path) })?; // Phase 1: Build all build groups first so compilation errors surface // before any QEMU time is spent. - for build_group in &build_groups { + for build_group in &mut build_groups { rootfs::ensure_qemu_rootfs_ready(&build_group.request, self.app.workspace_root(), None) .await?; + rootfs::prepare_loongarch_linux_memory_vmconfigs( + &mut build_group.request, + self.app.workspace_root(), + None, + )?; + build_group.cargo = build::load_cargo_config(&build_group.request)?; if build_group_needs_arceos_x86_64_guest(&build_group.request) { self.build_arceos_x86_64_guest_image() .await diff --git a/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml b/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml index c4efdb343d..e0b23fe9f1 100644 --- a/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml +++ b/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml @@ -7,4 +7,4 @@ log = "Info" max_cpu_num = 1 plat_dyn = false target = "loongarch64-unknown-none-softfloat" -vm_configs = [] +vm_configs = ["os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml"] diff --git a/test-suit/axvisor/normal/qemu/smoke/qemu-loongarch64.toml b/test-suit/axvisor/normal/qemu/smoke/qemu-loongarch64.toml index 57fca3e4d7..a5131ba48c 100644 --- a/test-suit/axvisor/normal/qemu/smoke/qemu-loongarch64.toml +++ b/test-suit/axvisor/normal/qemu/smoke/qemu-loongarch64.toml @@ -22,8 +22,8 @@ fail_regex = [ "(?i)login incorrect", "(?i)permission denied", ] -success_regex = ["Welcome to AxVisor Shell!", "axvisor:\\$"] -shell_prefix = "axvisor:$" -shell_init_cmd = "" +success_regex = ["(?m)^guest linux test pass!\\s*$"] +shell_prefix = "~ #" +shell_init_cmd = "pwd && echo 'guest linux test pass!'" to_bin = false uefi = false From 64c2cbdc3fa4708be36e5c1bb355e3c3d737dae4 Mon Sep 17 00:00:00 2001 From: szy Date: Wed, 10 Jun 2026 10:31:08 +0800 Subject: [PATCH 14/50] fix loongarch arcoes CI --- test-suit/arceos/c/qemu-loongarch64.toml | 2 ++ test-suit/arceos/rust/qemu-loongarch64.toml | 2 +- virtualization/axvcpu/src/test.rs | 16 ++++++++++------ 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/test-suit/arceos/c/qemu-loongarch64.toml b/test-suit/arceos/c/qemu-loongarch64.toml index 6c17a43491..d1f64409a6 100644 --- a/test-suit/arceos/c/qemu-loongarch64.toml +++ b/test-suit/arceos/c/qemu-loongarch64.toml @@ -1,4 +1,6 @@ args = [ + "-m", + "2G", "-smp", "4", "-device", diff --git a/test-suit/arceos/rust/qemu-loongarch64.toml b/test-suit/arceos/rust/qemu-loongarch64.toml index 6a7d02ae5b..710ff27427 100644 --- a/test-suit/arceos/rust/qemu-loongarch64.toml +++ b/test-suit/arceos/rust/qemu-loongarch64.toml @@ -1,6 +1,6 @@ args = [ "-m", - "256M", + "2G", "-smp", "4", "-device", diff --git a/virtualization/axvcpu/src/test.rs b/virtualization/axvcpu/src/test.rs index 10a3bfbbd5..b0d5388fa0 100644 --- a/virtualization/axvcpu/src/test.rs +++ b/virtualization/axvcpu/src/test.rs @@ -32,8 +32,6 @@ mod tests { // Mock architecture implementation for testing #[derive(Debug)] struct MockArchVCpu { - vm_id: VMId, - vcpu_id: VCpuId, entry: Option, ept_root: Option, is_setup: bool, @@ -57,11 +55,9 @@ mod tests { type CreateConfig = MockCreateConfig; type SetupConfig = MockSetupConfig; - fn new(vm_id: VMId, vcpu_id: VCpuId, config: Self::CreateConfig) -> AxResult { + fn new(_vm_id: VMId, _vcpu_id: VCpuId, config: Self::CreateConfig) -> AxResult { config.call_log.borrow_mut().push("new".to_string()); Ok(Self { - vm_id, - vcpu_id, entry: None, ept_root: None, is_setup: false, @@ -217,9 +213,17 @@ mod tests { assert!(result.is_ok()); assert_eq!(vcpu.state(), VCpuState::Ready); - // Invalid transition should fail + // Mismatched `from` state should fail without changing the current state. let result = vcpu.transition_state(VCpuState::Running, VCpuState::Free); assert!(result.is_err()); + assert_eq!(vcpu.state(), VCpuState::Ready); + + // A failed transition body should mark the VCpu as invalid. + let result: AxResult<()> = + vcpu.with_state_transition(VCpuState::Ready, VCpuState::Free, || { + Err(AxError::BadState) + }); + assert!(result.is_err()); assert_eq!(vcpu.state(), VCpuState::Invalid); } From c78efb50e04b83d6a7cf123a420dc63fa91e15fb Mon Sep 17 00:00:00 2001 From: szy Date: Wed, 10 Jun 2026 15:20:26 +0800 Subject: [PATCH 15/50] fix(ci): raise Starry LoongArch QEMU memory --- test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml index 8017c7c2c4..6d8635bf07 100644 --- a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml @@ -5,7 +5,7 @@ args = [ "la464", "-nographic", "-m", - "512M", + "2G", "-smp", "4", "-device", From 97362552be26dfe96d55a24f6e05af1e9f11049b Mon Sep 17 00:00:00 2001 From: szy Date: Wed, 10 Jun 2026 16:29:45 +0800 Subject: [PATCH 16/50] fix loongarch CI --- test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml | 2 +- test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml index 59851ea694..309c40be41 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml @@ -22,7 +22,7 @@ args = [ "virtio-tablet-pci", ] uefi = false -to_bin = true +to_bin = false shell_prefix = "root@starry:" test_commands = [ ''' diff --git a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml index 6d8635bf07..1d35f03160 100644 --- a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml @@ -18,7 +18,7 @@ args = [ "user,id=net0", ] uefi = false -to_bin = true +to_bin = false shell_prefix = "root@starry:" test_commands = [ ''' From ef4802a673697c56734b8d4b347c8b8354350fdd Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 11 Jun 2026 09:24:47 +0800 Subject: [PATCH 17/50] docs(axvisor): clean LoongArch debug notes --- os/axvisor/doc/loongarch/debug-log-restore.md | 17 -- .../loongarch/gintc-hwi-passthrough-freeze.md | 195 +++--------- .../implementation-gaps-and-roadmap.md | 148 ---------- os/axvisor/doc/loongarch/interrupt-wakeup.md | 125 -------- .../loongarch/linux-direct-boot-analysis.md | 124 -------- .../doc/loongarch/restore-debug-logs.patch | 277 ------------------ os/axvisor/doc/loongarch/rootfs-virtio-blk.md | 68 ----- os/axvisor/doc/loongarch/stage2-tlb-refill.md | 85 ++++-- 8 files changed, 113 insertions(+), 926 deletions(-) delete mode 100644 os/axvisor/doc/loongarch/debug-log-restore.md delete mode 100644 os/axvisor/doc/loongarch/implementation-gaps-and-roadmap.md delete mode 100644 os/axvisor/doc/loongarch/interrupt-wakeup.md delete mode 100644 os/axvisor/doc/loongarch/linux-direct-boot-analysis.md delete mode 100644 os/axvisor/doc/loongarch/restore-debug-logs.patch delete mode 100644 os/axvisor/doc/loongarch/rootfs-virtio-blk.md diff --git a/os/axvisor/doc/loongarch/debug-log-restore.md b/os/axvisor/doc/loongarch/debug-log-restore.md deleted file mode 100644 index adf162e259..0000000000 --- a/os/axvisor/doc/loongarch/debug-log-restore.md +++ /dev/null @@ -1,17 +0,0 @@ -# LoongArch 调试日志恢复补丁 - -`restore-debug-logs.patch` 保存了一组 LoongArch LVZ 启动/VM-exit 定位用日志。 - -正常开发时不应用该补丁，避免启动日志变慢、变多。需要重新定位启动卡顿、中断、GSPR/IOCSR、timer、guest PC 推进等问题时，在仓库根目录执行： - -```bash -git apply os/axvisor/doc/loongarch/restore-debug-logs.patch -``` - -定位完成后移除这些调试日志： - -```bash -git apply -R os/axvisor/doc/loongarch/restore-debug-logs.patch -``` - -补丁已用 `git apply --check` 验证可应用到当前代码。 diff --git a/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md b/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md index 6c062bd015..507954ca68 100644 --- a/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md +++ b/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md @@ -1,24 +1,41 @@ # LoongArch64 LVZ: GINTC HWI Passthrough 导致 Guest UART 控制台卡死 +本文记录 LoongArch LVZ passthrough HWI 的一个关键问题：不能在每次 VM entry +时重写 GINTC passthrough 配置，否则可能清掉 guest pending HWI，导致 Linux guest +串口输入输出卡死。 + ## 现象 -在 Axvisor (LoongArch64 QEMU-LVZ) 上以 passthrough 模式运行 Linux guest 时， -guest 控制台在执行若干命令后会**完全冻结**——不再响应任何输入输出，但 guest 内核本身并未崩溃。 +在 LoongArch64 QEMU-LVZ 上运行 Linux guest 时，guest shell 曾出现过随机卡死： -**复现条件**： -- VM 配置：`passthrough_devices = [["/"]]`，`interrupt_mode = "passthrough"` -- 在 guest 内启动高频 shell 循环（如 `while true; do echo "..."; usleep 500000; done`） -- 同时手动输入命令 -- 通常在执行数十条命令后触发冻结 +- guest 内核没有崩溃； +- vCPU 循环还在运行； +- 控制台不再响应输入输出； +- 高频串口输出或连续输入更容易触发。 ## 根因 -`gintc_set_hwi_passthrough(0xff)` 在**每次 VM entry** 时被调用 -（调用链：`vcpu_run()` → `vm.run_vcpu()` → `vcpu.bind()` → `enable_guest_mode()`）， -该函数写 GINTC 寄存器时，其内部逻辑会清除 **HWIS（HWI Status）** 中的 pending 位， -导致在此间隙到达的 UART 中断被静默丢弃。 +GINTC 的 HWI 相关位里，`HWIC` 是 write-one-clear 语义。写入 `HWIC` 会清除 +对应的 `HWIS` pending 位。 + +如果 `gintc_set_hwi_passthrough(0xff)` 在每次 VM entry 都执行，并且写入了 +`HWIC=0xff`，就会出现这个竞态： + +```text +guest 运行 + -> timer 导致 VM exit + -> host 处理 exit + -> UART HWI 在此期间到达，暂存在 GINTC HWIS + -> host 准备重新进入 guest + -> 重写 GINTC，并写入 HWIC + -> HWIS pending 位被清掉 + -> guest 丢失 UART 中断 +``` + +guest 串口驱动依赖 UART 中断推进收发。中断被清掉后，guest 可能停在 idle 或等待 I/O +完成的位置，看起来就是 shell 卡死。 -### GINTC 寄存器结构 (CSR 0x52) +## GINTC 位语义 | 位域 | 名称 | 含义 | |------|------|------| @@ -26,121 +43,27 @@ guest 控制台在执行若干命令后会**完全冻结**——不再响应任 | [15:8] | HWIP | HWI passthrough 使能掩码 | | [23:16] | HWIC | 写 1 清除对应 HWIS 位 | -`gintc_set_hwi_passthrough()` 的**原始实现**同时写入了 HWIC=0xFF： +问题代码的核心是把 passthrough mask 同时写到了 `HWIP` 和 `HWIC`： ```rust -// 原始代码（有 bug） pub(crate) unsafe fn gintc_set_hwi_passthrough(mask: usize) { let mut gintc = read_gintc(); gintc &= !GINTC_HWIP_MASK; - gintc &= !GINTC_HWIC_MASK; // ← 准备写入 HWIC + gintc &= !GINTC_HWIC_MASK; gintc |= (mask << GINTC_HWIP_SHIFT) & GINTC_HWIP_MASK; - gintc |= (mask << GINTC_HWIC_SHIFT) & GINTC_HWIC_MASK; // ← HWIC=0xFF，清除所有 HWIS！ + gintc |= (mask << GINTC_HWIC_SHIFT) & GINTC_HWIC_MASK; write_gintc(gintc); } ``` -写入 HWIC 位会清除对应的 HWIS pending 位。当 HWIC=0xFF 时，所有 8 条 HWI 线的 pending 状态被一次性清除。 - -### 触发时序 - -``` - Guest 运行中 Host 处理 VM exit Guest 重新进入 - ────────────── ───────────────────── ───────────────── - 1. Timer 中断 ──→ 2. VM exit (timer) - 3. 处理 timer exit - (此时 guest IE=0) - 4. UART 中断到达 - → LVZ 拦截，记录在 - GINTC HWIS 中 - (pending) - 5. bind() → enable_guest_mode() - → gintc_set_hwi_passthrough(0xff) - → 写 GINTC，HWIC=0xFF - → HWIS pending 位被清除！ - 6. Guest 恢复运行 - 但 UART 中断已丢失 - Shell 阻塞在 UART I/O - → 进入 idle 循环 -``` - -步骤 5 是关键：每次 VM entry 都重置 GINTC，清除了步骤 4 中 pending 的 UART 中断。 - -### 为什么高频操作更容易触发 - -Timer VM exit 大约每 ~500μs 发生一次。UART 中断频率与 shell 输出成正比。 -命令越频繁，UART 中断越密集，在 timer VM exit 的处理窗口中 -命中"guest IE=0 且 UART 中断到达"的竞态窗口的概率越大。 -一旦某个 UART 中断被丢弃，guest 的串口驱动就会卡在等待中断唤醒的状态， -后续的 UART 中断也可能因为同样的竞态被反复丢弃。 - -## 证据 - -### 1. 心跳调试：vcpu 循环持续运行但 guest 卡在 idle - -在 vcpu loop 中加入每 500 次 VM exit 打印 guest 状态的心跳： - -``` -DBG heartbeat VM[1] VCpu[0] exit#14500 sepc=0x9000000000cbdd8c crmd=0xb4 - ectl=0x71c1d estat=0x800 era=0x9000000000cbdd8c -DBG heartbeat VM[1] VCpu[0] exit#15000 sepc=0x9000000000cbdd8c crmd=0xb4 - ectl=0x71c1d estat=0x800 era=0x9000000000cbdd8c -... -（冻结后心跳仍在输出，sepc/era 固定不变） -``` - -- `era=0x9000000000cbdd8c` = guest idle 循环地址（WFI/idle） -- `crmd=0xb4` = guest 中断已开启 (IE=1) -- `estat` 只有 timer 位 (0x800) 和 0 之间切换，**从未出现 HWI 位** -- 心跳持续输出 → vcpu 循环正常，问题在 guest 侧 - -### 2. GINTC 寄存器值确认 HWIS=0 - -修正 CSR 编号后读取 GINTC (CSR 0x52)： - -``` -DBG #500 gintc=0x0000ff00 est=0x800 ... (正常时) -DBG #4000 gintc=0x0000ff00 est=0x0 ... (卡住时) -``` - -- `gintc=0x0000ff00`：HWIP=0xFF（passthrough 全开），**HWIS=0x00**（无 pending HWI） -- 零 HWI VM exit — 从未出现非 timer 的 IRQ exit 日志 - -这说明 UART 中断在 EIOINTC/PCH-PIC 层面到达了，但在 GINTC 层面被丢弃。 - -### 3. 定期 HWI 注入可恢复 guest - -在 vcpu loop 中每 50 次 exit 注入一次 HWI2（UART 中断线）后： - -``` -[37] 00:00:36 ---------------------------------------- -ls -bin etc linuxrc root sys -[38] 00:00:37 ---------------------------------------- -pwd -/ -[39] 00:00:38 ---------------------------------------- -（命令正常响应，不再卡死） -``` - -通过 `pulse_hwi(2)` 向 guest 注入模拟的 UART 中断后，guest 恢复正常。 -这证实了 **guest 的中断处理逻辑本身没问题，问题在于中断信号在 GINTC 层面丢失**。 - -### 4. 禁用大页后问题消失（二次确认） - -该 bug 还与大页支持代码交互：大页 PTE 中 `LEVEL` 字段（bits[14:13]） -与 `PHYS_ADDR_MASK`（bits[47:12]）重叠，导致 `lddir`/`ldpte` 硬件页表遍历 -时物理地址被破坏。大页映射启用后 TLB refill 更频繁，放大了 GINTC 竞态窗口， -使卡死更快出现。但即使禁用大页，仅靠高频命令仍可触发，只是概率更低。 - ## 修复 -### 修复 1：GINTC passthrough 只配置一次 +修复分两部分。 -将 `gintc_set_hwi_passthrough(0xff)` 从 `enable_guest_mode()` -（每次 VM entry 调用）移到 `init_hv()`（仅 vcpu setup 时调用一次）。 +第一，GINTC passthrough mask 只在 vCPU 初始化时配置一次，不放在每次 VM entry +都会执行的路径里： -**文件**：`components/loongarch_vcpu/src/vcpu.rs` +**文件**：`virtualization/loongarch_vcpu/src/vcpu.rs` ```rust // init_hv() — 只调用一次 @@ -160,9 +83,7 @@ unsafe fn enable_guest_mode(&self) { } ``` -**文件**：`components/loongarch_vcpu/src/registers.rs` - -同时修复 `gintc_set_hwi_passthrough()` 本身，不再写入 HWIC 位： +第二，`gintc_set_hwi_passthrough()` 只更新 `HWIP`，不写 `HWIC`： ```rust pub(crate) unsafe fn gintc_set_hwi_passthrough(mask: usize) { @@ -174,22 +95,7 @@ pub(crate) unsafe fn gintc_set_hwi_passthrough(mask: usize) { } ``` -### 修复 2：大页 PTE 不存储 LEVEL 到物理地址位域 - -**文件**：`components/page_table_multiarch/page_table_entry/src/arch/loongarch64.rs` -**文件**：`components/axaddrspace/src/npt/arch/loongarch64.rs` - -LoongArch 大页 PTE 只设置 `GH` 位标识大页，不存储 LEVEL 到内存 PTE 中。 -`lddir` 硬件遍历页表时根据当前遍历层级自动识别大页，无需软件在 PTE 中记录 level。 - -```rust -// 大页 PTE 只设 GH，不写 LEVEL -fn new_page_with_level(paddr: PhysAddr, flags: MappingFlags, level: usize) -> Self { - Self::new_page(paddr, flags, level > 0) // level > 0 时设 GH 位 -} -``` - -## 原理：LoongArch LVZ 中断路径 +## 中断路径 ``` 外设 (UART) → PCH-PIC → EIOINTC → CPU 中断控制器 → CPU @@ -201,22 +107,17 @@ fn new_page_with_level(paddr: PhysAddr, flags: MappingFlags, level: usize) -> Se HWIC 写 1 清除 pending ``` -在 passthrough 模式下（HWIP=0xFF），外部硬件中断不引起 VM exit， -直接注入 guest。但如果 timer 中断导致 VM exit（`gcfg_set_toti(false)`）， -则在 host 处理期间到达的 HWI 会被 LVZ 暂存到 GINTC HWIS 中。 -问题在于 host 在恢复 guest 前重写 GINTC 时把 HWIS 清掉了。 - -## 经验教训 +在 passthrough 模式下，外部硬件中断可以直接进入 guest。但如果 host 正在处理 +timer exit 或其他 VM exit，这段时间到达的 HWI 可能会先挂在 GINTC 的 `HWIS` 中。 +因此 VM entry 前的寄存器恢复路径必须避免清除 `HWIS`。 -1. **不要在每次 VM entry 时重写中断控制器配置**。静态配置（如 passthrough mask） - 只需初始化一次，重复写入会带来意外的副作用。 +## 注意事项 -2. **GINTC 的 HWIC 是 write-to-clear 语义**。写 HWIC 位会清除对应的 HWIS pending 位， - 这是 LoongArch LVZ 架构的设计，但容易被忽视。 +1. 静态中断控制器配置不要放在高频 VM entry 路径中反复写。 +2. 写 `HWIC` 会清 pending HWI，不能把它当成普通配置位。 +3. 如果 guest shell 卡在 idle 但 vCPU loop 仍在运行，要优先检查 pending HWI 是否被丢弃。 -3. **调试方法**：通过心跳日志区分"vcpu 循环停止"和"vcpu 循环运行但 guest 卡死"， - 是定位虚拟化 bug 的关键第一步。前者指向 host/hypervisor 问题，后者指向 guest 侧问题。 +## 相关文件 -4. **多个 bug 可以交互放大**：GINTC 丢失中断本身是一个低概率竞态， - 但大页映射引入的 TLB refill 异常增加了 VM exit 频率和内存映射错误， - 使卡死更容易复现。 +- `virtualization/loongarch_vcpu/src/vcpu.rs` +- `virtualization/loongarch_vcpu/src/registers.rs` diff --git a/os/axvisor/doc/loongarch/implementation-gaps-and-roadmap.md b/os/axvisor/doc/loongarch/implementation-gaps-and-roadmap.md deleted file mode 100644 index 0d05d7aac2..0000000000 --- a/os/axvisor/doc/loongarch/implementation-gaps-and-roadmap.md +++ /dev/null @@ -1,148 +0,0 @@ -# LoongArch 外部中断默认直通问题 - -LoongArch 当前在 `feature = "hypervisor"` 下，对 EIOINTC claim 出来的外部 IRQ 没有判断归属，而是默认认为外部 IRQ 都应该交给 guest interrupt controller。host 只完成物理中断控制器层面的 claim/complete，不执行设备级中断处理。 - -这意味着当前实现隐含了一个前提：**hypervisor 模式下所有 EIOINTC 外设中断都属于 guest**。这个前提只适合“外设全部直通给 guest，host 不拥有外设驱动”的 bring-up 场景；一旦 host 也需要处理某些设备，或存在多个 VM，这个模型就不够。 - -## 当前代码行为 - -外部中断进入 host 后，CPU 侧最初看到的是 EIOINTC 入口线： - -```rust -IrqType::Io -``` - -随后 host 调用： - -```rust -eiointc::claim_irq() -``` - -从 EIOINTC 读取真实外部 IRQ 号，并转换成： - -```rust -IrqType::Ex(ex_irq) -``` - -在非 hypervisor 模式下，host 会查自己的 handler table： - -```rust -if !IRQ_HANDLER_TABLE.handle(ex_irq) { - debug!("Unhandled IRQ {irq:?}"); -} -``` - -但在 hypervisor 模式下，host 不处理这个外部 IRQ： - -```rust -trace!("Leaving passthrough external IRQ {ex_irq} to guest interrupt controller"); -``` - -最后无论是否是 hypervisor 模式，host 都会执行： - -```rust -eiointc::complete_irq(ex_irq); -``` - -这里的 `complete_irq()` 只是告诉物理 EIOINTC：这次 claim 出来的 IRQ 已经完成控制器层面的处理，可以继续投递后续中断。它不表示 guest 已经处理完设备，也不表示设备中断源已经被清除。 - -## 问题本质 - -当前代码没有回答这个问题： - -```text -这个外部 IRQ 到底属于谁？ -``` - -它直接把所有 `IrqType::Ex(ex_irq)` 都当成 guest passthrough IRQ。 - -实际 hypervisor 里通常需要区分： - -```text -IRQ n -> host -IRQ n -> VM0 -IRQ n -> VM1 -IRQ n -> masked / reserved -``` - -如果没有 IRQ ownership/routing 表，就无法可靠支持： - -- host 自己使用串口、磁盘、网卡或管理设备； -- 多 VM 共享同一个物理中断控制器； -- 部分设备 emulation，部分设备 passthrough； -- legacy IRQ、MSI、timer、IPI 等不同中断来源的不同处理策略。 - -## 为什么当前暂时能工作 - -当前 LoongArch bring-up 场景主要依赖 passthrough interrupt： - -```rust -gintc_set_hwi_passthrough(0xff); -``` - -这表示 guest HWI 线被配置为 passthrough。对于“外设都给 guest”的单 VM 场景，host 看到外部 IRQ 后不做设备处理，只 complete 物理 EIOINTC，是可以解释得通的。 - -典型流程是： - -```text -外设触发 IRQ - -> EIOINTC 置 pending - -> host trap 到外部中断 - -> host claim 得到 ex_irq - -> host 不调用自己的 IRQ handler - -> guest interrupt controller / HWI passthrough 负责让 guest 看到中断 - -> host complete EIOINTC -``` - -这个流程依赖一个条件：这个 IRQ 的设备语义确实由 guest 负责处理。 - -## 风险 - -如果某个外部 IRQ 实际应该由 host 处理，当前代码会跳过 host handler，导致 host 永远不处理该设备中断。 - -如果未来支持多个 VM，当前代码也无法判断这个 IRQ 应该注入哪个 VM、哪个 vCPU。 - -如果设备是 level-triggered，host complete EIOINTC 时 guest 可能还没有清设备中断源。之后是否重新触发依赖硬件和中断控制器语义，需要单独验证。 - -如果设备是 edge-triggered 或 MSI，需要确认 host 过早 complete 是否存在事件丢失风险。 - -## 与其他架构的差异 - -RISC-V 当前也有类似简化，但代码里已经明确留下 TODO： - -```rust -// TODO: judge irq's ownership before handling (axvisor or any vm). -``` - -也就是说 RISC-V 当前也知道未来需要判断 IRQ 属于 axvisor 还是某个 VM。 - -AArch64 更偏向通过 passthrough SPI / vGIC 配置来描述 guest 拥有哪些中断，不是简单把所有外部 IRQ 都无条件视为 guest IRQ。 - -LoongArch 当前缺少类似的 ownership 判断，因此问题更集中地体现在 `IrqType::Ex(ex_irq)` 分支。 - -## 后续方向 - -需要引入 LoongArch IRQ ownership/routing 机制。外部 IRQ 处理应从： - -```text -所有 Ex IRQ 默认 guest -``` - -演进为： - -```text -claim physical IRQ - -> 查询 IRQ owner - -> owner 是 host：调用 IRQ_HANDLER_TABLE.handle(ex_irq) - -> owner 是 guest：注入 guest 或依赖 passthrough HWI - -> owner 不明确：mask 或 warn - -> 按控制器语义 complete physical IRQ -``` - -同时需要明确： - -- `complete_irq()` 与 guest 设备处理完成之间没有强同步关系； -- passthrough HWI 和 software injection 的适用边界； -- `Ex(ex_irq)` 到 guest vector/HWI 线的映射； -- 多 VM、多 vCPU 下 IRQ 注入目标； -- level-triggered、edge-triggered、MSI 的 complete/ack 时序。 diff --git a/os/axvisor/doc/loongarch/interrupt-wakeup.md b/os/axvisor/doc/loongarch/interrupt-wakeup.md deleted file mode 100644 index 69e1b718c1..0000000000 --- a/os/axvisor/doc/loongarch/interrupt-wakeup.md +++ /dev/null @@ -1,125 +0,0 @@ -# LoongArch Interrupt And Wakeup - -本文记录 LoongArch guest 外部中断注入与 vCPU 唤醒闭环的问题。IRQ injection 和 idle wakeup 需要放在一起看，因为 guest 等待设备或 timer 时，最终依赖的是同一条链路： - -```text -host receives timer / IPI / external IRQ - -> hypervisor marks or injects guest virtual interrupt - -> notify blocked vCPU task - -> vCPU resumes guest execution -``` - -## 当前状态 - -LoongArch 当前已经能处理部分 guest timer 和异常路径，但完整的事件驱动唤醒闭环尚未完成。 - -RISC-V 平台会注册 virtual IRQ injector： - -```rust -register_virtual_irq_injector(crate::hal::arch::inject_interrupt) -``` - -LoongArch 当前对应初始化仍为空： - -```rust -pub(super) fn init_platform_irq_injector() {} -``` - -同时，LoongArch guest `idle` 当前使用短轮询处理： - -```rust -AxVCpuExitReason::Idle => { - trace!("VM[{vm_id}] run VCpu[{vcpu_id}] Idle"); - super::timer::check_events(); - busy_wait(Duration::from_micros(50)); -} -``` - -这不是最终模型，而是 bring-up 阶段为了避免 guest 睡死的临时策略。 - -## 为什么 IRQ 和 idle 是同一个问题 - -标准虚拟化模型通常是： - -```text -guest idle/halt - -> vCPU task block - -> virtual timer / external interrupt / IPI arrives - -> hypervisor injects or marks virtual interrupt pending - -> notify blocked vCPU task - -> vCPU resumes guest execution -``` - -如果只有 IRQ injection，没有 notify blocked vCPU，guest 可能仍然睡着。 - -如果只有 idle wait，没有可靠 IRQ/timer notify，guest 可能在第一次 idle 后永久睡眠。 - -所以 LoongArch 后续需要补的是完整闭环，而不是单独补一个 IRQ handler 或单独改 `Idle` 分支。 - -## 当前短轮询的原因 - -如果把 `Idle` 直接改成： - -```rust -wait(vm_id) -``` - -vCPU task 会进入 wait queue。当前 LoongArch 还没有完整实现： - -```text -timer / IRQ arrives - -> inject virtual interrupt - -> notify target vCPU -``` - -因此 guest 可能在 idle 后无法醒来。 - -当前短轮询路径是： - -```text -Idle exit - -> check pending VMM timer events - -> busy wait 50us - -> re-enter guest -``` - -它能降低 guest idle loop 高频 VM exit 的开销，同时避免唤醒链路不完整导致 vCPU 睡死。 - -## 需要明确的中断语义 - -LoongArch 平台中断在 hypervisor 场景下需要明确： - -- 哪些中断由 host Axvisor 消费； -- 哪些中断应该交给 guest； -- claim/complete 的时机由 host 负责还是 guest 负责； -- PCH PIC、EIOINTC、PCI legacy IRQ/MSI 如何映射到 guest interrupt； -- pending interrupt 如何唤醒 blocked vCPU。 - -这些语义会影响： - -- guest timer； -- virtio-blk I/O 完成中断； -- PCI passthrough interrupt； -- guest idle 后等待设备中断； -- 多 vCPU IPI 或跨 CPU wakeup。 - -## 当前限制 - -- `busy_wait(Duration::from_micros(50))` 仍会消耗 host CPU。 -- 50us 是经验值，不是根据最近 timer deadline 动态计算。 -- `notify_vcpu_timer_expired()` 当前仍未实现。 -- LoongArch `init_platform_irq_injector()` 当前为空。 -- 外部中断到 guest virtual interrupt pending 的平台闭环尚未完成。 -- 中断注入后唤醒 blocked vCPU 的闭环尚未完成。 - -## 后续工作 - -1. 实现 LoongArch `init_platform_irq_injector()`。 -2. 明确 host IRQ handler 中 passthrough IRQ 的 claim/complete 策略。 -3. 实现外部 IRQ 到 `vcpu.inject_interrupt()` 或架构 pending interrupt 的路径。 -4. 为 VMM timer 增加查询最近 deadline 的接口。 -5. 实现 `notify_vcpu_timer_expired(vm_id, vcpu_id)`。 -6. timer、IPI、外部设备中断注入后通知目标 vCPU。 -7. 在 `Idle` 分支中先检查 pending virtual interrupt。 -8. 唤醒链路稳定后，把短轮询改成事件驱动 wait。 -9. 用 virtio-blk I/O 完成中断验证整条链路。 diff --git a/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md b/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md deleted file mode 100644 index 7de9c903dd..0000000000 --- a/os/axvisor/doc/loongarch/linux-direct-boot-analysis.md +++ /dev/null @@ -1,124 +0,0 @@ -# LoongArch Linux Direct Boot - -本文只记录 LoongArch Linux direct boot 问题：Axvisor 不经过 guest UEFI/bootloader，直接把 Linux kernel、cmdline、DTB 等启动信息放到 guest 可见的位置，然后跳到 Linux entry。 - -## 这个文件是什么 - -`linux-direct-boot-analysis.md` 用来说明 LoongArch Linux 的启动协议和 Axvisor 当前怎么模拟该启动环境。 - -它不跟踪 virtio-blk rootfs、IRQ 注入、idle 唤醒或 stage-2 TLB refill。这些问题分别放在独立文档中。 - -## 当前启动链路 - -当前 LoongArch Linux quick-start 的 direct boot 链路是： - -```text -VM TOML - -> ImageLoader 加载 LoongArch ELF kernel - -> 加载 DTB - -> setup_bootinfo 构造 LoongArch Linux bootinfo - -> 设置 guest boot_args - -> vCPU 进入 Linux entry -``` - -关键代码位置： - -- `os/axvisor/src/images/mod.rs` -- `os/axvisor/src/images/loongarch_elf.rs` -- `os/axvisor/src/images/loongarch_linux.rs` -- `virtualization/loongarch_vcpu/src/vcpu.rs` -- `virtualization/axvm/src/config.rs` -- `virtualization/axvm/src/vm.rs` - -## Kernel 格式 - -LoongArch loader 当前先尝试 ELF： - -```rust -loongarch_elf::try_load(...) -``` - -如果是 LoongArch ELF，就按 `PT_LOAD` segment 加载，并用 ELF entry 更新： - -```rust -config.cpu_config.bsp_entry = info.entry; -config.cpu_config.ap_entry = info.entry; -``` - -如果不是 ELF，则 fallback 为 raw image，按 `kernel_load_gpa` 直接拷贝。 - -当前 quick-start 使用的是 LoongArch ELF kernel。 - -## Boot 参数 - -LoongArch Linux 当前通过 boot args 接收 direct boot 信息： - -```text -a0 = 1 -a1 = cmdline GPA -a2 = EFI system table GPA -``` - -Axvisor 中对应设置为： - -```rust -config.cpu_config.boot_args = [1, CMDLINE_GPA, SYSTAB_GPA]; -``` - -其中 `setup_bootinfo()` 会构造： - -- cmdline buffer； -- EFI vendor string； -- EFI system table； -- EFI config table； -- EFI memory map； -- optional initrd table； -- optional DTB pointer。 - -## Cmdline 原则 - -`kernel.cmdline` 必须来自 VM 配置文件。loader 不应该自动生成或追加 `console=`、`root=`、`init=` 等参数。 - -当前原则： - -- `kernel.cmdline` 缺失时直接报错； -- 缺少 `console=` 只 warning； -- 缺少 `init=` / `rdinit=` 只 warning； -- quick-start 当前只维护 `root=/dev/vda` 的 virtio-blk rootfs 方式。 - -这样可以确保使用者能从配置文件明确知道 guest 是如何启动的。 - -## 与 ARM/RISC-V 的区别 - -AArch64 Linux direct boot 通常是： - -```text -x0 = DTB physical address -entry = raw Image entry -``` - -RISC-V Linux direct boot 通常是： - -```text -a0 = hart id -a1 = DTB physical address -entry = raw Image entry -``` - -LoongArch 这里不是简单传一个 DTB 地址，而是需要模拟 EFI-style bootinfo： - -```text -a0 = efi_boot flag -a1 = cmdline -a2 = EFI system table -``` - -因此不能直接复用 ARM 的 raw Image + `x0=dtb` 方法。 - -## 需要继续确认 - -1. EFI memory map 的 memory type 是否足够准确。 -2. DTB config table GUID 和 Linux LoongArch 实际读取路径是否完全匹配。 -3. 多内存段、多 vCPU、较大 initrd 时 bootinfo 边界是否正确。 -4. raw image fallback 是否需要更严格校验 entry/load address。 -5. `kernel.cmdline` 缺失时报错是否覆盖所有 direct boot 入口。 diff --git a/os/axvisor/doc/loongarch/restore-debug-logs.patch b/os/axvisor/doc/loongarch/restore-debug-logs.patch deleted file mode 100644 index f424390f78..0000000000 --- a/os/axvisor/doc/loongarch/restore-debug-logs.patch +++ /dev/null @@ -1,277 +0,0 @@ ---- a/components/loongarch_vcpu/src/exception.rs -+++ b/components/loongarch_vcpu/src/exception.rs -@@ -125,6 +125,24 @@ - - static GUEST_IOCSR_IPI_STATUS: AtomicUsize = AtomicUsize::new(0); - static GUEST_IOCSR_IPI_ENABLE: AtomicUsize = AtomicUsize::new(0); -+static DBG_TIMER_FORWARD_COUNT: AtomicUsize = AtomicUsize::new(0); -+static DBG_TIMER_WRITE_COUNT: AtomicUsize = AtomicUsize::new(0); -+static DBG_IDLE_EXIT_COUNT: AtomicUsize = AtomicUsize::new(0); -+static DBG_IOCSR_EMULATION_COUNT: AtomicUsize = AtomicUsize::new(0); -+static DBG_FETCHED_INSTRUCTION_COUNT: AtomicUsize = AtomicUsize::new(0); -+static DBG_GSPR_EMULATION_COUNT: AtomicUsize = AtomicUsize::new(0); -+static DBG_IRQ_EXIT_COUNT: AtomicUsize = AtomicUsize::new(0); -+static DBG_PC_ADVANCE_COUNT: AtomicUsize = AtomicUsize::new(0); -+static DBG_BRANCH_EMULATION_COUNT: AtomicUsize = AtomicUsize::new(0); -+ -+fn dbg_log_sparse(counter: &AtomicUsize) -> Option { -+ let count = counter.fetch_add(1, Ordering::Relaxed) + 1; -+ if count <= 16 || count.is_power_of_two() { -+ Some(count) -+ } else { -+ None -+ } -+} - - #[repr(u8)] - #[derive(Debug, Clone, Copy, PartialEq, Eq)] -@@ -370,6 +388,10 @@ - ctx.gcsr_crmd &= !(CSR_CRMD_PLV_MASK | CSR_CRMD_IE); - ctx.sepc = ctx.gcsr_eentry + ecode * guest_exception_vector_size(ctx); - ctx.guest_pc = ctx.sepc; -+ log::debug!( -+ "LoongArch inject guest exception: ecode={:#x}, esubcode={:#x}, pc={:#x}, badv={:#x}, entry={:#x}, gcrmd={:#x}, gestat={:#x}, gbadi={:#x}", -+ ecode, esubcode, pc, badv, ctx.sepc, ctx.gcsr_crmd, ctx.gcsr_estat, ctx.gcsr_badi, -+ ); - } - - fn inject_guest_emulated_memory_fault( -@@ -404,6 +426,10 @@ - ctx.gcsr_crmd = - (ctx.gcsr_crmd | CSR_CRMD_DA) & !(CSR_CRMD_PG | CSR_CRMD_PLV_MASK | CSR_CRMD_IE); - ctx.sepc = ctx.gcsr_tlbrentry; -+ log::debug!( -+ "LoongArch inject guest TLB refill: pc={:#x}, badv={:#x}, tlbrentry={:#x}, tlbrehi={:#x}, pgd={:#x}", -+ pc, badv, ctx.sepc, ctx.gcsr_tlbrehi, ctx.gcsr_pgd, -+ ); - } - - fn get_guest_interrupt_status(ctx: &LoongArchContextFrame) -> usize { -@@ -417,7 +443,14 @@ - } - - fn forward_timer_interrupt(ctx: &mut LoongArchContextFrame) { -+ let old_gestat = ctx.gcsr_estat; - ctx.gcsr_estat |= TIMER_BIT; -+ if let Some(count) = dbg_log_sparse(&DBG_TIMER_FORWARD_COUNT) { -+ log::debug!( -+ "LoongArch forward guest timer #{count}: pc={:#x}, sepc={:#x}, host_estat={:#x}, gcrmd={:#x}, gecfg={:#x}, old_gestat={:#x}, new_gestat={:#x}, host_tcfg={:#x}, host_tval={:#x}", -+ get_guest_pc(ctx), ctx.sepc, ctx.host_estat, ctx.gcsr_crmd, ctx.gcsr_ectl, old_gestat, ctx.gcsr_estat, read_host_timer_csr(CSR_TCFG), read_host_timer_csr(CSR_TVAL), -+ ); -+ } - ack_host_timer_interrupt(); - } - -@@ -447,16 +480,33 @@ - } - - fn advance_guest_pc(ctx: &mut LoongArchContextFrame) { -- let pc = get_guest_pc(ctx).wrapping_add(4); -+ let old_pc = get_guest_pc(ctx); -+ let old_sepc = ctx.sepc; -+ let old_gcsr_era = ctx.gcsr_era; -+ let pc = old_pc.wrapping_add(4); - ctx.sepc = pc; - ctx.guest_pc = pc; - ctx.gcsr_estat &= !CSR_ESTAT_EXC_MASK; -+ if let Some(count) = dbg_log_sparse(&DBG_PC_ADVANCE_COUNT) { -+ log::debug!( -+ "LoongArch guest PC advance #{count}: old_pc={:#x}, new_pc={:#x}, old_sepc={:#x}, preserved_gcsr_era={:#x}, host_tlbrera={:#x}", -+ old_pc, pc, old_sepc, old_gcsr_era, ctx.host_tlbrera, -+ ); -+ } - } - - fn set_guest_pc(ctx: &mut LoongArchContextFrame, pc: usize) { -+ let old_pc = get_guest_pc(ctx); -+ let old_sepc = ctx.sepc; - ctx.sepc = pc; - ctx.guest_pc = pc; - ctx.gcsr_estat &= !CSR_ESTAT_EXC_MASK; -+ if let Some(count) = dbg_log_sparse(&DBG_BRANCH_EMULATION_COUNT) { -+ log::debug!( -+ "LoongArch guest branch emulation #{count}: old_pc={:#x}, new_pc={:#x}, old_sepc={:#x}, host_era={:#x}, host_estat={:#x}", -+ old_pc, pc, old_sepc, ctx.host_era, ctx.host_estat, -+ ); -+ } - } - - fn emulate_cpucfg(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { -@@ -488,6 +538,10 @@ - emulate_guest_csr(ctx, rd, rj, csr); - advance_guest_pc(ctx); - if csr == CSR_CRMD && ctx.gcsr_crmd & CSR_CRMD_IE != 0 && ctx.gcsr_estat & TIMER_BIT != 0 { -+ log::debug!( -+ "LoongArch guest CRMD enables pending timer: pc={:#x}, gcrmd={:#x}, gecfg={:#x}, gestat={:#x}", -+ get_guest_pc(ctx), ctx.gcsr_crmd, ctx.gcsr_ectl, ctx.gcsr_estat, -+ ); - forward_timer_interrupt(ctx); - } - AxVCpuExitReason::Nothing -@@ -531,7 +585,10 @@ - CSR_STLBPS => ctx.gcsr_stlbps, - CSR_TCFG | CSR_TVAL | CSR_TICLR => read_host_timer_csr(csr), - CSR_SAVE0..=CSR_SAVE15 => read_guest_save_csr(ctx, csr), -- _ => 0, -+ _ => { -+ log::debug!("LoongArch GSPR csrrd emulation: csr={:#x}", csr); -+ 0 -+ }, - } - } - -@@ -552,7 +609,10 @@ - CSR_STLBPS => ctx.gcsr_stlbps = value, - CSR_TCFG | CSR_TVAL | CSR_TICLR => emulate_timer_write(ctx, csr, value), - CSR_SAVE0..=CSR_SAVE15 => write_guest_save_csr(ctx, csr, value), -- _ => {} -+ _ => log::debug!( -+ "LoongArch GSPR csr write emulation ignored: csr={:#x}, value={:#x}", -+ csr, value, -+ ) - } - } - -@@ -606,6 +666,12 @@ - /// when it fires the IRQ handler injects the interrupt into the guest ESTAT. - fn emulate_timer_write(ctx: &mut LoongArchContextFrame, csr: usize, value: usize) { - write_host_timer_csr(csr, value); -+ if let Some(count) = dbg_log_sparse(&DBG_TIMER_WRITE_COUNT) { -+ log::debug!( -+ "LoongArch guest timer CSR write #{count}: csr={:#x}, value={:#x}, pc={:#x}, gcrmd={:#x}, gecfg={:#x}, gestat={:#x}, host_tcfg={:#x}, host_tval={:#x}", -+ csr, value, get_guest_pc(ctx), ctx.gcsr_crmd, ctx.gcsr_ectl, ctx.gcsr_estat, read_host_timer_csr(CSR_TCFG), read_host_timer_csr(CSR_TVAL), -+ ); -+ } - if csr == CSR_TICLR && (value & CSR_TICLR_TI) != 0 { - ctx.gcsr_estat &= !TIMER_BIT; - ack_host_timer_interrupt(); -@@ -639,12 +705,22 @@ - } - - fn emulate_cacop(ctx: &mut LoongArchContextFrame, _ins: usize) -> AxVCpuExitReason { -+ log::debug!( -+ "LoongArch GSPR cacop emulation skipped at guest_pc={:#x}", -+ get_guest_pc(ctx), -+ ); - advance_guest_pc(ctx); - AxVCpuExitReason::Nothing - } - - fn emulate_idle(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { -- let _ = ins; -+ let level = extract_field(ins, 0, 15); -+ if let Some(count) = dbg_log_sparse(&DBG_IDLE_EXIT_COUNT) { -+ log::debug!( -+ "LoongArch guest idle request #{count}: level={:#x}, pc={:#x}, gcrmd={:#x}, gecfg={:#x}, gestat={:#x}, host_tcfg={:#x}, host_tval={:#x}", -+ level, get_guest_pc(ctx), ctx.gcsr_crmd, ctx.gcsr_ectl, ctx.gcsr_estat, read_host_timer_csr(CSR_TCFG), read_host_timer_csr(CSR_TVAL), -+ ); -+ } - advance_guest_pc(ctx); - AxVCpuExitReason::Idle - } -@@ -687,6 +763,12 @@ - let rj = extract_field(ins, 5, 5); - let rj_value = ctx.x[rj]; - let rd_value = ctx.x[rd]; -+ if let Some(count) = dbg_log_sparse(&DBG_IOCSR_EMULATION_COUNT) { -+ log::debug!( -+ "LoongArch IOCSR emulation #{count}: pc={:#x}, ins={:#x}, ty={}, rd={}, rd_value={:#x}, rj={}, rj_value={:#x}, host_estat={:#x}, host_badi={:#x}", -+ get_guest_pc(ctx), ins, ty, rd, rd_value, rj, rj_value, ctx.host_estat, ctx.host_badi, -+ ); -+ } - - if ty <= 3 { - if let Some(value) = read_guest_iocsr_ipi(rj_value) { -@@ -1227,7 +1309,7 @@ - ins: u32, - ) -> Option { - let ins = ins as usize; -- emulate_guest_pointer_access(ctx, ins) -+ let result = emulate_guest_pointer_access(ctx, ins) - .or_else(|| emulate_guest_regular_memory_access(ctx, ins)) - .or_else(|| emulate_guest_ll_sc(ctx, ins)) - .or_else(|| emulate_guest_logical_imm(ctx, ins)) -@@ -1246,7 +1328,14 @@ - .or_else(|| emulate_guest_alu_reg(ctx, ins)) - .or_else(|| emulate_guest_compact_branch(ctx, ins)) - .or_else(|| emulate_guest_branch(ctx, ins)) -- .or_else(|| try_emulate_gspr(ctx, ins)) -+ .or_else(|| try_emulate_gspr(ctx, ins)); -+ if let Some(count) = dbg_log_sparse(&DBG_FETCHED_INSTRUCTION_COUNT) { -+ log::debug!( -+ "LoongArch fetched instruction emulation #{count}: pc={:#x}, sepc={:#x}, gcsr_era={:#x}, host_era={:#x}, host_badi={:#x}, ins={:#x}, result={:?}", -+ get_guest_pc(ctx), ctx.sepc, ctx.gcsr_era, ctx.host_era, ctx.host_badi, ins, result, -+ ); -+ } -+ result - } - - fn try_emulate_gspr(ctx: &mut LoongArchContextFrame, ins: usize) -> Option { -@@ -1287,12 +1376,22 @@ - - fn emulate_gspr(ctx: &mut LoongArchContextFrame) -> AxVCpuExitReason { - let ins = get_guest_instruction(ctx); -+ if let Some(count) = dbg_log_sparse(&DBG_GSPR_EMULATION_COUNT) { -+ log::debug!( -+ "LoongArch GSPR emulation #{count}: pc={:#x}, ins={:#x}, host_estat={:#x}, host_badi={:#x}, guest_badi={:#x}, sepc={:#x}, gcsr_era={:#x}, host_era={:#x}", -+ get_guest_pc(ctx), ins, ctx.host_estat, ctx.host_badi, ctx.gcsr_badi, ctx.sepc, ctx.gcsr_era, ctx.host_era, -+ ); -+ } - if let Some(reason) = try_emulate_gspr(ctx, ins) { - return reason; - } - - let pc = get_guest_pc(ctx); - let fetch_gpa = direct_map_guest_addr_to_gpa(pc); -+ log::debug!( -+ "LoongArch GSPR BADI did not decode, fetching guest instruction: pc={:#x}, fetch_gpa={:#x}, badi={:#x}", -+ pc, fetch_gpa, ins, -+ ); - AxVCpuExitReason::GuestInstructionFetch { - addr: GuestPhysAddr::from(fetch_gpa), - } -@@ -1400,6 +1499,10 @@ - } else if is_qemu_invalid_badi(ins) { - let pc = get_guest_pc(ctx); - let fetch_gpa = direct_map_guest_addr_to_gpa(pc); -+ log::debug!( -+ "LoongArch INE BADI did not decode, fetching guest instruction: pc={:#x}, fetch_gpa={:#x}, badi={:#x}", -+ pc, fetch_gpa, ins, -+ ); - Ok(AxVCpuExitReason::GuestInstructionFetch { - addr: GuestPhysAddr::from(fetch_gpa), - }) -@@ -1441,6 +1544,10 @@ - // is never taken. Forward the timer interrupt into the guest by setting the - // timer bit in the guest ESTAT so that it is observed on the next VM entry. - if get_guest_interrupt_status(ctx) & TIMER_BIT != 0 { -+ log::debug!( -+ "LoongArch pending timer after sync: result={:?}, pc={:#x}, host_estat={:#x}, gestat={:#x}", -+ result, get_guest_pc(ctx), ctx.host_estat, ctx.gcsr_estat, -+ ); - forward_timer_interrupt(ctx); - } - result -@@ -1451,6 +1558,12 @@ - let is = guest_is; - - if let Some(vector) = decode_interrupt_vector(is) { -+ if let Some(count) = dbg_log_sparse(&DBG_IRQ_EXIT_COUNT) { -+ log::debug!( -+ "LoongArch irq exit #{count}: vector={}, guest_is={:#x}, host_estat={:#x}, pc={:#x}, gcrmd={:#x}, gecfg={:#x}, gestat={:#x}", -+ vector, guest_is, ctx.host_estat, get_guest_pc(ctx), ctx.gcsr_crmd, ctx.gcsr_ectl, ctx.gcsr_estat, -+ ); -+ } - // Inject the timer interrupt into the guest by setting the timer bit - // in the guest ESTAT. On the next VM entry RESTORE_GUEST_REGS will - // write this to GCSR ESTAT, so the guest sees the interrupt. ---- a/components/loongarch_vcpu/src/vcpu.rs -+++ b/components/loongarch_vcpu/src/vcpu.rs -@@ -182,6 +182,7 @@ - fn run(&mut self) -> AxResult { - #[cfg(target_arch = "loongarch64")] - { -+ log::debug!("LoongArch guest entry context:\n{}", self.ctx); - self.ctx.guest_pc = self.ctx.sepc; - let exit_reason = unsafe { - save_host_sp(); diff --git a/os/axvisor/doc/loongarch/rootfs-virtio-blk.md b/os/axvisor/doc/loongarch/rootfs-virtio-blk.md deleted file mode 100644 index c39aa292bb..0000000000 --- a/os/axvisor/doc/loongarch/rootfs-virtio-blk.md +++ /dev/null @@ -1,68 +0,0 @@ -# LoongArch Rootfs And Virtio Block - -本文记录 LoongArch Linux guest 在 QEMU quick-start 中使用 virtio-blk 磁盘 rootfs 的方式。 - -## 当前方式 - -当前 LoongArch Linux quick-start 只支持 virtio-blk rootfs。VM 配置使用： - -```toml -dtb_path = "/guest/linux/linux-rootfs-smp1.dtb" -cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw init=/init console=ttyS0 ..." -``` - -启动路径是： - -```text -Axvisor 加载 LoongArch Linux kernel 和 DTB - -> setup_bootinfo 构造 LoongArch Linux bootinfo - -> QEMU 暴露 virtio-blk rootfs 磁盘 - -> Linux 枚举 virtio-blk 并挂载 /dev/vda - -> 执行 rootfs 中的 /init -``` - -这条路径依赖 guest 侧 virtio-blk 设备链路，quick-start 不再准备 initramfs 配置。 - -## Rootfs 设备链路 - -典型 cmdline 是： - -```text -root=/dev/vda rw console=ttyS0 -``` - -guest 需要走完整设备链路： - -```text -Linux virtio-blk driver - -> PCI/virtio device discovery - -> virtqueue setup - -> disk I/O - -> device interrupt - -> hypervisor injects guest IRQ - -> guest handles completion - -> mount /dev/vda -``` - -当前 LoongArch quick-start 已经把这条链路作为 Linux guest 的唯一启动路径。 - -## Initramfs 状态 - -initramfs 曾用于早期 bring-up，用来绕开： - -- guest PCI 枚举； -- virtio-blk device discovery； -- virtqueue I/O； -- virtio-blk 完成中断； -- 外部设备中断注入 guest； -- guest idle 后等待设备中断唤醒。 - -现在 quick-start 已经切换到 rootfs，`--linux` 和 `--linux-rootfs` 都使用 `configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml`。仓库里的通用 ramdisk/initrd 加载逻辑仍可被其他架构或其他配置使用，但 LoongArch QEMU quick-start 不再维护 initramfs 作为启动模式。 - -QEMU runtime 配置中挂载： - -```toml -"virtio-blk-pci,drive=disk0" -``` - -VM cmdline 使用 `root=/dev/vda`，因此 Linux guest 启动依赖 virtio-blk rootfs。 diff --git a/os/axvisor/doc/loongarch/stage2-tlb-refill.md b/os/axvisor/doc/loongarch/stage2-tlb-refill.md index 82aea6da0a..ded1cddf4c 100644 --- a/os/axvisor/doc/loongarch/stage2-tlb-refill.md +++ b/os/axvisor/doc/loongarch/stage2-tlb-refill.md @@ -1,37 +1,82 @@ # LoongArch Stage-2 TLB Refill -本文只记录 LoongArch stage-2 映射和 TLB refill 的特殊处理。 +本文记录 LoongArch LVZ 下 AxVisor 处理 guest stage-2 缺页和 TLB refill 的关键路径。 -## 当前实现 +## 背景 -通用 nested page fault 路径会先补二阶段页表映射。大多数架构在页表更新后，可以依赖硬件下一次访问重新 page walk。 +LoongArch guest 运行时，host 会把 stage-2 页表根写入 `CSR_PGDL/CSR_PGDH`，并把 +`CSR_TLBRENTRY` 指向 AxVisor 提供的 guest TLB refill 入口。 -LoongArch 当前额外实现了架构 hook： +正常路径是： -```rust -self.fill_stage2_tlb(gpa, hpa, access_flags); -Ok(true) +```text +guest 访问地址 + -> LVZ/stage-2 TLB miss + -> _guest_tlb_refill_vector 使用 lddir/ldpte 查 stage-2 页表 + -> 查到映射后 tlbfill + -> ertn 回 guest ``` -也就是在 nested page fault 已经解析出 `gpa -> hpa` 后，主动填充 LoongArch stage-2 TLB/refill 相关项。 +这条路径在汇编里完成，不需要每次 miss 都回到 Rust。 -## 为什么需要 +## 缺页路径 -当前 LoongArch LVZ/stage2 路径不能完全依赖“更新二阶段页表后硬件自动重新 page walk”这个假设。某些缺页路径上，如果只更新 `address_space` 里的二阶段页表，guest 再次进入后仍可能继续触发 TLB refill 或转换异常。 +如果 `_guest_tlb_refill_vector` 通过 `lddir/ldpte` 查不到 stage-2 映射，会进入 +VM exit。Rust 侧根据 `host_tlbrera` 判断这是 TLB refill 触发的 exit： -因此 LoongArch 需要在 VM exit 处理后主动补一条 stage-2 TLB entry，让 guest 能继续访问。 +```text +_guest_tlb_refill_vector + -> stage-2 PTE miss + -> vmexit_trampoline + -> handle_exception_sync() + -> AxVCpuExitReason::NestedPageFault + -> AxVM::handle_nested_page_fault() + -> address_space.handle_page_fault() +``` + +也就是说，LoongArch 当前没有在 Rust 侧手工写入某条 TLB entry。真正的补映射动作 +仍然发生在通用 `address_space.handle_page_fault()` 中；补完后，guest 再次进入时 +由 TLB refill 汇编重新 page walk 并 `tlbfill`。 + +## Guest Fault 与 Stage-2 Fault + +LoongArch Linux 自己也会产生 guest 虚拟地址缺页。AxVisor 需要区分两类情况： + +- guest 自己页表缺页：注入回 guest 的 TLB refill 或普通异常； +- stage-2 映射缺失：返回 `NestedPageFault`，由 AxVisor 补二阶段映射。 + +当前判断主要依赖： + +- guest 是否开启分页； +- fault 地址是否是 guest direct-map 地址； +- fault 地址是否落在已知 guest RAM/MMIO 范围； +- 是否来自 host TLB refill 入口。 + +这样可以避免把 Linux guest 自己应该处理的页表异常误当作 stage-2 缺页。 + +## 大页注意点 + +LoongArch stage-2 PTE 的物理地址位域不能混入软件 level 标记。当前实现只用 +`GH` 位表示 huge page： + +```text +is_huge == true -> set GH +physical address -> only kept in PHYS_ADDR_MASK +``` + +不要把 page-table level 写入 PTE 物理地址位域，否则 `lddir/ldpte` 硬件遍历时 +会读到被污染的物理地址，进而导致异常或反复缺页。 ## 与其他架构区别 -- x86 EPT：通常由硬件 EPT walker 根据更新后的 EPT 继续翻译。 -- ARM Stage-2：通常由硬件 stage-2 walker 继续翻译。 -- RISC-V G-stage：通常由硬件 G-stage walker 继续翻译。 -- LoongArch：当前实现需要在部分路径上手动填充 stage-2 TLB/refill 项。 +- x86 EPT、ARM Stage-2、RISC-V G-stage 通常直接依赖硬件 walker。 +- LoongArch 当前需要显式安装 guest TLB refill 入口，并在该入口中执行 + `lddir/ldpte/tlbfill`。 +- stage-2 miss 仍走 AxVisor 的通用 nested page fault 补映射逻辑。 ## 后续工作 -1. 确认 READ/WRITE/EXECUTE 权限都能正确填充。 -2. 确认 huge page level 软件标记位不会污染物理地址。 -3. 确认 guest direct-map VA 到 GPA 的转换覆盖 Linux 常见地址区间。 -4. 确认映射权限变化或解除映射时是否需要失效旧 TLB 项。 -5. 用 Linux boot、initramfs 访问、用户态执行、设备 MMIO 访问分别验证。 +1. 继续验证 READ/WRITE/EXECUTE fault 的权限判断。 +2. 覆盖更多 guest direct-map VA 到 GPA 的转换场景。 +3. 确认映射权限变化或解除映射时的 TLB 失效策略。 +4. 用 Linux boot、rootfs I/O、用户态执行、设备 MMIO 分别验证。 From 12ee1b79266c8fba9f631e505876661a31263102 Mon Sep 17 00:00:00 2001 From: szy Date: Fri, 12 Jun 2026 13:09:54 +0800 Subject: [PATCH 18/50] feat(axvisor): dyn to shell --- .../someboot/src/arch/loongarch64/console.rs | 37 ++++++++++++++++++- os/arceos/modules/axhal/src/lib.rs | 4 +- .../configs/board/qemu-loongarch64.toml | 2 +- os/axvisor/configs/qemu/qemu-loongarch64.toml | 6 +-- platforms/axplat-dyn/src/irq.rs | 14 +++++++ ...ld-loongarch64-unknown-none-softfloat.toml | 4 +- .../normal/qemu/smoke/qemu-loongarch64.toml | 10 ++--- 7 files changed, 63 insertions(+), 14 deletions(-) diff --git a/components/someboot/src/arch/loongarch64/console.rs b/components/someboot/src/arch/loongarch64/console.rs index a43237d26e..97e077a9b4 100644 --- a/components/someboot/src/arch/loongarch64/console.rs +++ b/components/someboot/src/arch/loongarch64/console.rs @@ -1,3 +1,38 @@ pub struct Console; -impl crate::console::ArchConsoleOps for Console {} +const QEMU_VIRT_UART_PADDR: usize = 0x1fe0_01e0; +const QEMU_VIRT_UART_CLOCK_HZ: u32 = 100_000_000; +const QEMU_VIRT_UART_REG_WIDTH: usize = 1; + +impl crate::console::ArchConsoleOps for Console { + fn init() -> bool { + use core::ptr::NonNull; + + use some_serial::InterfaceRaw; + + let Some(base) = NonNull::new(crate::mem::_fixmap_io(QEMU_VIRT_UART_PADDR)) else { + return false; + }; + let mut uart = some_serial::ns16550::Ns16550::new_mmio( + base, + QEMU_VIRT_UART_CLOCK_HZ, + QEMU_VIRT_UART_REG_WIDTH, + ); + uart.open(); + + let Some(tx) = uart.take_tx() else { + return false; + }; + let Some(rx) = uart.take_rx() else { + return false; + }; + + crate::console::set_earlycon_sender(tx); + crate::console::set_earlycon_receiver(rx); + unsafe { + crate::console::DEBUG_BASE = QEMU_VIRT_UART_PADDR; + crate::console::DEBUG_IS_MMIO = true; + } + true + } +} diff --git a/os/arceos/modules/axhal/src/lib.rs b/os/arceos/modules/axhal/src/lib.rs index 0873978fc3..552de7f21d 100644 --- a/os/arceos/modules/axhal/src/lib.rs +++ b/os/arceos/modules/axhal/src/lib.rs @@ -56,12 +56,14 @@ pub mod irq; ax_hal_any_platform_feature ))] pub mod loongarch64_hv_irq { + const EIOINTC_IRQ: usize = 3; + pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize)) { ax_plat::irq::register_loongarch_virtual_irq_injector(injector); } pub fn enable_external_irq_line() { - crate::irq::set_enable(ax_config::devices::EIOINTC_IRQ, true); + crate::irq::set_enable(EIOINTC_IRQ, true); } pub fn register_guest_irq_route( diff --git a/os/axvisor/configs/board/qemu-loongarch64.toml b/os/axvisor/configs/board/qemu-loongarch64.toml index c4efdb343d..cccff7f8cc 100644 --- a/os/axvisor/configs/board/qemu-loongarch64.toml +++ b/os/axvisor/configs/board/qemu-loongarch64.toml @@ -5,6 +5,6 @@ features = [ ] log = "Info" max_cpu_num = 1 -plat_dyn = false +plat_dyn = true target = "loongarch64-unknown-none-softfloat" vm_configs = [] diff --git a/os/axvisor/configs/qemu/qemu-loongarch64.toml b/os/axvisor/configs/qemu/qemu-loongarch64.toml index c8dcfbad8e..0c3b4f4363 100644 --- a/os/axvisor/configs/qemu/qemu-loongarch64.toml +++ b/os/axvisor/configs/qemu/qemu-loongarch64.toml @@ -11,8 +11,6 @@ args = [ "-serial", "mon:stdio", "-no-reboot", - "-net", - "none", "-device", "virtio-blk-pci,drive=disk0", "-drive", @@ -20,5 +18,5 @@ args = [ ] fail_regex = [] success_regex = [] -to_bin = false -uefi = false +to_bin = true +uefi = true diff --git a/platforms/axplat-dyn/src/irq.rs b/platforms/axplat-dyn/src/irq.rs index 758fb67f63..c1939dd7fa 100644 --- a/platforms/axplat-dyn/src/irq.rs +++ b/platforms/axplat-dyn/src/irq.rs @@ -70,6 +70,20 @@ impl IrqIf for IrqIfImpl { } } +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +#[impl_plat_interface] +impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { + fn register_virtual_irq_injector(_injector: fn(usize, usize, usize)) {} + + fn register_guest_irq_route( + _physical_irq: usize, + _vm_id: usize, + _vcpu_id: usize, + _guest_vector: usize, + ) { + } +} + #[cfg(all(target_arch = "riscv64", feature = "hv"))] fn inject_virtual_irq(irq: usize) -> bool { let injector = VIRTUAL_IRQ_INJECTOR.load(Ordering::Acquire); diff --git a/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml b/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml index e0b23fe9f1..cccff7f8cc 100644 --- a/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml +++ b/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml @@ -5,6 +5,6 @@ features = [ ] log = "Info" max_cpu_num = 1 -plat_dyn = false +plat_dyn = true target = "loongarch64-unknown-none-softfloat" -vm_configs = ["os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml"] +vm_configs = [] diff --git a/test-suit/axvisor/normal/qemu/smoke/qemu-loongarch64.toml b/test-suit/axvisor/normal/qemu/smoke/qemu-loongarch64.toml index a5131ba48c..2f82ef8d3d 100644 --- a/test-suit/axvisor/normal/qemu/smoke/qemu-loongarch64.toml +++ b/test-suit/axvisor/normal/qemu/smoke/qemu-loongarch64.toml @@ -22,8 +22,8 @@ fail_regex = [ "(?i)login incorrect", "(?i)permission denied", ] -success_regex = ["(?m)^guest linux test pass!\\s*$"] -shell_prefix = "~ #" -shell_init_cmd = "pwd && echo 'guest linux test pass!'" -to_bin = false -uefi = false +success_regex = ["Welcome to AxVisor Shell!", "axvisor:\\$"] +shell_prefix = "axvisor:$" +shell_init_cmd = "" +to_bin = true +uefi = true From 9c9bda860e1459ad370355374909cb20158a32cd Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 15 Jun 2026 09:06:03 +0800 Subject: [PATCH 19/50] loongarch uefi ok --- components/someboot/build.rs | 2 + .../someboot/src/arch/loongarch64/head.rs | 2 +- .../someboot/src/arch/loongarch64/mod.rs | 1 + .../someboot/src/arch/loongarch64/trap.rs | 8 + components/someboot/src/efi_stub/mod.rs | 1 + drivers/rdrive/src/probe/acpi.rs | 16 +- os/arceos/api/arceos_posix_api/src/imp/io.rs | 5 +- .../api/arceos_posix_api/src/imp/task.rs | 1 + os/arceos/modules/axhal/src/lib.rs | 2 +- os/arceos/modules/axruntime/src/lang_items.rs | 3 + os/arceos/modules/axtask/src/run_queue.rs | 2 + .../qemu/loongarch64/linux-rootfs-smp1.dts | 184 --- .../qemu/loongarch64/linux-rootfs-smp1.toml | 33 +- os/axvisor/src/config.rs | 57 +- os/axvisor/src/fdt/create.rs | 28 +- os/axvisor/src/fdt/mod.rs | 76 +- os/axvisor/src/images/mod.rs | 443 +++++- os/axvisor/src/manager.rs | 49 +- .../ax-plat-loongarch64-qemu-virt/src/irq.rs | 7 +- platforms/ax-plat/src/irq.rs | 4 +- platforms/axplat-dyn/src/irq.rs | 118 +- platforms/axplat-dyn/src/mem.rs | 11 + platforms/axplat-dyn/src/power.rs | 1 + .../somehal/src/arch/loongarch64/eiointc.rs | 120 +- platforms/somehal/src/arch/loongarch64/mod.rs | 8 + .../somehal/src/arch/loongarch64/pch_pic.rs | 51 + scripts/axbuild/src/axvisor/rootfs.rs | 42 +- .../axaddrspace/src/npt/arch/loongarch64.rs | 11 +- virtualization/axdevice/src/device.rs | 71 +- virtualization/axdevice/src/fw_cfg.rs | 1223 +++++++++++++++++ virtualization/axdevice/src/lib.rs | 6 + .../axdevice/src/loongarch_pch_pic.rs | 407 ++++++ virtualization/axvcpu/src/arch_vcpu.rs | 10 + virtualization/axvm-types/src/lib.rs | 12 +- virtualization/axvm/src/arch.rs | 19 + virtualization/axvm/src/config.rs | 19 +- virtualization/axvm/src/lib.rs | 4 +- virtualization/axvm/src/manager.rs | 30 + virtualization/axvm/src/runtime/mod.rs | 10 +- virtualization/axvm/src/runtime/vcpus.rs | 474 ++++--- virtualization/axvmconfig/src/lib.rs | 8 +- virtualization/axvmconfig/src/test.rs | 13 +- .../loongarch_vcpu/src/context_frame.rs | 37 + virtualization/loongarch_vcpu/src/exception.S | 96 +- .../loongarch_vcpu/src/exception.rs | 857 +++++++++++- virtualization/loongarch_vcpu/src/host.rs | 3 + virtualization/loongarch_vcpu/src/lib.rs | 1 + virtualization/loongarch_vcpu/src/mmio.rs | 333 +++++ .../loongarch_vcpu/src/registers.rs | 29 +- virtualization/loongarch_vcpu/src/vcpu.rs | 331 ++++- 50 files changed, 4652 insertions(+), 627 deletions(-) delete mode 100644 os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.dts create mode 100644 virtualization/axdevice/src/fw_cfg.rs create mode 100644 virtualization/axdevice/src/loongarch_pch_pic.rs create mode 100644 virtualization/loongarch_vcpu/src/mmio.rs diff --git a/components/someboot/build.rs b/components/someboot/build.rs index 564c26c563..47627c37cd 100644 --- a/components/someboot/build.rs +++ b/components/someboot/build.rs @@ -115,6 +115,8 @@ impl Build { } fn prepare_loongarch64(&mut self) { + self.kernel_paddr = + env_u64("SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR").unwrap_or(0x8000_0000); self.kernel_vaddr = 0xffff_ffff_8000_0000; println!("cargo:rustc-cfg=efi"); diff --git a/components/someboot/src/arch/loongarch64/head.rs b/components/someboot/src/arch/loongarch64/head.rs index 3d1c146b07..9bdf11303e 100644 --- a/components/someboot/src/arch/loongarch64/head.rs +++ b/components/someboot/src/arch/loongarch64/head.rs @@ -48,7 +48,7 @@ pub unsafe extern "C" fn _head() { ".long _stext - _head", // BaseOfCode // Extra header fields - ".quad 0", // ImageBase + ".quad {phys_link_kaddr}", // ImageBase ".long PAGE_SIZE", // SectionAlignment (PECOFF_SEGMENT_ALIGN) ".long PECOFF_FILE_ALIGN", // FileAlignment (PECOFF_FILE_ALIGN) ".short 0", // MajorOperatingSystemVersion diff --git a/components/someboot/src/arch/loongarch64/mod.rs b/components/someboot/src/arch/loongarch64/mod.rs index e385b6bc95..9ec2e5fdae 100644 --- a/components/someboot/src/arch/loongarch64/mod.rs +++ b/components/someboot/src/arch/loongarch64/mod.rs @@ -141,6 +141,7 @@ impl ArchTrait for Arch { } fn shutdown() -> ! { + crate::console::_write_str("[someboot loongarch64] shutdown entered\n"); if efi_stub::is_uefi_available() { efi_stub::reset( efi_stub::ResetType::SHUTDOWN, diff --git a/components/someboot/src/arch/loongarch64/trap.rs b/components/someboot/src/arch/loongarch64/trap.rs index 9f6371b0d4..740a98b578 100644 --- a/components/someboot/src/arch/loongarch64/trap.rs +++ b/components/someboot/src/arch/loongarch64/trap.rs @@ -195,6 +195,7 @@ fn do_vint(_tf: &mut TrapFrame) { /// Page Fault 处理函数 (普通 TLB 异常: TLBL, TLBS, TLBI, TLBM, TLBNR, TLBNX, TLBPE) #[unsafe(no_mangle)] extern "C" fn do_page_fault(tf: &TrapFrame, write: usize, address: usize) -> ! { + crate::console::_write_str("[someboot trap] do_page_fault\n"); println!("do_page_fault called"); let estat = estat::read(); @@ -229,6 +230,7 @@ extern "C" fn do_page_fault(tf: &TrapFrame, write: usize, address: usize) -> ! { /// TLB Refill 使用独立的 CSR: TLBRERA, TLBRPRMD, TLBRBADV #[unsafe(no_mangle)] extern "C" fn do_tlb_refill(tf: &TrapFrame, address: usize) -> ! { + crate::console::_write_str("[someboot trap] do_tlb_refill\n"); println!("do_tlb_refill called"); panic_on_exception( @@ -663,6 +665,7 @@ global_asm!( /// 保留异常处理函数 #[unsafe(no_mangle)] extern "C" fn do_reserved_exception(tf: &TrapFrame) -> ! { + crate::console::_write_str("[someboot trap] do_reserved_exception\n"); println!("*** do_reserved_exception 被调用 ***"); let estat = estat::read(); let ecode = estat.ecode(); @@ -686,6 +689,7 @@ extern "C" fn do_reserved_exception(tf: &TrapFrame) -> ! { /// ADE: Address Error - Memory access (内存访问时地址错误) #[unsafe(no_mangle)] extern "C" fn do_address_error(tf: &TrapFrame, badv: usize) -> ! { + crate::console::_write_str("[someboot trap] do_address_error\n"); println!("\n*** do_address_error 被调用 ***"); println!("BADV (错误地址): {:#x}", badv); @@ -719,6 +723,10 @@ extern "C" fn do_address_error(tf: &TrapFrame, badv: usize) -> ! { } fn panic_on_exception(name: &str, tf: &TrapFrame, fmt: Arguments<'_>) -> ! { + crate::console::_print(format_args!( + "[someboot trap] panic_on_exception name={name} era={:#x} prmd={:#x} sp={:#x}\n", + tf.era, tf.prmd, tf.regs.sp + )); println!( " ============================================================\n{name} \ diff --git a/components/someboot/src/efi_stub/mod.rs b/components/someboot/src/efi_stub/mod.rs index 1041b0d389..f88ec85463 100644 --- a/components/someboot/src/efi_stub/mod.rs +++ b/components/someboot/src/efi_stub/mod.rs @@ -389,6 +389,7 @@ pub fn is_uefi_available() -> bool { #[cfg(target_arch = "loongarch64")] pub fn reset(reset_type: ResetType, status: Status, data: Option<&[u8]>) -> ! { + crate::console::_write_str("[someboot efi_stub] reset via UEFI\n"); info!("Resetting system via UEFI..."); uefi::runtime::reset(reset_type, status, data) } diff --git a/drivers/rdrive/src/probe/acpi.rs b/drivers/rdrive/src/probe/acpi.rs index fa0aae4d6a..6d77034897 100644 --- a/drivers/rdrive/src/probe/acpi.rs +++ b/drivers/rdrive/src/probe/acpi.rs @@ -1546,13 +1546,21 @@ fn read_loongarch_bio_pic_entry( } let entry = unsafe { (base.add(offset) as *const RawMadtBioPic).read_unaligned() }; + let id = entry.id; + let address = entry.address; + let size = entry.size; + let gsi_base = entry.gsi_base; + info!( + "LoongArch MADT BIO_PIC: id={}, address={:#x}, size={:#x}, gsi_base={}", + id, address, size, gsi_base + ); routing.add_pch_pic(AcpiPchPic { - id: entry.id, - address: entry.address, - mmio_size: entry.size, + id, + address, + mmio_size: size, gsi_count: LOONGARCH_PCH_PIC_GSI_COUNT, - gsi_base: u32::from(entry.gsi_base), + gsi_base: u32::from(gsi_base), }); } diff --git a/os/arceos/api/arceos_posix_api/src/imp/io.rs b/os/arceos/api/arceos_posix_api/src/imp/io.rs index 2147a4ff3d..9ffba42d6e 100644 --- a/os/arceos/api/arceos_posix_api/src/imp/io.rs +++ b/os/arceos/api/arceos_posix_api/src/imp/io.rs @@ -6,7 +6,7 @@ use ax_io::prelude::*; use crate::ctypes; #[cfg(feature = "fd")] -use crate::imp::fd_ops::get_file_like; +use crate::imp::fd_ops::{FileLike, get_file_like}; /// Read data from the file indicated by `fd`. /// @@ -38,6 +38,9 @@ fn write_impl(fd: c_int, buf: *const c_void, count: usize) -> LinuxResult c_int { /// Exit current task #[track_caller] pub fn sys_exit(exit_code: c_int) -> ! { + ax_hal::console::write_text_bytes(b"[ax-posix-api] sys_exit\n"); debug!("sys_exit <= {exit_code}"); #[cfg(feature = "multitask")] ax_task::exit(exit_code); diff --git a/os/arceos/modules/axhal/src/lib.rs b/os/arceos/modules/axhal/src/lib.rs index 552de7f21d..e580291399 100644 --- a/os/arceos/modules/axhal/src/lib.rs +++ b/os/arceos/modules/axhal/src/lib.rs @@ -58,7 +58,7 @@ pub mod irq; pub mod loongarch64_hv_irq { const EIOINTC_IRQ: usize = 3; - pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize)) { + pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { ax_plat::irq::register_loongarch_virtual_irq_injector(injector); } diff --git a/os/arceos/modules/axruntime/src/lang_items.rs b/os/arceos/modules/axruntime/src/lang_items.rs index b2b28c666e..782c114b43 100644 --- a/os/arceos/modules/axruntime/src/lang_items.rs +++ b/os/arceos/modules/axruntime/src/lang_items.rs @@ -35,7 +35,9 @@ fn panic_primary(info: &PanicInfo) -> ! { } fn panic_message(info: &PanicInfo) { + ax_hal::console::write_text_bytes(b"[axruntime panic] entering panic_message\n"); ax_println!("{}", info); + ax_hal::console::write_text_bytes(b"[axruntime panic] leaving panic_message\n"); } fn panic_backtrace() { @@ -49,6 +51,7 @@ fn should_print_panic_backtrace() -> bool { } fn panic_shutdown() -> ! { + ax_hal::console::write_text_bytes(b"[axruntime panic] system_off from panic_shutdown\n"); ax_hal::power::system_off() } diff --git a/os/arceos/modules/axtask/src/run_queue.rs b/os/arceos/modules/axtask/src/run_queue.rs index acb80c1db0..b62c61ce75 100644 --- a/os/arceos/modules/axtask/src/run_queue.rs +++ b/os/arceos/modules/axtask/src/run_queue.rs @@ -615,9 +615,11 @@ impl CurrentRunQueueRef<'_, G> { pub fn exit_current(&mut self, exit_code: i32) -> ! { let curr = &self.current_task; debug!("task exit: {}, exit_code={}", curr.id_name(), exit_code); + ax_hal::console::write_text_bytes(b"[axtask] exit_current\n"); assert!(curr.is_running(), "task is not running: {:?}", curr.state()); assert!(!curr.is_idle()); if curr.is_init() { + ax_hal::console::write_text_bytes(b"[axtask] init task exiting, calling system_off\n"); // Safety: it is called from `current_run_queue::().exit_current(exit_code)`, // which disabled IRQs and preemption. unsafe { diff --git a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.dts b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.dts deleted file mode 100644 index 7bbfe753b1..0000000000 --- a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.dts +++ /dev/null @@ -1,184 +0,0 @@ -/dts-v1/; - -/ { - #size-cells = <0x02>; - #address-cells = <0x02>; - compatible = "linux,dummy-loongson3"; - - platform-bus@16000000 { - interrupt-parent = <0x8003>; - ranges = <0x00 0x00 0x16000000 0x2000000>; - #address-cells = <0x01>; - #size-cells = <0x01>; - compatible = "qemu,platform\0simple-bus"; - }; - - poweroff { - value = <0x34>; - offset = <0x00>; - regmap = <0x8005>; - compatible = "syscon-poweroff"; - }; - - reboot { - value = <0x42>; - offset = <0x02>; - regmap = <0x8005>; - compatible = "syscon-reboot"; - }; - - ged@100e001c { - phandle = <0x8005>; - reg-io-width = <0x01>; - reg-shift = <0x00>; - reg = <0x00 0x100e001c 0x00 0x03>; - compatible = "syscon"; - }; - - rtc@100d0100 { - interrupt-parent = <0x8003>; - interrupts = <0x06 0x04>; - reg = <0x00 0x100d0100 0x00 0x100>; - compatible = "loongson,ls7a-rtc"; - }; - - serial@1fe001e0 { - interrupt-parent = <0x8003>; - interrupts = <0x02 0x04>; - clock-frequency = <0x5f5e100>; - reg = <0x00 0x1fe001e0 0x00 0x100>; - compatible = "ns16550a"; - }; - - serial@1fe002e0 { - status = "disabled"; - interrupt-parent = <0x8003>; - interrupts = <0x03 0x04>; - clock-frequency = <0x5f5e100>; - reg = <0x00 0x1fe002e0 0x00 0x100>; - compatible = "ns16550a"; - }; - - serial@1fe003e0 { - status = "disabled"; - interrupt-parent = <0x8003>; - interrupts = <0x04 0x04>; - clock-frequency = <0x5f5e100>; - reg = <0x00 0x1fe003e0 0x00 0x100>; - compatible = "ns16550a"; - }; - - serial@1fe004e0 { - status = "disabled"; - interrupt-parent = <0x8003>; - interrupts = <0x05 0x04>; - clock-frequency = <0x5f5e100>; - reg = <0x00 0x1fe004e0 0x00 0x100>; - compatible = "ns16550a"; - }; - - pcie@20000000 { - interrupt-map-mask = <0x1800 0x00 0x00 0x07>; - interrupt-map = <0x800 0x00 0x00 0x01 0x8003 0x11 0x04 - 0x800 0x00 0x00 0x02 0x8003 0x12 0x04 - 0x800 0x00 0x00 0x03 0x8003 0x13 0x04 - 0x800 0x00 0x00 0x04 0x8003 0x10 0x04>; - msi-map = <0x00 0x8004 0x00 0x10000>; - ranges = <0x1000000 0x00 0x4000 0x00 0x18004000 0x00 0xc000 0x2000000 0x00 0x40000000 0x00 0x40000000 0x00 0x40000000>; - reg = <0x00 0x20000000 0x00 0x8000000>; - dma-coherent; - bus-range = <0x00 0x7f>; - linux,pci-domain = <0x00>; - #interrupt-cells = <0x01>; - #size-cells = <0x02>; - #address-cells = <0x03>; - device_type = "pci"; - compatible = "pci-host-ecam-generic"; - }; - - msi@2ff00000 { - loongson,msi-num-vecs = <0xe0>; - loongson,msi-base-vec = <0x20>; - interrupt-parent = <0x8002>; - #address-cells = <0x00>; - #interrupt-cells = <0x01>; - #msi-cells = <0x01>; - msi-controller; - interrupt-controller; - reg = <0x00 0x2ff00000 0x00 0x08>; - compatible = "loongson,pch-msi-1.0"; - phandle = <0x8004>; - }; - - platic@10000000 { - loongson,pic-base-vec = <0x00>; - interrupt-parent = <0x8002>; - #address-cells = <0x00>; - #interrupt-cells = <0x02>; - interrupt-controller; - reg = <0x00 0x10000000 0x00 0x400>; - compatible = "loongson,pch-pic-1.0"; - phandle = <0x8003>; - }; - - eiointc@1400 { - reg = <0x00 0x1400 0x00 0x800>; - interrupts = <0x03>; - interrupt-parent = <0x8001>; - #address-cells = <0x00>; - #interrupt-cells = <0x01>; - interrupt-controller; - compatible = "loongson,ls2k2000-eiointc"; - phandle = <0x8002>; - }; - - cpuic { - #address-cells = <0x00>; - #interrupt-cells = <0x01>; - interrupt-controller; - compatible = "loongson,cpu-interrupt-controller"; - phandle = <0x8001>; - }; - - flash@1c000000 { - bank-width = <0x04>; - reg = <0x00 0x1c000000 0x00 0x1000000 0x00 0x1d000000 0x00 0x1000000>; - compatible = "cfi-flash"; - }; - - fw_cfg@1e020000 { - dma-coherent; - reg = <0x00 0x1e020000 0x00 0x18>; - compatible = "qemu,fw-cfg-mmio"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x00 0x00 0x00 0x0a000000>; - }; - - cpus { - #size-cells = <0x00>; - #address-cells = <0x01>; - - cpu-map { - socket0 { - core0 { - cpu = <0x8000>; - }; - }; - }; - - cpu@0 { - phandle = <0x8000>; - reg = <0x00>; - compatible = "loongarch,Loongson-3A5000"; - device_type = "cpu"; - }; - }; - - chosen { - bootargs = ""; - stdout-path = "/serial@1fe001e0"; - }; -}; diff --git a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml index cf7230645b..2f82d0360d 100644 --- a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml +++ b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml @@ -16,28 +16,28 @@ phys_cpu_ids = [0] # Vm kernel configs # [kernel] -# The entry point is replaced by the LoongArch ELF loader when vmlinux.elf is used. -entry_point = 0x0020_0000 +# UEFI guest starts from firmware; Linux is provided to firmware through fw_cfg. +entry_point = 0x1c00_0000 # The location of image: "memory" | "fs". image_location = "fs" # The file path of the kernel image. kernel_path = "/guest/linux/linux-qemu" # The ELF LOAD paddr is used by the LoongArch loader; this is a fallback for flat images. kernel_load_addr = 0x0020_0000 -# The file path of the device tree blob (DTB). -# When omitted, AxVisor generates a guest DTB from the host FDT. -# dtb_path = "/guest/linux/linux-rootfs-smp1.dtb" -# The load address of the device tree blob (DTB). -dtb_load_addr = 0x0010_0000 +# Boot Linux through guest UEFI/ACPI, matching the LoongArch QEMU virt platform. +enable_bios = true +boot_protocol = "uefi" +uefi_firmware_path = "/tmp/ostool/ovmf/loongarch64/code.fd" +bios_load_addr = 0x1c00_0000 # Kernel command line. Rootfs mode intentionally uses virtio-blk /dev/vda. -cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw console=ttyS0 earlycon=uart,mmio,0x1fe001e0 nokaslr loglevel=8 ignore_loglevel swiotlb=1024 initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" +cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw console=ttyS0,115200 earlycon=uart8250,mmio,0x1fe001e0,115200 nokaslr loglevel=8 ignore_loglevel swiotlb=1024 pci=nomsi initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" # Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`). # For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`, 2 means `MAP_RESERVED`. memory_regions = [ - [0x0008_0000, 0x0018_0000, 0x7, 2], # Low bootinfo/DTB RAM 512K-2M MAP_RESERVED - [0x0020_0000, 0x0fe0_0000, 0x7, 2], # Low System RAM 2-256M MAP_RESERVED - [0x8000_0000, 0x2400_0000, 0x7, 0], # High System RAM kept mapped but hidden from Linux memory map + [0x0000_0000, 0x1000_0000, 0x7, 2], + [0x8000_0000, 0x2400_0000, 0x7, 1], + [0x1c00_0000, 0x0100_0000, 0x7, 0], ] # @@ -49,12 +49,19 @@ interrupt_mode = "passthrough" # Pass-through devices. passthrough_devices = [ - ["/"], ] # Passthrough addresses. # Base-GPA Length. passthrough_addresses = [ + [0x100d_0100, 0x100], + [0x100e_0000, 0x1_0000], + [0x1d00_0000, 0x0100_0000], + [0x1fe0_01e0, 0x100], + [0x1800_4000, 0xc000], + [0x2000_0000, 0x0800_0000], + [0x2ff0_0000, 0x8], + [0x4000_0000, 0x4000_0000], ] # Devices that are not desired to be passed through to the guest @@ -63,4 +70,6 @@ excluded_devices = [ # Emu_devices. emu_devices = [ + ["fw_cfg", 0x1e02_0000, 0x18, 0, 0x3, []], + ["ls7a_pch_pic", 0x1000_0000, 0x1000, 0, 0x25, []], ] diff --git a/os/axvisor/src/config.rs b/os/axvisor/src/config.rs index 83098819c4..7f25465bc6 100644 --- a/os/axvisor/src/config.rs +++ b/os/axvisor/src/config.rs @@ -144,6 +144,19 @@ pub fn init_guest_vm(raw_cfg: &str) -> AxResult { any(target_arch = "x86_64", target_arch = "loongarch64") ))] let release_host_filesystem = vm_config_needs_host_filesystem_release(&vm_create_config); + #[cfg(all( + feature = "fs", + any(target_arch = "x86_64", target_arch = "loongarch64") + ))] + info!( + "VM[{}] host filesystem release check: image_location={:?}, passthrough_devices={}, \ + passthrough_addresses={}, required={}", + vm_create_config.base.id, + vm_create_config.kernel.image_location, + vm_create_config.devices.passthrough_devices.len(), + vm_create_config.devices.passthrough_addresses.len(), + release_host_filesystem + ); if let Some(linux) = super::images::get_image_header(&vm_create_config) { debug!( @@ -237,6 +250,8 @@ pub(crate) fn build_axvm_config(cfg: &AxVMCrateConfig) -> AxVMConfig { boot_args: [0; 3], #[cfg(target_arch = "loongarch64")] boot_stack_top: 0, + #[cfg(target_arch = "loongarch64")] + firmware_boot: cfg.kernel.effective_boot_protocol() == VMBootProtocol::Uefi, }, image_config: VMImageConfig { kernel_load_gpa: GuestPhysAddr::from(cfg.kernel.kernel_load_addr), @@ -280,9 +295,31 @@ fn configured_bios_load_gpa(cfg: &AxVMCrateConfig) -> Option { any(target_arch = "x86_64", target_arch = "loongarch64") ))] fn vm_config_needs_host_filesystem_release(config: &AxVMCrateConfig) -> bool { - config.kernel.image_location.as_deref() == Some("fs") - && (!config.devices.passthrough_devices.is_empty() - || !config.devices.passthrough_addresses.is_empty()) + let has_passthrough = !config.devices.passthrough_devices.is_empty() + || !config.devices.passthrough_addresses.is_empty(); + if !has_passthrough { + return false; + } + + if config.kernel.image_location.as_deref() == Some("fs") { + return true; + } + + #[cfg(target_arch = "loongarch64")] + { + let loongarch_uefi_rootfs_guest = config.kernel.effective_boot_protocol() + == VMBootProtocol::Uefi + && config.kernel.cmdline.as_deref().is_some_and(|cmdline| { + cmdline + .split_ascii_whitespace() + .any(|arg| arg == "root=/dev/vda") + }); + if loongarch_uefi_rootfs_guest { + return true; + } + } + + false } #[cfg(all( @@ -328,6 +365,13 @@ fn vm_alloc_memory_regions(vm_create_config: &AxVMCrateConfig, vm: &AxVMRef) -> }; for memory in &vm_create_config.kernel.memory_regions { + info!( + "VM[{}] allocating memory region: gpa={:#x}, size={:#x}, map_type={:?}", + vm.id(), + memory.gpa, + memory.size, + memory.map_type + ); match memory.map_type { VmMemMappingType::MapAlloc => { vm.alloc_memory_region(make_layout(memory)?, Some(GuestPhysAddr::from(memory.gpa))) @@ -361,6 +405,13 @@ fn vm_alloc_memory_regions(vm_create_config: &AxVMCrateConfig, vm: &AxVMRef) -> })?; } } + info!( + "VM[{}] memory region allocated: gpa={:#x}, size={:#x}, map_type={:?}", + vm.id(), + memory.gpa, + memory.size, + memory.map_type + ); } Ok(()) } diff --git a/os/axvisor/src/fdt/create.rs b/os/axvisor/src/fdt/create.rs index 4f913618c1..434a629c6b 100644 --- a/os/axvisor/src/fdt/create.rs +++ b/os/axvisor/src/fdt/create.rs @@ -590,6 +590,11 @@ pub fn update_fdt( vm: AxVMRef, crate_config: &AxVMCrateConfig, ) -> AxResult { + info!( + "Updating guest FDT for VM[{}], input size={:#x}", + vm.id(), + dtb_size + ); // Fix up the cached DTB against the runtime layout before boot. let fdt_bytes = unsafe { core::slice::from_raw_parts(fdt_src.as_ptr(), dtb_size) }; let fdt = Fdt::from_bytes(fdt_bytes).map_err(|e| { @@ -610,10 +615,21 @@ pub fn update_fdt( }) }) .transpose()?; + info!("Patching guest FDT runtime layout for VM[{}]", vm.id()); let new_fdt_bytes = patch_guest_fdt_for_runtime(&fdt, &vm.memory_regions(), crate_config, host_fdt.as_ref())?; // Recompute the DTB load address from the runtime memory layout. + info!( + "Patched guest FDT for VM[{}], output size={:#x}", + vm.id(), + new_fdt_bytes.len() + ); let dest_addr = calculate_dtb_load_addr(vm.clone(), new_fdt_bytes.len())?; + info!( + "Loading guest FDT for VM[{}] at {:#x}", + vm.id(), + dest_addr.as_usize() + ); load_vm_image_from_memory(&new_fdt_bytes, dest_addr, vm) } @@ -722,11 +738,15 @@ pub(crate) fn calculate_dtb_load_addr(vm: AxVMRef, fdt_size: usize) -> AxResult< })?; let dtb_addr = vm.with_config(|config| { - let dtb_addr = if let Some(addr) = config.image_config.dtb_load_gpa - && !main_memory.is_identical() - { + #[cfg(target_arch = "loongarch64")] + let use_configured_dtb_addr = config.image_config.dtb_load_gpa.is_some(); + #[cfg(not(target_arch = "loongarch64"))] + let use_configured_dtb_addr = + config.image_config.dtb_load_gpa.is_some() && !main_memory.is_identical(); + + let dtb_addr = if use_configured_dtb_addr { // If dtb_load_gpa is already set, use the original value - addr + config.image_config.dtb_load_gpa.unwrap() } else { // If dtb_load_gpa is None, calculate based on memory size and FDT size let main_memory_size = main_memory.size().min(512 * MB); diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index 0a77a5ef25..f973a05170 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -21,7 +21,7 @@ mod create; mod device; mod parser; mod print; -mod vm_fdt; +pub(crate) mod vm_fdt; use alloc::{collections::BTreeMap, format, vec::Vec}; @@ -40,7 +40,7 @@ use fdt_parser::Fdt; pub use parser::*; use axvm::config::AxVMConfig; -use axvmconfig::AxVMCrateConfig; +use axvmconfig::{AxVMCrateConfig, VMBootProtocol}; use crate::config::{get_vm_dtb_arc, vmcfg}; @@ -96,11 +96,65 @@ pub fn get_loongarch_guest_irq_routes(vm_id: usize) -> Vec AxResult { + const LOONGARCH_UEFI_FDT_BASE: usize = 0x0010_0000; + + info!( + "VM[{}] uses LoongArch UEFI boot protocol, keeping firmware DTB at {:#x}", + vm_config.id(), + LOONGARCH_UEFI_FDT_BASE + ); + vm_config.set_dtb_load_gpa(LOONGARCH_UEFI_FDT_BASE.into()); + vm_create_config.kernel.dtb_load_addr = Some(LOONGARCH_UEFI_FDT_BASE); + store_loongarch_guest_irq_routes(vm_config.id(), loongarch_qemu_uefi_irq_routes()); + Ok(()) +} + +#[cfg(target_arch = "loongarch64")] +fn loongarch_qemu_uefi_irq_routes() -> Vec { + const HOST_UART_IRQ: usize = 2; + const HOST_PCI_INTX_BASE: usize = 16; + const GUEST_UART_PCH_INPUT: usize = 2; + const GUEST_PCH_INTX_BASE: usize = 16; + + let mut routes = Vec::from([LoongArchGuestIrqRoute { + physical_irq: HOST_UART_IRQ, + guest_vector: GUEST_UART_PCH_INPUT, + }]); + routes.extend((0..4).map(|idx| LoongArchGuestIrqRoute { + physical_irq: HOST_PCI_INTX_BASE + idx, + guest_vector: GUEST_PCH_INTX_BASE + idx, + })); + routes +} + +#[cfg(not(target_arch = "loongarch64"))] +fn handle_uefi_fdt_operations( + vm_config: &mut AxVMConfig, + vm_create_config: &mut AxVMCrateConfig, +) -> AxResult { + info!( + "VM[{}] uses UEFI boot protocol, skipping guest DTB handling", + vm_config.id() + ); + vm_config.clear_dtb_load_gpa(); + vm_create_config.kernel.dtb_load_addr = None; + Ok(()) +} + /// Handle all FDT-related operations for guest architectures that boot with DTB. pub fn handle_fdt_operations( vm_config: &mut AxVMConfig, vm_create_config: &mut AxVMCrateConfig, ) -> AxResult { + if vm_create_config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { + return handle_uefi_fdt_operations(vm_config, vm_create_config); + } + let host_fdt_bytes = try_get_host_fdt(); if let Some(host_fdt_bytes) = host_fdt_bytes { @@ -153,6 +207,24 @@ pub fn handle_fdt_operations( "VM[{}] DTB not found in memory, skipping...", vm_config.id() ); + let unresolved_passthrough_devices = vm_config + .pass_through_devices() + .iter() + .filter(|device| device.length == 0) + .cloned() + .collect::>(); + if !unresolved_passthrough_devices.is_empty() { + warn!( + "VM[{}] clearing {} unresolved passthrough discovery device(s)", + vm_config.id(), + unresolved_passthrough_devices.len() + ); + for device in unresolved_passthrough_devices { + vm_config.remove_pass_through_device(device); + } + } + vm_config.clear_dtb_load_gpa(); + vm_create_config.kernel.dtb_load_addr = None; } Ok(()) } diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index fb50688674..e6837af342 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -12,18 +12,27 @@ // See the License for the specific language governing permissions and // limitations under the License. -use alloc::format; +use alloc::{boxed::Box, format, vec::Vec}; use ax_errno::{AxResult, ax_err, ax_err_type}; -use axvmconfig::AxVMCrateConfig; +#[cfg(any(target_arch = "x86_64", target_arch = "loongarch64"))] +use axvmconfig::EmulatedDeviceType; #[cfg(target_arch = "x86_64")] -use axvmconfig::{EmulatedDeviceType, VMBootProtocol, VmMemMappingType}; +use axvmconfig::VmMemMappingType; +use axvmconfig::{AxVMCrateConfig, VMBootProtocol}; use byte_unit::Byte; use axvm::{AxVMRef, GuestPhysAddr, VMMemoryRegion}; use crate::config::{get_vm_dtb_arc, vmcfg}; +#[cfg(target_arch = "loongarch64")] +#[derive(Clone, Copy, Debug)] +struct LoongArchUefiRamRegion { + base: u64, + size: u64, +} + mod linux; #[cfg(target_arch = "loongarch64")] mod loongarch_elf; @@ -168,6 +177,14 @@ impl ImageLoader { ); } + #[cfg(target_arch = "loongarch64")] + if self.loongarch_uefi_boot() { + self.load_loongarch_uefi_firmware_dtb()?; + self.add_loongarch_uefi_fw_cfg_from_memory(vm_imags.kernel, vm_imags.ramdisk)?; + self.load_boot_image_from_memory(vm_imags.bios)?; + return Ok(()); + } + self.load_kernel_from_memory(vm_imags.kernel)?; // Load Ramdisk image and record its size before regenerating the DTB. @@ -265,6 +282,16 @@ impl ImageLoader { let load_gpa = self .bios_load_gpa .ok_or_else(|| ax_err_type!(NotFound, "boot firmware load address is missing"))?; + if self.config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { + let flash_len = self + .config + .kernel + .memory_regions + .iter() + .find(|region| region.gpa == load_gpa.as_usize()) + .map_or(buffer.len(), |region| region.size); + fill_vm_region(load_gpa, flash_len, 0xff, self.vm.clone())?; + } load_vm_image_from_memory(buffer, load_gpa, self.vm.clone())?; #[cfg(target_arch = "x86_64")] if should_patch_x86_multiboot_info(&self.config) { @@ -273,7 +300,6 @@ impl ImageLoader { return Ok(()); } - #[cfg(target_arch = "x86_64")] if self.config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { let firmware_path = self.config.kernel.boot_firmware_path().ok_or_else(|| { ax_errno::ax_err_type!(NotFound, "UEFI firmware image path is missed") @@ -320,6 +346,107 @@ impl ImageLoader { Ok(()) } + #[cfg(target_arch = "loongarch64")] + fn loongarch_uefi_boot(&self) -> bool { + self.config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi + } + + #[cfg(target_arch = "loongarch64")] + fn add_loongarch_uefi_fw_cfg( + &self, + kernel: &'static [u8], + ramdisk: Option<&'static [u8]>, + ) -> AxResult { + let fw_cfg = self + .config + .devices + .emu_devices + .iter() + .find(|device| device.emu_type == EmulatedDeviceType::FwCfg) + .ok_or_else(|| { + ax_errno::ax_err_type!(NotFound, "LoongArch UEFI boot requires a fw_cfg device") + })?; + + self.vm.add_fw_cfg_device( + GuestPhysAddr::from(fw_cfg.base_gpa), + fw_cfg.length, + kernel, + ramdisk, + self.config.kernel.cmdline.as_deref(), + self.config.base.cpu_num as u16, + ) + } + + #[cfg(target_arch = "loongarch64")] + fn add_loongarch_uefi_fw_cfg_from_memory( + &self, + kernel: &'static [u8], + ramdisk: Option<&'static [u8]>, + ) -> AxResult { + info!( + "VM[{}] configuring LoongArch UEFI fw_cfg payloads from memory: kernel={} bytes, \ + ramdisk={:?}", + self.config.base.id, + kernel.len(), + ramdisk.map(|data| data.len()) + ); + self.add_loongarch_uefi_fw_cfg(kernel, ramdisk) + } + + #[cfg(target_arch = "loongarch64")] + fn load_loongarch_uefi_firmware_dtb(&self) -> AxResult { + const LOONGARCH_UEFI_FDT_BASE: usize = 0x0010_0000; + + let ram_regions = self.loongarch_uefi_ram_regions(); + let dtb = build_loongarch_uefi_firmware_dtb(&ram_regions)?; + info!( + "VM[{}] loading internally generated LoongArch UEFI firmware DTB: {} bytes at \ + {:#x}", + self.config.base.id, + dtb.len(), + LOONGARCH_UEFI_FDT_BASE + ); + self.vm.with_config(|config| { + config.set_dtb_load_gpa(GuestPhysAddr::from(LOONGARCH_UEFI_FDT_BASE)); + }); + load_vm_image_from_memory( + &dtb, + GuestPhysAddr::from(LOONGARCH_UEFI_FDT_BASE), + self.vm.clone(), + ) + } + + #[cfg(target_arch = "loongarch64")] + fn loongarch_uefi_ram_regions(&self) -> Vec { + let mut ram_regions = self + .vm + .memory_regions() + .into_iter() + .inspect(|region| { + info!( + "VM[{}] LoongArch UEFI firmware candidate RAM: gpa={:#x}, hpa={:#x}, size={:#x}", + self.config.base.id, + region.gpa.as_usize(), + region.host_paddr().as_usize(), + region.size() + ); + }) + .filter(|region| region.gpa.as_usize() < 0x1000_0000 || region.gpa.as_usize() >= 0x8000_0000) + .map(|region| LoongArchUefiRamRegion { + base: region.gpa.as_usize() as u64, + size: region.size() as u64, + }) + .filter(|region| region.size != 0) + .collect::>(); + ram_regions.sort_by_key(|region| region.base); + + info!( + "VM[{}] LoongArch UEFI firmware RAM regions: {:?}", + self.config.base.id, ram_regions + ); + ram_regions + } + fn load_kernel_from_memory(&self, kernel: &[u8]) -> AxResult { #[cfg(target_arch = "loongarch64")] if let Some(info) = loongarch_zboot::try_load_streamed_image(kernel, self.vm.clone())? { @@ -704,6 +831,264 @@ pub fn zero_vm_memory(load_addr: GuestPhysAddr, size: usize, vm: AxVMRef) -> AxR } } +fn fill_vm_region(load_addr: GuestPhysAddr, size: usize, byte: u8, vm: AxVMRef) -> AxResult { + let image_load_regions = vm.get_image_load_region(load_addr, size)?; + let mut filled_size = 0; + + for region in image_load_regions { + unsafe { + core::ptr::write_bytes(region.as_mut_ptr(), byte, region.len()); + } + axvm::clean_dcache_range((region.as_ptr() as usize).into(), region.len()); + filled_size += region.len(); + } + + if filled_size == size { + Ok(()) + } else { + ax_err!( + InvalidData, + format!("VM memory was only partially filled: {filled_size}/{size} bytes") + ) + } +} + +#[cfg(target_arch = "loongarch64")] +fn build_loongarch_uefi_firmware_dtb(ram_regions: &[LoongArchUefiRamRegion]) -> AxResult> { + use crate::fdt::vm_fdt::FdtWriter; + + const FALLBACK_RAM_REGIONS: [LoongArchUefiRamRegion; 2] = [ + LoongArchUefiRamRegion { + base: 0, + size: 0x1000_0000, + }, + LoongArchUefiRamRegion { + base: 0x8000_0000, + size: 0x2400_0000, + }, + ]; + + fn fdt_err(err: impl core::fmt::Debug) -> ax_errno::AxError { + ax_errno::ax_err_type!( + InvalidData, + format!("failed to build LoongArch UEFI firmware DTB: {err:?}") + ) + } + + let mut fdt = FdtWriter::new().map_err(fdt_err)?; + let root = fdt.begin_node("").map_err(fdt_err)?; + fdt.property_u32("#address-cells", 2).map_err(fdt_err)?; + fdt.property_u32("#size-cells", 2).map_err(fdt_err)?; + fdt.property_string("compatible", "linux,dummy-loongson3") + .map_err(fdt_err)?; + + let platform_bus = fdt.begin_node("platform-bus@16000000").map_err(fdt_err)?; + fdt.property_string_list( + "compatible", + vec!["qemu,platform".into(), "simple-bus".into()], + ) + .map_err(fdt_err)?; + fdt.property_u32("#address-cells", 1).map_err(fdt_err)?; + fdt.property_u32("#size-cells", 1).map_err(fdt_err)?; + fdt.property_array_u32("ranges", &[0, 0, 0x1600_0000, 0x0200_0000]) + .map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", 0x8003) + .map_err(fdt_err)?; + fdt.end_node(platform_bus).map_err(fdt_err)?; + + let chosen = fdt.begin_node("chosen").map_err(fdt_err)?; + fdt.property_string("stdout-path", "/serial@1fe001e0") + .map_err(fdt_err)?; + fdt.end_node(chosen).map_err(fdt_err)?; + + let cpus = fdt.begin_node("cpus").map_err(fdt_err)?; + fdt.property_u32("#address-cells", 1).map_err(fdt_err)?; + fdt.property_u32("#size-cells", 0).map_err(fdt_err)?; + let cpu_map = fdt.begin_node("cpu-map").map_err(fdt_err)?; + let socket0 = fdt.begin_node("socket0").map_err(fdt_err)?; + let core0 = fdt.begin_node("core0").map_err(fdt_err)?; + fdt.property_u32("cpu", 0x8000).map_err(fdt_err)?; + fdt.end_node(core0).map_err(fdt_err)?; + fdt.end_node(socket0).map_err(fdt_err)?; + fdt.end_node(cpu_map).map_err(fdt_err)?; + let cpu = fdt.begin_node("cpu@0").map_err(fdt_err)?; + fdt.property_string("device_type", "cpu").map_err(fdt_err)?; + fdt.property_string("compatible", "loongarch,Loongson-3A5000") + .map_err(fdt_err)?; + fdt.property_u32("reg", 0).map_err(fdt_err)?; + fdt.property_phandle(0x8000).map_err(fdt_err)?; + fdt.end_node(cpu).map_err(fdt_err)?; + fdt.end_node(cpus).map_err(fdt_err)?; + + let ram_regions = if ram_regions.is_empty() { + &FALLBACK_RAM_REGIONS + } else { + ram_regions + }; + for region in ram_regions { + let memory = fdt + .begin_node(&format!("memory@{:x}", region.base)) + .map_err(fdt_err)?; + fdt.property_string("device_type", "memory") + .map_err(fdt_err)?; + fdt.property_array_u32( + "reg", + &[ + (region.base >> 32) as u32, + region.base as u32, + (region.size >> 32) as u32, + region.size as u32, + ], + ) + .map_err(fdt_err)?; + fdt.end_node(memory).map_err(fdt_err)?; + } + + let cpuic = fdt.begin_node("cpuic").map_err(fdt_err)?; + fdt.property_null("interrupt-controller").map_err(fdt_err)?; + fdt.property_u32("#interrupt-cells", 1).map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,cpu-interrupt-controller") + .map_err(fdt_err)?; + fdt.property_phandle(0x8001).map_err(fdt_err)?; + fdt.end_node(cpuic).map_err(fdt_err)?; + + let eiointc = fdt.begin_node("eiointc@1400").map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,ls2k2000-eiointc") + .map_err(fdt_err)?; + fdt.property_null("interrupt-controller").map_err(fdt_err)?; + fdt.property_u32("#interrupt-cells", 1).map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", 0x8001) + .map_err(fdt_err)?; + fdt.property_array_u32("interrupts", &[3]) + .map_err(fdt_err)?; + fdt.property_array_u32("reg", &[0, 0x0000_1400, 0, 0x800]) + .map_err(fdt_err)?; + fdt.property_phandle(0x8002).map_err(fdt_err)?; + fdt.end_node(eiointc).map_err(fdt_err)?; + + let pch_pic = fdt.begin_node("platic@10000000").map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,pch-pic-1.0") + .map_err(fdt_err)?; + fdt.property_null("interrupt-controller").map_err(fdt_err)?; + fdt.property_u32("#interrupt-cells", 2).map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", 0x8002) + .map_err(fdt_err)?; + fdt.property_array_u32("reg", &[0, 0x1000_0000, 0, 0x400]) + .map_err(fdt_err)?; + fdt.property_array_u32("loongson,pic-base-vec", &[0]) + .map_err(fdt_err)?; + fdt.property_phandle(0x8003).map_err(fdt_err)?; + fdt.end_node(pch_pic).map_err(fdt_err)?; + + let msi = fdt.begin_node("msi@2ff00000").map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,pch-msi-1.0") + .map_err(fdt_err)?; + fdt.property_null("interrupt-controller").map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", 0x8002) + .map_err(fdt_err)?; + fdt.property_array_u32("reg", &[0, 0x2ff0_0000, 0, 0x8]) + .map_err(fdt_err)?; + fdt.property_u32("loongson,msi-base-vec", 0x20) + .map_err(fdt_err)?; + fdt.property_u32("loongson,msi-num-vecs", 0xe0) + .map_err(fdt_err)?; + fdt.property_phandle(0x8004).map_err(fdt_err)?; + fdt.end_node(msi).map_err(fdt_err)?; + + let ged = fdt.begin_node("ged@100e001c").map_err(fdt_err)?; + fdt.property_string("compatible", "syscon") + .map_err(fdt_err)?; + fdt.property_array_u32("reg", &[0, 0x100e_001c, 0, 3]) + .map_err(fdt_err)?; + fdt.property_u32("reg-shift", 0).map_err(fdt_err)?; + fdt.property_u32("reg-io-width", 1).map_err(fdt_err)?; + fdt.property_phandle(0x8005).map_err(fdt_err)?; + fdt.end_node(ged).map_err(fdt_err)?; + + let poweroff = fdt.begin_node("poweroff").map_err(fdt_err)?; + fdt.property_string("compatible", "syscon-poweroff") + .map_err(fdt_err)?; + fdt.property_u32("regmap", 0x8005).map_err(fdt_err)?; + fdt.property_u32("offset", 0).map_err(fdt_err)?; + fdt.property_u32("value", 0x34).map_err(fdt_err)?; + fdt.end_node(poweroff).map_err(fdt_err)?; + + let reboot = fdt.begin_node("reboot").map_err(fdt_err)?; + fdt.property_string("compatible", "syscon-reboot") + .map_err(fdt_err)?; + fdt.property_u32("regmap", 0x8005).map_err(fdt_err)?; + fdt.property_u32("offset", 2).map_err(fdt_err)?; + fdt.property_u32("value", 0x42).map_err(fdt_err)?; + fdt.end_node(reboot).map_err(fdt_err)?; + + let rtc = fdt.begin_node("rtc@100d0100").map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,ls7a-rtc") + .map_err(fdt_err)?; + fdt.property_array_u32("reg", &[0, 0x100d_0100, 0, 0x100]) + .map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", 0x8003) + .map_err(fdt_err)?; + fdt.property_array_u32("interrupts", &[6, 4]) + .map_err(fdt_err)?; + fdt.end_node(rtc).map_err(fdt_err)?; + + for (index, addr) in [ + 0x1fe0_01e0u32, + 0x1fe0_02e0u32, + 0x1fe0_03e0u32, + 0x1fe0_04e0u32, + ] + .into_iter() + .enumerate() + { + let serial = fdt + .begin_node(&format!("serial@{addr:x}")) + .map_err(fdt_err)?; + fdt.property_string("compatible", "ns16550a") + .map_err(fdt_err)?; + fdt.property_array_u32("reg", &[0, addr, 0, 0x100]) + .map_err(fdt_err)?; + fdt.property_u32("clock-frequency", 100_000_000) + .map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", 0x8003) + .map_err(fdt_err)?; + fdt.property_array_u32("interrupts", &[(index as u32) + 2, 4]) + .map_err(fdt_err)?; + fdt.end_node(serial).map_err(fdt_err)?; + } + + let flash = fdt.begin_node("flash@1c000000").map_err(fdt_err)?; + fdt.property_string("compatible", "cfi-flash") + .map_err(fdt_err)?; + fdt.property_u32("bank-width", 4).map_err(fdt_err)?; + fdt.property_array_u32( + "reg", + &[ + 0, + 0x1c00_0000, + 0, + 0x0100_0000, + 0, + 0x1d00_0000, + 0, + 0x0100_0000, + ], + ) + .map_err(fdt_err)?; + fdt.end_node(flash).map_err(fdt_err)?; + + let fw_cfg = fdt.begin_node("fw_cfg@1e020000").map_err(fdt_err)?; + fdt.property_string("compatible", "qemu,fw-cfg-mmio") + .map_err(fdt_err)?; + fdt.property_array_u32("reg", &[0, 0x1e02_0000, 0, 0x18]) + .map_err(fdt_err)?; + fdt.property_null("dma-coherent").map_err(fdt_err)?; + fdt.end_node(fw_cfg).map_err(fdt_err)?; + + fdt.end_node(root).map_err(fdt_err)?; + fdt.finish().map_err(fdt_err) +} + #[cfg(feature = "fs")] pub mod fs { use alloc::vec::Vec; @@ -738,7 +1123,12 @@ pub mod fs { } // Load kernel image. #[cfg(target_arch = "loongarch64")] - loader.load_kernel_from_filesystem(&loader.config.kernel.kernel_path)?; + if loader.loongarch_uefi_boot() { + loader.load_loongarch_uefi_firmware_dtb()?; + loader.add_loongarch_uefi_fw_cfg_from_filesystem()?; + } else { + loader.load_kernel_from_filesystem(&loader.config.kernel.kernel_path)?; + } #[cfg(not(target_arch = "loongarch64"))] load_vm_image( &loader.config.kernel.kernel_path, @@ -762,7 +1152,19 @@ pub mod fs { } } #[cfg(not(target_arch = "x86_64"))] - load_vm_image(bios_path, bios_load_addr, loader.vm.clone())?; + { + if loader.config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { + let flash_len = loader + .config + .kernel + .memory_regions + .iter() + .find(|region| region.gpa == bios_load_addr.as_usize()) + .map_or_else(|| image_size(bios_path), |region| Ok(region.size))?; + fill_vm_region(bios_load_addr, flash_len, 0xff, loader.vm.clone())?; + } + load_vm_image(bios_path, bios_load_addr, loader.vm.clone())?; + } } else { return ax_err!(NotFound, "boot firmware load addr is missed"); } @@ -782,6 +1184,12 @@ pub mod fs { #[cfg(target_arch = "x86_64")] loader.load_x86_multiboot_info(x86_boot::DEFAULT_BIOS_IMAGE, bios_load_gpa)?; } + + #[cfg(target_arch = "loongarch64")] + if loader.loongarch_uefi_boot() { + return Ok(()); + } + // Load Ramdisk image if needed. if let Some(ramdisk_path) = &loader.config.kernel.ramdisk_path { loader.load_ramdisk_from_filesystem(ramdisk_path)?; @@ -813,6 +1221,29 @@ pub mod fs { Ok(()) } + #[cfg(target_arch = "loongarch64")] + impl ImageLoader { + fn add_loongarch_uefi_fw_cfg_from_filesystem(&self) -> AxResult { + let kernel = read_full_image(&self.config.kernel.kernel_path)?; + let kernel: &'static [u8] = Box::leak(kernel.into_boxed_slice()); + let ramdisk = if let Some(path) = &self.config.kernel.ramdisk_path { + let ramdisk = read_full_image(path)?; + Some(Box::leak(ramdisk.into_boxed_slice()) as &'static [u8]) + } else { + None + }; + + info!( + "VM[{}] configuring LoongArch UEFI fw_cfg payloads from filesystem: kernel={} \ + bytes, ramdisk={:?}", + self.config.base.id, + kernel.len(), + ramdisk.map(|data| data.len()) + ); + self.add_loongarch_uefi_fw_cfg(kernel, ramdisk) + } + } + #[cfg(target_arch = "x86_64")] impl ImageLoader { fn load_x86_linux_images_from_filesystem( diff --git a/os/axvisor/src/manager.rs b/os/axvisor/src/manager.rs index a1bb6dd5d8..e0189b0be7 100644 --- a/os/axvisor/src/manager.rs +++ b/os/axvisor/src/manager.rs @@ -227,11 +227,12 @@ impl AxvmManager { } #[cfg(target_arch = "loongarch64")] -fn inject_loongarch_platform_irq(vm_id: usize, vcpu_id: usize, vector: usize) { - if let Err(err) = axvm::inject_vm_vcpu_interrupt(vm_id, vcpu_id, vector) { +fn inject_loongarch_platform_irq(vm_id: usize, vcpu_id: usize, vector: usize, physical_irq: usize) { + if let Err(err) = axvm::inject_vm_vcpu_external_interrupt(vm_id, vcpu_id, vector, physical_irq) + { warn!( - "failed to inject LoongArch platform IRQ {vector:#x} for VM[{vm_id}] VCpu[{vcpu_id}]: \ - {err:?}" + "failed to inject LoongArch platform IRQ {vector:#x}/physical {physical_irq:#x} for \ + VM[{vm_id}] VCpu[{vcpu_id}]: {err:?}" ); } } @@ -240,30 +241,36 @@ fn inject_loongarch_platform_irq(vm_id: usize, vcpu_id: usize, vector: usize) { fn init_loongarch_passthrough_irq_routes() { let mut matched = 0usize; for vm in axvm::get_vm_list() { - let passthrough = vm.with_config(|cfg| !cfg.pass_through_devices().is_empty()); - if !passthrough { - continue; - } - - matched += 1; - let vcpu_id = 0usize; let routes = crate::fdt::get_loongarch_guest_irq_routes(vm.id()); - if routes.is_empty() { - warn!( - "VM[{}] has passthrough devices but no LoongArch guest IRQ route parsed from DTB", + if !routes.is_empty() { + matched += 1; + let vcpu_id = 0usize; + info!( + "Registering {} LoongArch passthrough IRQ route(s) for VM[{}]", + routes.len(), vm.id() ); + for route in routes { + ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::register_guest_irq_route( + route.physical_irq, + vm.id(), + vcpu_id, + route.guest_vector, + ); + } continue; } - for route in routes { - ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::register_guest_irq_route( - route.physical_irq, - vm.id(), - vcpu_id, - route.guest_vector, - ); + let passthrough = vm.with_config(|cfg| !cfg.pass_through_devices().is_empty()); + if !passthrough { + continue; } + + matched += 1; + warn!( + "VM[{}] has passthrough devices but no LoongArch guest IRQ route parsed from DTB", + vm.id() + ); } if matched > 1 { diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs index fed51d3cee..9ca6b7e2bd 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs @@ -54,7 +54,7 @@ fn make_ipi_send_value(cpu_id: usize, vector: u32, blocking: bool) -> u32 { /// Registers the virtual interrupt injector used by hypervisor builds. #[cfg(feature = "hypervisor")] -pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize)) { +pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); info!("LoongArch platform virtual IRQ injector registered"); } @@ -224,10 +224,11 @@ impl IrqIf for IrqIfImpl { // SAFETY: The injector is registered through // register_virtual_irq_injector as a valid function pointer. unsafe { - core::mem::transmute::<*mut (), fn(usize, usize, usize)>(injector)( + core::mem::transmute::<*mut (), fn(usize, usize, usize, usize)>(injector)( vm_id, vcpu_id, guest_vector, + ex_irq, ); } return Some(ex_irq); @@ -308,7 +309,7 @@ impl IrqIf for IrqIfImpl { #[cfg(feature = "hypervisor")] #[impl_plat_interface] impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { - fn register_virtual_irq_injector(injector: fn(usize, usize, usize)) { + fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { register_virtual_irq_injector(injector); } diff --git a/platforms/ax-plat/src/irq.rs b/platforms/ax-plat/src/irq.rs index 6db9f30975..0901e58399 100644 --- a/platforms/ax-plat/src/irq.rs +++ b/platforms/ax-plat/src/irq.rs @@ -275,7 +275,7 @@ pub trait IrqIf { #[def_plat_interface] pub trait LoongArchHvIrqIf { /// Registers the virtual interrupt injector used by hypervisor builds. - fn register_virtual_irq_injector(injector: fn(usize, usize, usize)); + fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)); /// Routes one physical EIOINTC/PCH-PIC IRQ to a guest CPU interrupt vector. fn register_guest_irq_route( @@ -288,7 +288,7 @@ pub trait LoongArchHvIrqIf { /// Registers the virtual interrupt injector used by LoongArch hypervisor builds. #[cfg(target_arch = "loongarch64")] -pub fn register_loongarch_virtual_irq_injector(injector: fn(usize, usize, usize)) { +pub fn register_loongarch_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { crate::__priv::call_interface!(LoongArchHvIrqIf::register_virtual_irq_injector(injector)); } diff --git a/platforms/axplat-dyn/src/irq.rs b/platforms/axplat-dyn/src/irq.rs index c1939dd7fa..87eca7483b 100644 --- a/platforms/axplat-dyn/src/irq.rs +++ b/platforms/axplat-dyn/src/irq.rs @@ -1,3 +1,5 @@ +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +use core::sync::atomic::{AtomicPtr, AtomicUsize, Ordering}; #[cfg(all(target_arch = "riscv64", feature = "hv"))] use core::sync::atomic::{AtomicPtr, Ordering}; @@ -9,6 +11,30 @@ const RISCV_INTERRUPT_BIT: usize = 1usize << (usize::BITS as usize - 1); #[cfg(all(target_arch = "riscv64", feature = "hv"))] static VIRTUAL_IRQ_INJECTOR: AtomicPtr<()> = AtomicPtr::new(core::ptr::null_mut()); +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +const LOONGARCH_MAX_IRQ_COUNT: usize = 256; +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +const IRQ_ROUTE_NONE: usize = 0; +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +const IRQ_TARGET_NONE: usize = usize::MAX; +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +const IRQ_TARGET_VM_SHIFT: usize = 32; +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +const LOONGARCH_IRQ_TRACE_LIMIT: usize = 80; + +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +static LOONGARCH_VIRTUAL_IRQ_INJECTOR: AtomicPtr<()> = AtomicPtr::new(core::ptr::null_mut()); +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +static LOONGARCH_GUEST_IRQ_ROUTES: [AtomicUsize; LOONGARCH_MAX_IRQ_COUNT] = + [const { AtomicUsize::new(IRQ_ROUTE_NONE) }; LOONGARCH_MAX_IRQ_COUNT]; +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +static LOONGARCH_GUEST_IRQ_TARGETS: [AtomicUsize; LOONGARCH_MAX_IRQ_COUNT] = + [const { AtomicUsize::new(IRQ_TARGET_NONE) }; LOONGARCH_MAX_IRQ_COUNT]; +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +static LOONGARCH_IRQ_MISS_LOGS: AtomicUsize = AtomicUsize::new(0); +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +static LOONGARCH_IRQ_INJECT_LOGS: AtomicUsize = AtomicUsize::new(0); + #[cfg(all(target_arch = "riscv64", feature = "hv"))] pub fn register_virtual_irq_injector(injector: fn(usize) -> bool) { VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); @@ -45,6 +71,11 @@ impl IrqIf for IrqIfImpl { let outcome = dispatch_irq(irq_num); if !outcome.handled { + #[cfg(all(target_arch = "loongarch64", feature = "hv"))] + if inject_loongarch_virtual_irq(irq_num) { + return Some(irq_num); + } + if outcome.called == 0 { warn!("Unhandled IRQ {irq:?}"); } else { @@ -73,14 +104,31 @@ impl IrqIf for IrqIfImpl { #[cfg(all(target_arch = "loongarch64", feature = "hv"))] #[impl_plat_interface] impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { - fn register_virtual_irq_injector(_injector: fn(usize, usize, usize)) {} + fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { + LOONGARCH_VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); + info!("LoongArch dynamic platform virtual IRQ injector registered"); + } fn register_guest_irq_route( - _physical_irq: usize, - _vm_id: usize, - _vcpu_id: usize, - _guest_vector: usize, + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, ) { + if physical_irq >= LOONGARCH_MAX_IRQ_COUNT { + warn!("LoongArch guest IRQ route ignored: physical IRQ {physical_irq} out of range"); + return; + } + + LOONGARCH_GUEST_IRQ_ROUTES[physical_irq].store(guest_vector + 1, Ordering::Release); + LOONGARCH_GUEST_IRQ_TARGETS[physical_irq] + .store((vm_id << IRQ_TARGET_VM_SHIFT) | vcpu_id, Ordering::Release); + somehal::irq::irq_set_enable(physical_irq.into(), true); + debug!( + "LoongArch dynamic guest IRQ route: physical_irq={}, target=VM[{}] VCpu[{}], \ + guest_vector={}", + physical_irq, vm_id, vcpu_id, guest_vector + ); } } @@ -93,3 +141,63 @@ fn inject_virtual_irq(irq: usize) -> bool { } unsafe { core::mem::transmute::<*mut (), fn(usize) -> bool>(injector)(irq) } } + +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +fn inject_loongarch_virtual_irq(physical_irq: usize) -> bool { + if physical_irq >= LOONGARCH_MAX_IRQ_COUNT { + if LOONGARCH_IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { + trace!( + "LoongArch guest IRQ route miss: physical_irq={} out of range", + physical_irq + ); + } + return false; + } + + let encoded_vector = LOONGARCH_GUEST_IRQ_ROUTES[physical_irq].load(Ordering::Acquire); + if encoded_vector == IRQ_ROUTE_NONE { + if LOONGARCH_IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { + trace!( + "LoongArch guest IRQ route miss: physical_irq={} has no route", + physical_irq + ); + } + return false; + } + + let encoded_target = LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); + if encoded_target == IRQ_TARGET_NONE { + if LOONGARCH_IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { + trace!( + "LoongArch guest IRQ route miss: physical_irq={} has no target", + physical_irq + ); + } + return false; + } + + let injector = LOONGARCH_VIRTUAL_IRQ_INJECTOR.load(Ordering::Acquire); + if injector.is_null() { + warn!("LoongArch virtual IRQ injector is not registered"); + return false; + } + + let guest_vector = encoded_vector - 1; + let vm_id = encoded_target >> IRQ_TARGET_VM_SHIFT; + let vcpu_id = encoded_target & ((1usize << IRQ_TARGET_VM_SHIFT) - 1); + if LOONGARCH_IRQ_INJECT_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { + trace!( + "LoongArch guest IRQ inject: physical_irq={} -> VM[{}] VCpu[{}] guest_vector={}", + physical_irq, vm_id, vcpu_id, guest_vector + ); + } + unsafe { + core::mem::transmute::<*mut (), fn(usize, usize, usize, usize)>(injector)( + vm_id, + vcpu_id, + guest_vector, + physical_irq, + ); + } + true +} diff --git a/platforms/axplat-dyn/src/mem.rs b/platforms/axplat-dyn/src/mem.rs index 6ed9205201..2e18682ead 100644 --- a/platforms/axplat-dyn/src/mem.rs +++ b/platforms/axplat-dyn/src/mem.rs @@ -21,6 +21,13 @@ const X86_RESERVED_RAM_RANGES: &[RawRange] = &[ (0, 0x20_0000), ]; +#[cfg(target_arch = "loongarch64")] +const LOONGARCH_RESERVED_RAM_RANGES: &[RawRange] = &[ + // Keep the low RAM identity-mappable for passthrough DMA used by the + // LoongArch QEMU virt machine. + (0, 0x1000_0000), +]; + struct MemIfImpl; fn push_non_overlapping(list: &mut Vec, range: RawRange) { @@ -78,6 +85,10 @@ impl MemIf for MemIfImpl { for &range in X86_RESERVED_RAM_RANGES { push_non_overlapping(&mut list, range); } + #[cfg(target_arch = "loongarch64")] + for &range in LOONGARCH_RESERVED_RAM_RANGES { + push_non_overlapping(&mut list, range); + } for r in somehal::mem::memory_map() { if matches!( r.memory_type, diff --git a/platforms/axplat-dyn/src/power.rs b/platforms/axplat-dyn/src/power.rs index fb16c8b01a..1c17de08e5 100644 --- a/platforms/axplat-dyn/src/power.rs +++ b/platforms/axplat-dyn/src/power.rs @@ -16,6 +16,7 @@ impl PowerIf for PowerImpl { /// Shutdown the whole system. fn system_off() -> ! { + ax_plat::console::write_text_bytes(b"[axplat-dyn] system_off\n"); somehal::power::shutdown() } diff --git a/platforms/somehal/src/arch/loongarch64/eiointc.rs b/platforms/somehal/src/arch/loongarch64/eiointc.rs index db63db2b51..f81935c65d 100644 --- a/platforms/somehal/src/arch/loongarch64/eiointc.rs +++ b/platforms/somehal/src/arch/loongarch64/eiointc.rs @@ -43,21 +43,27 @@ module_driver!( ); pub fn set_irq_enable(irq: usize, enable: bool) { - with_eiointc("setting EIOINTC IRQ enable", |intc| { - if enable { - intc.enable_irq(irq); - } else { - intc.disable_irq(irq); - } - }); + if enable { + enable_irq(irq, EIOINTC_VECTOR_COUNT); + } else { + disable_irq(irq, EIOINTC_VECTOR_COUNT); + } } pub fn claim_irq() -> Option { - with_eiointc("claiming EIOINTC IRQ", |intc| intc.claim_irq()).flatten() + claim_irq_from(EIOINTC_VECTOR_COUNT) } pub fn complete_irq(irq: usize) { - with_eiointc("completing EIOINTC IRQ", |intc| intc.complete_irq(irq)); + complete_irq_for(irq, EIOINTC_VECTOR_COUNT); +} + +pub fn debug_pending_summary() -> [u64; 4] { + let mut pending = [0; 4]; + for (reg, slot) in pending.iter_mut().enumerate() { + *slot = iocsr_read_d(EIOINTC_REG_ISR + reg * 8); + } + pending } fn probe_eiointc_fdt(probe: ProbeFdt<'_>) -> Result<(), OnProbeError> { @@ -79,26 +85,6 @@ fn register_eiointc(dev: PlatformDevice) -> Result<(), OnProbeError> { Ok(()) } -fn with_eiointc(op: &str, f: impl FnOnce(&mut EioIntc) -> R) -> Option { - if !rdrive::is_initialized() { - return None; - } - - for intc in rdrive::get_list::() { - let Ok(intc) = intc.downcast::() else { - continue; - }; - let Ok(mut intc) = intc.try_lock() else { - warn!("failed to lock Loongson EIOINTC when {op}"); - return None; - }; - return Some(f(&mut intc)); - } - - warn!("Loongson EIOINTC is not registered when {op}"); - None -} - struct EioIntc { vectors: usize, } @@ -132,55 +118,55 @@ impl EioIntc { iocsr_write_w(EIOINTC_REG_BOUNCE + i * 4, u32::MAX); } } +} - fn enable_irq(&mut self, irq: usize) { - if !self.contains_irq(irq, "enable") { - return; - } - - let (offset, bit) = eiointc_reg_bit(irq); - for base in [EIOINTC_REG_ENABLE, EIOINTC_REG_BOUNCE] { - let addr = base + offset; - iocsr_write_d(addr, iocsr_read_d(addr) | bit); - } +fn enable_irq(irq: usize, vectors: usize) { + if !contains_irq(irq, vectors, "enable") { + return; } - fn disable_irq(&mut self, irq: usize) { - if !self.contains_irq(irq, "disable") { - return; - } - - let (offset, bit) = eiointc_reg_bit(irq); - let addr = EIOINTC_REG_ENABLE + offset; - iocsr_write_d(addr, iocsr_read_d(addr) & !bit); + let (offset, bit) = eiointc_reg_bit(irq); + for base in [EIOINTC_REG_ENABLE, EIOINTC_REG_BOUNCE] { + let addr = base + offset; + iocsr_write_d(addr, iocsr_read_d(addr) | bit); } +} - fn claim_irq(&mut self) -> Option { - for i in 0..(self.vectors / VEC_COUNT_PER_REG) { - let flags = iocsr_read_d(EIOINTC_REG_ISR + i * 8); - if flags != 0 { - return Some(flags.trailing_zeros() as usize + VEC_COUNT_PER_REG * i); - } - } - None +fn disable_irq(irq: usize, vectors: usize) { + if !contains_irq(irq, vectors, "disable") { + return; } - fn complete_irq(&mut self, irq: usize) { - if !self.contains_irq(irq, "complete") { - return; + let (offset, bit) = eiointc_reg_bit(irq); + let addr = EIOINTC_REG_ENABLE + offset; + iocsr_write_d(addr, iocsr_read_d(addr) & !bit); +} + +fn claim_irq_from(vectors: usize) -> Option { + for i in 0..(vectors / VEC_COUNT_PER_REG) { + let flags = iocsr_read_d(EIOINTC_REG_ISR + i * 8); + if flags != 0 { + return Some(flags.trailing_zeros() as usize + VEC_COUNT_PER_REG * i); } + } + None +} - let (offset, bit) = eiointc_reg_bit(irq); - iocsr_write_d(EIOINTC_REG_ISR + offset, bit); +fn complete_irq_for(irq: usize, vectors: usize) { + if !contains_irq(irq, vectors, "complete") { + return; } - fn contains_irq(&self, irq: usize, op: &str) -> bool { - if irq < self.vectors { - true - } else { - warn!("skip {op} for out-of-range EIOINTC IRQ {irq}"); - false - } + let (offset, bit) = eiointc_reg_bit(irq); + iocsr_write_d(EIOINTC_REG_ISR + offset, bit); +} + +fn contains_irq(irq: usize, vectors: usize, op: &str) -> bool { + if irq < vectors { + true + } else { + warn!("skip {op} for out-of-range EIOINTC IRQ {irq}"); + false } } diff --git a/platforms/somehal/src/arch/loongarch64/mod.rs b/platforms/somehal/src/arch/loongarch64/mod.rs index f6940c6104..312109fa76 100644 --- a/platforms/somehal/src/arch/loongarch64/mod.rs +++ b/platforms/somehal/src/arch/loongarch64/mod.rs @@ -8,6 +8,14 @@ mod pch_pic; pub struct Plat; +pub fn debug_external_irq_snapshot(inputs: &[usize]) { + info!( + "LoongArch EIOINTC pending summary: {:?}", + eiointc::debug_pending_summary() + ); + pch_pic::debug_summary(inputs); +} + const IOCSR_IPI_SEND_CPU_SHIFT: u32 = 16; const IOCSR_IPI_SEND_BLOCKING: u32 = 1 << 31; diff --git a/platforms/somehal/src/arch/loongarch64/pch_pic.rs b/platforms/somehal/src/arch/loongarch64/pch_pic.rs index e0901d9d5f..1c8866f08d 100644 --- a/platforms/somehal/src/arch/loongarch64/pch_pic.rs +++ b/platforms/somehal/src/arch/loongarch64/pch_pic.rs @@ -15,7 +15,10 @@ const DEFAULT_PCH_PIC_SIZE: usize = 0x400; const PCH_PIC_ID: usize = 0x00; const PCH_PIC_MASK: usize = 0x20; +const PCH_PIC_HTMSI_EN: usize = 0x40; const PCH_PIC_EDGE: usize = 0x60; +const PCH_PIC_CLR: usize = 0x80; +const PCH_INT_ROUTE: usize = 0x100; const PCH_PIC_POL: usize = 0x3e0; const PCH_INT_HTVEC: usize = 0x200; @@ -49,6 +52,45 @@ pub fn set_irq_enable(irq: usize, enable: bool) { }); } +pub fn debug_summary(inputs: &[usize]) { + with_pch_pic("debugging PCH-PIC state", |pic| { + let mask0 = pic.read_w(PCH_PIC_MASK); + let mask1 = pic.read_w(PCH_PIC_MASK + 4); + let htmsi0 = pic.read_w(PCH_PIC_HTMSI_EN); + let htmsi1 = pic.read_w(PCH_PIC_HTMSI_EN + 4); + let edge0 = pic.read_w(PCH_PIC_EDGE); + let edge1 = pic.read_w(PCH_PIC_EDGE + 4); + let pol0 = pic.read_w(PCH_PIC_POL); + let pol1 = pic.read_w(PCH_PIC_POL + 4); + let clr0 = pic.read_w(PCH_PIC_CLR); + let clr1 = pic.read_w(PCH_PIC_CLR + 4); + info!( + "LoongArch PCH-PIC summary: base_vector={}, vector_count={}, mask=[{:#x},{:#x}], \ + htmsi=[{:#x},{:#x}], edge=[{:#x},{:#x}], pol=[{:#x},{:#x}], clr=[{:#x},{:#x}]", + pic.base_vector, + pic.vector_count, + mask0, + mask1, + htmsi0, + htmsi1, + edge0, + edge1, + pol0, + pol1, + clr0, + clr1 + ); + for &input in inputs { + if input >= pic.vector_count { + continue; + } + let route = pic.read_b(PCH_INT_ROUTE + input); + let htvec = pic.read_b(PCH_INT_HTVEC + input); + info!("LoongArch PCH-PIC input {input}: route={route:#x}, htvec={htvec:#x}"); + } + }); +} + fn probe_pch_pic_fdt(probe: ProbeFdt<'_>) -> Result<(), OnProbeError> { let (info, dev) = probe.into_parts(); let reg = info @@ -250,6 +292,10 @@ impl PchPic { self.mmio.read(offset) } + fn read_b(&self, offset: usize) -> u8 { + self.mmio.read(offset) + } + fn write_w(&self, offset: usize, value: u32) { self.mmio.write(offset, value); } @@ -279,6 +325,11 @@ impl Interface for PchPic { ); return self.base_vector.into(); }; + info!( + "LoongArch ACPI PCH-PIC route: gsi={}, input={}, vector={}, trigger={:?}, \ + polarity={:?}", + route.gsi, route.controller_input, vector, route.trigger, route.polarity + ); self.configure_input(usize::from(route.controller_input), route); vector.into() } diff --git a/scripts/axbuild/src/axvisor/rootfs.rs b/scripts/axbuild/src/axvisor/rootfs.rs index d611b7481e..1168b1e6c5 100644 --- a/scripts/axbuild/src/axvisor/rootfs.rs +++ b/scripts/axbuild/src/axvisor/rootfs.rs @@ -69,6 +69,7 @@ pub(crate) fn prepare_loongarch_linux_memory_vmconfigs( let rootfs_path = qemu_rootfs_path(request, workspace_root, explicit_rootfs)?; let out_dir = workspace_root.join("tmp/axbuild/axvisor/loongarch64"); let kernel_path = out_dir.join("linux-qemu"); + let firmware_path = loongarch_uefi_firmware_path(workspace_root); let mut prepared_vmconfigs = Vec::with_capacity(request.vmconfigs.len()); for vmconfig in &request.vmconfigs { @@ -102,12 +103,19 @@ pub(crate) fn prepare_loongarch_linux_memory_vmconfigs( ); fs::create_dir_all(&out_dir) .with_context(|| format!("failed to create {}", out_dir.display()))?; - let patched = content + let mut patched = content .replace("image_location = \"fs\"", "image_location = \"memory\"") .replace( "kernel_path = \"/guest/linux/linux-qemu\"", &format!("kernel_path = \"{}\"", kernel_path.display()), ); + if let Some(firmware_path) = &firmware_path { + patched = replace_toml_string_value( + &patched, + "uefi_firmware_path", + &firmware_path.display().to_string(), + ); + } fs::write(&prepared_vmconfig, patched) .with_context(|| format!("failed to write {}", prepared_vmconfig.display()))?; prepared_vmconfigs.push(prepared_vmconfig); @@ -117,15 +125,39 @@ pub(crate) fn prepare_loongarch_linux_memory_vmconfigs( Ok(()) } +fn loongarch_uefi_firmware_path(workspace_root: &Path) -> Option { + [ + PathBuf::from("/tmp/ostool/ovmf/loongarch64/code.fd"), + workspace_root.join("tmp/ostool/ovmf/loongarch64/code.fd"), + workspace_root.join("tmp/loongarch-uefi-stage1/assets/qemu-binary/QEMU_EFI.fd"), + ] + .into_iter() + .find(|path| path.exists()) +} + +fn replace_toml_string_value(content: &str, key: &str, value: &str) -> String { + let prefix = format!("{key} = "); + content + .lines() + .map(|line| { + if line.trim_start().starts_with(&prefix) { + let indent_len = line.len() - line.trim_start().len(); + format!("{}{}\"{}\"", &line[..indent_len], prefix, value) + } else { + line.to_string() + } + }) + .collect::>() + .join("\n") + + "\n" +} + fn ensure_loongarch_busybox_serial_init(rootfs_path: &Path, out_dir: &Path) -> anyhow::Result<()> { let Some(inittab) = rootfs::inject::read_text_file(rootfs_path, "/etc/inittab")? else { return Ok(()); }; let replacement_content = loongarch_busybox_inittab(); - if inittab == replacement_content - || (!inittab.contains("/sbin/openrc") && !inittab.contains("/etc/init.d/rcS")) - || rootfs_file_exists(rootfs_path, "/sbin/openrc")? - { + if inittab == replacement_content || rootfs_file_exists(rootfs_path, "/sbin/openrc")? { return Ok(()); } diff --git a/virtualization/axaddrspace/src/npt/arch/loongarch64.rs b/virtualization/axaddrspace/src/npt/arch/loongarch64.rs index 155f7441ac..60feca181f 100644 --- a/virtualization/axaddrspace/src/npt/arch/loongarch64.rs +++ b/virtualization/axaddrspace/src/npt/arch/loongarch64.rs @@ -12,7 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -use core::{arch::asm, fmt}; +use core::fmt; use ax_page_table_entry::{GenericPTE, MappingFlags}; use ax_page_table_multiarch::PagingMetaData; @@ -187,14 +187,7 @@ impl PagingMetaData for LoongArchPagingMetaDataL3 { type VirtAddr = GuestPhysAddr; fn flush_tlb(vaddr: Option) { - unsafe { - // `invtlb 0x6/0x7` may trap on current LVZ bring-up path before the - // guest TLB context is fully configured. Use a conservative global - // invalidation instead. VM creation/setup is not performance critical. - let _ = vaddr; - asm!("invtlb 0x0, $r0, $r0"); - asm!("dbar 0"); - } + let _ = vaddr; } } diff --git a/virtualization/axdevice/src/device.rs b/virtualization/axdevice/src/device.rs index d80a6994b7..05517ed066 100644 --- a/virtualization/axdevice/src/device.rs +++ b/virtualization/axdevice/src/device.rs @@ -35,9 +35,11 @@ use riscv_vplic::VPlicGlobal; #[cfg(target_arch = "x86_64")] use x86_vlapic::{EmulatedIoApic, EmulatedPit, EmulatedSerialPort, IoApicInterrupt}; +#[cfg(target_arch = "loongarch64")] +use crate::LoongArchPchPic; use crate::{ - AxVmDeviceConfig, DeviceBuildContext, DeviceBundle, DeviceFactoryRegistry, PollableDeviceOps, - range_alloc::RangeAllocator, + AxVmDeviceConfig, DeviceBuildContext, DeviceBundle, DeviceFactoryRegistry, FwCfg, + PollableDeviceOps, range_alloc::RangeAllocator, }; #[inline] @@ -80,6 +82,11 @@ pub struct AxVmDevices { /// x86 16550 serial port — kept for type-specific access. #[cfg(target_arch = "x86_64")] x86_serial: Option>, + /// LoongArch PCH-PIC — kept for type-specific access. + #[cfg(target_arch = "loongarch64")] + loongarch_pch_pic: Option>, + /// QEMU fw_cfg — kept for DMA access routing. + fw_cfg: Option>, /// IVC channel range allocator ivc_channel: Option>, } @@ -99,6 +106,9 @@ impl AxVmDevices { x86_pit: None, #[cfg(target_arch = "x86_64")] x86_serial: None, + #[cfg(target_arch = "loongarch64")] + loongarch_pch_pic: None, + fw_cfg: None, ivc_channel: None, } } @@ -156,6 +166,8 @@ impl AxVmDevices { | EmulatedDeviceType::GPPTRedistributor | EmulatedDeviceType::GPPTDistributor | EmulatedDeviceType::GPPTITS + | EmulatedDeviceType::FwCfg + | EmulatedDeviceType::LoongArchPchPic | EmulatedDeviceType::X86IoApic | EmulatedDeviceType::X86Pit | EmulatedDeviceType::PPPTGlobal @@ -403,6 +415,36 @@ impl AxVmDevices { ); } } + EmulatedDeviceType::LoongArchPchPic => { + #[cfg(target_arch = "loongarch64")] + { + let pch_pic = + Arc::new(LoongArchPchPic::new(config.base_gpa.into(), config.length)); + this.register(MmioDeviceAdapter::from_arc(pch_pic.clone()) + as Arc) + .map_err(|e| { + ax_err_type!( + InvalidInput, + format!("register loongarch pch-pic: {e:?}") + ) + })?; + this.loongarch_pch_pic = Some(pch_pic); + info!( + "LoongArch PCH-PIC initialized with base GPA {:#x} and length {:#x}", + config.base_gpa, config.length + ); + } + #[cfg(not(target_arch = "loongarch64"))] + { + warn!( + "emu type: {} is not supported on this platform", + config.emu_type + ); + } + } + EmulatedDeviceType::FwCfg => { + debug!("fw_cfg device is initialized when runtime image payloads are added"); + } EmulatedDeviceType::IVCChannel => { if this.ivc_channel.is_none() { // Initialize the IVC channel range allocator @@ -923,6 +965,31 @@ impl AxVmDevices { .is_some_and(|serial| serial.poll_irq()) } + /// Add a QEMU fw_cfg MMIO device to the device list. + pub fn add_fw_cfg_dev(&mut self, dev: Arc) -> AxResult { + self.register(MmioDeviceAdapter::from_arc(dev.clone()) + as Arc) + .map_err(|e| ax_err_type!(InvalidInput, format!("register fw_cfg: {e:?}")))?; + self.fw_cfg = Some(dev); + Ok(()) + } + + /// Returns the fw_cfg device that owns `addr`, if any. + pub fn fw_cfg_for_dma_addr(&self, addr: GuestPhysAddr) -> Option> { + self.fw_cfg + .as_ref() + .filter(|fw_cfg| fw_cfg.is_dma_address(addr)) + .cloned() + } + + /// Assert a LoongArch PCH-PIC input and return the routed EIOINTC vector. + #[cfg(target_arch = "loongarch64")] + pub fn loongarch_pch_pic_assert_irq(&self, irq: usize) -> Option> { + self.loongarch_pch_pic + .as_ref() + .map(|pch_pic| pch_pic.set_irq_level(irq, true)) + } + // ─── Find helpers ─────────────────────────────────────────────── /// Find specific MMIO device by ipa. diff --git a/virtualization/axdevice/src/fw_cfg.rs b/virtualization/axdevice/src/fw_cfg.rs new file mode 100644 index 0000000000..7553360af3 --- /dev/null +++ b/virtualization/axdevice/src/fw_cfg.rs @@ -0,0 +1,1223 @@ +use alloc::{format, vec, vec::Vec}; + +use ax_errno::{AxResult, ax_err}; +use ax_kspin::SpinNoIrq as Mutex; +use axdevice_base::{AccessWidth, BaseDeviceOps, EmuDeviceType}; +use axvm_types::{GuestPhysAddr, GuestPhysAddrRange}; + +const FW_CFG_SIGNATURE: u16 = 0x00; +const FW_CFG_ID: u16 = 0x01; +const FW_CFG_RAM_SIZE: u16 = 0x03; +const FW_CFG_NB_CPUS: u16 = 0x05; +const FW_CFG_MAX_CPUS: u16 = 0x0f; +const FW_CFG_KERNEL_SIZE: u16 = 0x08; +const FW_CFG_INITRD_SIZE: u16 = 0x0b; +const FW_CFG_KERNEL_DATA: u16 = 0x11; +const FW_CFG_INITRD_DATA: u16 = 0x12; +const FW_CFG_CMDLINE_SIZE: u16 = 0x14; +const FW_CFG_CMDLINE_DATA: u16 = 0x15; +const FW_CFG_FILE_DIR: u16 = 0x19; +const FW_CFG_FILE_FIRST: u16 = 0x20; +const FW_CFG_SMBIOS_TABLES: u16 = FW_CFG_FILE_FIRST + 1; +const FW_CFG_SMBIOS_ANCHOR: u16 = FW_CFG_FILE_FIRST + 2; +const FW_CFG_ACPI_TABLES: u16 = FW_CFG_FILE_FIRST + 3; +const FW_CFG_ACPI_RSDP: u16 = FW_CFG_FILE_FIRST + 4; +const FW_CFG_ACPI_LOADER: u16 = FW_CFG_FILE_FIRST + 5; +const FW_CFG_FILE_NAME_SIZE: usize = 56; + +const FW_CFG_VERSION: u32 = 0x01; +const FW_CFG_VERSION_DMA: u32 = 0x02; +const LOWMEM_BASE: u64 = 0; +const LOWMEM_LENGTH: u64 = 0x1000_0000; +const HIGHMEM_BASE: u64 = 0x8000_0000; +const HIGHMEM_LENGTH: u64 = 0x2400_0000; +const MEMMAP_RAM_TYPE: u32 = 1; +const VIRT_PCI_CFG_BASE: u64 = 0x2000_0000; +const VIRT_PCI_CFG_SIZE: u64 = 0x0800_0000; + +const FW_CFG_DATA_OFFSET: usize = 0x00; +const FW_CFG_SELECTOR_OFFSET: usize = 0x08; +const FW_CFG_DMA_OFFSET: usize = 0x10; + +const ACPI_TABLE_FILE: &str = "etc/acpi/tables"; +const ACPI_RSDP_FILE: &str = "etc/acpi/rsdp"; +const ACPI_LOADER_FILE: &str = "etc/table-loader"; +const ACPI_OEM_ID: &[u8; 6] = b"BOCHS "; +const ACPI_OEM_TABLE_ID: &[u8; 8] = b"BXPC "; + +const QEMU_LOADER_CMD_ALLOCATE: u32 = 1; +const QEMU_LOADER_CMD_ADD_POINTER: u32 = 2; +const QEMU_LOADER_CMD_ADD_CHECKSUM: u32 = 3; +const QEMU_LOADER_ALLOC_HIGH: u8 = 1; +const QEMU_LOADER_ALLOC_FSEG: u8 = 2; +const QEMU_LOADER_ENTRY_SIZE: usize = 128; + +const FW_CFG_DMA_CTL_ERROR: u32 = 0x01; +const FW_CFG_DMA_CTL_READ: u32 = 0x02; +const FW_CFG_DMA_CTL_SKIP: u32 = 0x04; +const FW_CFG_DMA_CTL_SELECT: u32 = 0x08; +const FW_CFG_DMA_CTL_WRITE: u32 = 0x10; +const FW_CFG_DMA_DESC_SIZE: usize = 16; + +#[derive(Clone, Copy, Debug)] +pub struct FwCfgRamRegion { + pub base: u64, + pub size: u64, +} + +#[derive(Clone, Copy, Debug)] +pub struct FwCfgPlatformConfig { + pub ram_regions: &'static [FwCfgRamRegion], + pub srat_regions: &'static [FwCfgRamRegion], +} + +impl Default for FwCfgPlatformConfig { + fn default() -> Self { + static DEFAULT_RAM_REGIONS: [FwCfgRamRegion; 2] = [ + FwCfgRamRegion { + base: LOWMEM_BASE, + size: LOWMEM_LENGTH, + }, + FwCfgRamRegion { + base: HIGHMEM_BASE, + size: HIGHMEM_LENGTH, + }, + ]; + + Self { + ram_regions: &DEFAULT_RAM_REGIONS, + srat_regions: &DEFAULT_RAM_REGIONS, + } + } +} + +struct FwCfgState { + selected: u16, + offset: usize, + dma_address: u64, +} + +/// Minimal QEMU-compatible fw_cfg MMIO device. +pub struct FwCfg { + base: GuestPhysAddr, + size: usize, + kernel: &'static [u8], + initrd: Option<&'static [u8]>, + cmdline: Vec, + file_dir: Vec, + memmap: Vec, + smbios_tables: Vec, + smbios_anchor: Vec, + acpi_tables: Vec, + acpi_rsdp: Vec, + acpi_loader: Vec, + cpu_num: u16, + ram_size: u64, + state: Mutex, +} + +impl FwCfg { + /// Create a fw_cfg device at `base`. + pub fn new( + base: GuestPhysAddr, + size: usize, + kernel: &'static [u8], + initrd: Option<&'static [u8]>, + cmdline: Option<&str>, + cpu_num: u16, + platform: FwCfgPlatformConfig, + ) -> Self { + let mut cmdline = cmdline.unwrap_or("").as_bytes().to_vec(); + if !cmdline.ends_with(&[0]) { + cmdline.push(0); + } + + let ram_size = platform + .ram_regions + .iter() + .fold(0u64, |acc, region| acc.saturating_add(region.size)); + let memmap = build_memmap(platform.ram_regions); + let smbios_tables = build_smbios_tables(); + let smbios_anchor = build_smbios_anchor(); + let acpi = build_acpi(cpu_num, platform.srat_regions); + let file_dir = build_file_dir(&[ + FwCfgFile { + name: "etc/memmap", + selector: FW_CFG_FILE_FIRST, + size: memmap.len() as u32, + }, + FwCfgFile { + name: "etc/smbios/smbios-anchor", + selector: FW_CFG_SMBIOS_ANCHOR, + size: smbios_anchor.len() as u32, + }, + FwCfgFile { + name: "etc/smbios/smbios-tables", + selector: FW_CFG_SMBIOS_TABLES, + size: smbios_tables.len() as u32, + }, + FwCfgFile { + name: ACPI_TABLE_FILE, + selector: FW_CFG_ACPI_TABLES, + size: acpi.tables.len() as u32, + }, + FwCfgFile { + name: ACPI_RSDP_FILE, + selector: FW_CFG_ACPI_RSDP, + size: acpi.rsdp.len() as u32, + }, + FwCfgFile { + name: ACPI_LOADER_FILE, + selector: FW_CFG_ACPI_LOADER, + size: acpi.loader.len() as u32, + }, + ]); + + Self { + base, + size, + kernel, + initrd, + cmdline, + file_dir, + memmap, + smbios_tables, + smbios_anchor, + acpi_tables: acpi.tables, + acpi_rsdp: acpi.rsdp, + acpi_loader: acpi.loader, + cpu_num, + ram_size, + state: Mutex::new(FwCfgState { + selected: FW_CFG_SIGNATURE, + offset: 0, + dma_address: 0, + }), + } + } + + fn selected_bytes(&self, selector: u16) -> FwCfgEntry<'_> { + match selector { + FW_CFG_SIGNATURE => FwCfgEntry::Bytes(b"QEMU"), + FW_CFG_ID => { + let version = if self.dma_enabled() { + FW_CFG_VERSION | FW_CFG_VERSION_DMA + } else { + FW_CFG_VERSION + }; + FwCfgEntry::Owned(version.to_le_bytes().to_vec()) + } + FW_CFG_RAM_SIZE => FwCfgEntry::Owned(self.ram_size.to_le_bytes().to_vec()), + FW_CFG_NB_CPUS => FwCfgEntry::Owned(self.cpu_num.to_le_bytes().to_vec()), + FW_CFG_MAX_CPUS => FwCfgEntry::Owned(self.cpu_num.to_le_bytes().to_vec()), + FW_CFG_KERNEL_SIZE => { + FwCfgEntry::Owned((self.kernel.len() as u32).to_le_bytes().to_vec()) + } + FW_CFG_KERNEL_DATA => FwCfgEntry::Bytes(self.kernel), + FW_CFG_INITRD_SIZE => { + let size = self.initrd.map_or(0, |initrd| initrd.len()) as u32; + FwCfgEntry::Owned(size.to_le_bytes().to_vec()) + } + FW_CFG_INITRD_DATA => FwCfgEntry::Bytes(self.initrd.unwrap_or(&[])), + FW_CFG_CMDLINE_SIZE => { + FwCfgEntry::Owned((self.cmdline.len() as u32).to_le_bytes().to_vec()) + } + FW_CFG_CMDLINE_DATA => FwCfgEntry::Bytes(&self.cmdline), + FW_CFG_FILE_DIR => FwCfgEntry::Bytes(&self.file_dir), + FW_CFG_FILE_FIRST => FwCfgEntry::Bytes(&self.memmap), + FW_CFG_SMBIOS_TABLES => FwCfgEntry::Bytes(&self.smbios_tables), + FW_CFG_SMBIOS_ANCHOR => FwCfgEntry::Bytes(&self.smbios_anchor), + FW_CFG_ACPI_TABLES => FwCfgEntry::Bytes(&self.acpi_tables), + FW_CFG_ACPI_RSDP => FwCfgEntry::Bytes(&self.acpi_rsdp), + FW_CFG_ACPI_LOADER => FwCfgEntry::Bytes(&self.acpi_loader), + _ => FwCfgEntry::Bytes(&[]), + } + } + + fn read_data(&self, width: AccessWidth) -> usize { + let mut state = self.state.lock(); + let entry = self.selected_bytes(state.selected); + let data = entry.as_slice(); + let mut value = 0usize; + let mut remaining = width.size(); + let old_offset = state.offset; + + let mut shift = 0; + while remaining > 0 && state.offset < data.len() { + value |= (data[state.offset] as usize) << shift; + state.offset += 1; + remaining -= 1; + shift += 8; + } + let old_mib = old_offset >> 20; + let new_mib = state.offset >> 20; + if state.selected == FW_CFG_KERNEL_DATA && new_mib > old_mib { + trace!( + "fw_cfg kernel read progress: {:#x}/{:#x}", + state.offset, + data.len() + ); + } + if matches!(state.selected, FW_CFG_CMDLINE_DATA | FW_CFG_CMDLINE_SIZE) && old_offset == 0 { + trace!( + "fw_cfg read selector={:#x}, width={:?}, value={:#x}, available={:#x}", + state.selected, + width, + value, + data.len() + ); + } + value + } + + fn write_selector(&self, width: AccessWidth, value: usize) { + let mut state = self.state.lock(); + state.selected = match width { + AccessWidth::Byte => value as u16, + AccessWidth::Word | AccessWidth::Dword | AccessWidth::Qword => { + ((value & 0xffff) as u16).swap_bytes() + } + }; + state.offset = 0; + if matches!( + state.selected, + FW_CFG_KERNEL_SIZE + | FW_CFG_KERNEL_DATA + | FW_CFG_INITRD_SIZE + | FW_CFG_INITRD_DATA + | FW_CFG_CMDLINE_SIZE + | FW_CFG_CMDLINE_DATA + | FW_CFG_FILE_DIR + | FW_CFG_ACPI_TABLES + | FW_CFG_ACPI_RSDP + | FW_CFG_ACPI_LOADER + ) { + trace!("fw_cfg select {:#x}", state.selected); + } + } + + fn dma_enabled(&self) -> bool { + self.size >= FW_CFG_DMA_OFFSET + core::mem::size_of::() + } + + /// Returns whether `addr` belongs to the QEMU fw_cfg DMA address register. + pub fn is_dma_address(&self, addr: GuestPhysAddr) -> bool { + if !self.dma_enabled() { + return false; + } + + let offset = addr.as_usize().saturating_sub(self.base.as_usize()); + (FW_CFG_DMA_OFFSET..FW_CFG_DMA_OFFSET + core::mem::size_of::()).contains(&offset) + } + + /// Records a big-endian DMA descriptor pointer write. + pub fn write_dma_address( + &self, + addr: GuestPhysAddr, + width: AccessWidth, + value: usize, + ) -> AxResult> { + let offset = addr.as_usize() - self.base.as_usize(); + if !self.is_dma_address(addr) { + return Ok(None); + } + + let mut state = self.state.lock(); + match (offset - FW_CFG_DMA_OFFSET, width) { + (0, AccessWidth::Dword) => { + let high = (value as u32).swap_bytes() as u64; + state.dma_address = (high << 32) | (state.dma_address & u32::MAX as u64); + Ok(None) + } + (4, AccessWidth::Dword) => { + let low = (value as u32).swap_bytes() as u64; + state.dma_address = (state.dma_address & !u32::MAX as u64) | low; + Ok(Some(GuestPhysAddr::from_usize(state.dma_address as usize))) + } + (0, AccessWidth::Qword) => { + state.dma_address = (value as u64).swap_bytes(); + Ok(Some(GuestPhysAddr::from_usize(state.dma_address as usize))) + } + _ => { + warn!( + "unsupported fw_cfg DMA address write: offset={:#x}, width={:?}", + offset, width + ); + ax_err!(InvalidInput, "unsupported fw_cfg DMA address write") + } + } + } + + /// Processes a QEMU fw_cfg DMA descriptor stored in guest physical memory. + pub fn process_dma( + &self, + desc_addr: GuestPhysAddr, + mut read_guest: R, + mut write_guest: W, + ) -> AxResult + where + R: FnMut(GuestPhysAddr, &mut [u8]) -> AxResult, + W: FnMut(GuestPhysAddr, &[u8]) -> AxResult, + { + let mut desc = [0u8; FW_CFG_DMA_DESC_SIZE]; + read_guest(desc_addr, &mut desc)?; + + let mut control = u32::from_be_bytes(desc[0..4].try_into().unwrap()); + let length = u32::from_be_bytes(desc[4..8].try_into().unwrap()) as usize; + let buffer_addr = + GuestPhysAddr::from_usize(u64::from_be_bytes(desc[8..16].try_into().unwrap()) as usize); + + let result = self.process_dma_command( + control, + length, + buffer_addr, + &mut read_guest, + &mut write_guest, + ); + control = if result.is_ok() { + 0 + } else { + FW_CFG_DMA_CTL_ERROR + }; + write_guest(desc_addr, &control.to_be_bytes())?; + result + } + + fn process_dma_command( + &self, + control: u32, + length: usize, + buffer_addr: GuestPhysAddr, + read_guest: &mut R, + write_guest: &mut W, + ) -> AxResult + where + R: FnMut(GuestPhysAddr, &mut [u8]) -> AxResult, + W: FnMut(GuestPhysAddr, &[u8]) -> AxResult, + { + let mut state = self.state.lock(); + if control & FW_CFG_DMA_CTL_SELECT != 0 { + state.selected = (control >> 16) as u16; + state.offset = 0; + } + + if control & FW_CFG_DMA_CTL_SKIP != 0 { + state.offset = state.offset.saturating_add(length); + } + + match control & (FW_CFG_DMA_CTL_READ | FW_CFG_DMA_CTL_WRITE) { + 0 => Ok(()), + FW_CFG_DMA_CTL_READ => { + trace!( + "fw_cfg DMA read selector={:#x}, offset={:#x}, length={:#x}, target={:#x}", + state.selected, + state.offset, + length, + buffer_addr.as_usize() + ); + let entry = self.selected_bytes(state.selected); + let data = entry.as_slice(); + let start = state.offset.min(data.len()); + let end = start.saturating_add(length).min(data.len()); + let mut out = Vec::with_capacity(length); + out.extend_from_slice(&data[start..end]); + out.resize(length, 0); + state.offset = state.offset.saturating_add(length); + drop(state); + write_guest(buffer_addr, &out) + } + FW_CFG_DMA_CTL_WRITE => { + let mut ignored = vec![0; length]; + if length != 0 { + read_guest(buffer_addr, &mut ignored)?; + } + state.offset = state.offset.saturating_add(length); + Ok(()) + } + _ => { + warn!("invalid fw_cfg DMA control {:#x}", control); + ax_err!(InvalidInput, "invalid fw_cfg DMA control") + } + } + } +} + +struct FwCfgFile<'a> { + name: &'a str, + selector: u16, + size: u32, +} + +fn build_file_dir(files: &[FwCfgFile<'_>]) -> Vec { + let mut dir = Vec::with_capacity(4 + files.len() * (4 + 2 + 2 + FW_CFG_FILE_NAME_SIZE)); + dir.extend_from_slice(&(files.len() as u32).to_be_bytes()); + for file in files { + dir.extend_from_slice(&file.size.to_be_bytes()); + dir.extend_from_slice(&file.selector.to_be_bytes()); + dir.extend_from_slice(&0u16.to_be_bytes()); + let name = file.name.as_bytes(); + let name_len = core::cmp::min(name.len(), FW_CFG_FILE_NAME_SIZE); + dir.extend_from_slice(&name[..name_len]); + dir.resize(dir.len() + FW_CFG_FILE_NAME_SIZE - name_len, 0); + } + dir +} + +fn build_memmap(regions: &[FwCfgRamRegion]) -> Vec { + let mut memmap = Vec::with_capacity(regions.len() * 24); + for region in regions { + if region.size != 0 { + push_memmap_entry(&mut memmap, region.base, region.size); + } + } + memmap +} + +fn push_memmap_entry(memmap: &mut Vec, base: u64, length: u64) { + memmap.extend_from_slice(&base.to_le_bytes()); + memmap.extend_from_slice(&length.to_le_bytes()); + memmap.extend_from_slice(&MEMMAP_RAM_TYPE.to_le_bytes()); + memmap.extend_from_slice(&0u32.to_le_bytes()); +} + +fn build_smbios_tables() -> Vec { + let mut table = Vec::with_capacity(6); + table.push(127); + table.push(4); + table.extend_from_slice(&0x7f00u16.to_le_bytes()); + table.extend_from_slice(&[0, 0]); + table +} + +fn build_smbios_anchor() -> Vec { + let table = build_smbios_tables(); + let mut anchor = Vec::with_capacity(24); + anchor.extend_from_slice(b"_SM3_"); + anchor.push(0); + anchor.push(24); + anchor.push(3); + anchor.push(0); + anchor.push(0); + anchor.push(1); + anchor.push(0); + anchor.extend_from_slice(&(table.len() as u32).to_le_bytes()); + anchor.extend_from_slice(&0u64.to_le_bytes()); + let checksum = (0u8).wrapping_sub(anchor.iter().fold(0u8, |sum, byte| sum.wrapping_add(*byte))); + anchor[5] = checksum; + anchor +} + +struct AcpiBlobs { + tables: Vec, + rsdp: Vec, + loader: Vec, +} + +fn build_acpi(cpu_num: u16, ram_regions: &[FwCfgRamRegion]) -> AcpiBlobs { + let mut tables = Vec::new(); + let mut loader = Vec::new(); + + push_loader_allocate(&mut loader, ACPI_TABLE_FILE, 64, QEMU_LOADER_ALLOC_HIGH); + + let facs = tables.len() as u32; + build_facs(&mut tables); + + let dsdt = tables.len() as u32; + build_dsdt(&mut tables); + push_loader_add_checksum( + &mut loader, + ACPI_TABLE_FILE, + dsdt as usize, + table_len(&tables, dsdt), + ); + + let fadt = tables.len() as u32; + build_fadt(&mut tables, facs, dsdt); + write_le_at(&mut tables, facs as u64, fadt as usize + 36, 4); + push_loader_add_pointer( + &mut loader, + ACPI_TABLE_FILE, + fadt + 36, + 4, + ACPI_TABLE_FILE, + facs, + ); + write_le_at(&mut tables, dsdt as u64, fadt as usize + 40, 4); + push_loader_add_pointer( + &mut loader, + ACPI_TABLE_FILE, + fadt + 40, + 4, + ACPI_TABLE_FILE, + dsdt, + ); + write_le_at(&mut tables, dsdt as u64, fadt as usize + 140, 8); + push_loader_add_pointer( + &mut loader, + ACPI_TABLE_FILE, + fadt + 140, + 8, + ACPI_TABLE_FILE, + dsdt, + ); + push_loader_add_checksum( + &mut loader, + ACPI_TABLE_FILE, + fadt as usize, + table_len(&tables, fadt), + ); + + let madt = tables.len() as u32; + build_madt(&mut tables, cpu_num); + push_loader_add_checksum( + &mut loader, + ACPI_TABLE_FILE, + madt as usize, + table_len(&tables, madt), + ); + + let srat = tables.len() as u32; + build_srat(&mut tables, cpu_num, ram_regions); + push_loader_add_checksum( + &mut loader, + ACPI_TABLE_FILE, + srat as usize, + table_len(&tables, srat), + ); + + let spcr = tables.len() as u32; + build_spcr(&mut tables); + push_loader_add_checksum( + &mut loader, + ACPI_TABLE_FILE, + spcr as usize, + table_len(&tables, spcr), + ); + + let mcfg = tables.len() as u32; + build_mcfg(&mut tables); + push_loader_add_checksum( + &mut loader, + ACPI_TABLE_FILE, + mcfg as usize, + table_len(&tables, mcfg), + ); + + let mut table_offsets = Vec::new(); + table_offsets.extend_from_slice(&[fadt, madt, srat, spcr, mcfg]); + + let rsdt = tables.len() as u32; + build_rsdt(&mut tables, &table_offsets); + for (idx, table_offset) in table_offsets.iter().enumerate() { + write_le_at( + &mut tables, + *table_offset as u64, + rsdt as usize + 36 + (idx * 4), + 4, + ); + push_loader_add_pointer( + &mut loader, + ACPI_TABLE_FILE, + rsdt + 36 + (idx as u32 * 4), + 4, + ACPI_TABLE_FILE, + *table_offset, + ); + } + push_loader_add_checksum( + &mut loader, + ACPI_TABLE_FILE, + rsdt as usize, + table_len(&tables, rsdt), + ); + + let mut rsdp = Vec::new(); + push_loader_allocate(&mut loader, ACPI_RSDP_FILE, 16, QEMU_LOADER_ALLOC_FSEG); + build_rsdp(&mut rsdp); + write_le_at(&mut rsdp, rsdt as u64, 16, 4); + push_loader_add_pointer(&mut loader, ACPI_RSDP_FILE, 16, 4, ACPI_TABLE_FILE, rsdt); + push_loader_add_checksum(&mut loader, ACPI_RSDP_FILE, 0, 20); + + AcpiBlobs { + tables, + rsdp, + loader, + } +} + +fn table_len(tables: &[u8], offset: u32) -> usize { + u32::from_le_bytes( + tables[offset as usize + 4..offset as usize + 8] + .try_into() + .unwrap(), + ) as usize +} + +fn build_facs(tables: &mut Vec) { + tables.extend_from_slice(b"FACS"); + push_le(tables, 64, 4); + push_le(tables, 0, 4); + push_le(tables, 0, 4); + push_le(tables, 0, 4); + push_le(tables, 0, 4); + tables.resize(tables.len() + 40, 0); +} + +fn build_dsdt(tables: &mut Vec) { + let start = begin_acpi_table(tables, b"DSDT", 1); + tables.extend_from_slice(&build_loongarch_dsdt_aml()); + end_acpi_table(tables, start); +} + +fn build_fadt(tables: &mut Vec, _facs: u32, _dsdt: u32) { + let start = begin_acpi_table(tables, b"FACP", 5); + push_le(tables, 0, 4); + push_le(tables, 0, 4); + push_le(tables, 0, 1); + push_le(tables, 0, 1); + push_le(tables, 0, 2); + push_le(tables, 0, 4); + push_le(tables, 0, 1); + push_le(tables, 0, 1); + push_le(tables, 0, 1); + push_le(tables, 0, 1); + for _ in 0..8 { + push_le(tables, 0, 4); + } + for _ in 0..8 { + push_le(tables, 0, 1); + } + push_le(tables, 0, 2); + push_le(tables, 0, 2); + push_le(tables, 0, 2); + push_le(tables, 0, 2); + for _ in 0..5 { + push_le(tables, 0, 1); + } + push_le(tables, 0, 2); + push_le(tables, 0, 1); + push_le(tables, (1u64 << 10) | (1u64 << 20), 4); + push_gas(tables, 0, 8, 0, 1, 0x100e_001e); + push_le(tables, 0x42, 1); + push_le(tables, 0, 3); + push_le(tables, 0, 8); + push_le(tables, 0, 8); + for _ in 0..8 { + push_gas(tables, 0, 0, 0, 0, 0); + } + push_gas(tables, 0, 8, 0, 1, 0x100e_001c); + push_gas(tables, 0, 8, 0, 1, 0x100e_001d); + end_acpi_table(tables, start); +} + +fn build_madt(tables: &mut Vec, cpu_num: u16) { + let start = begin_acpi_table(tables, b"APIC", 1); + push_le(tables, 0, 4); + push_le(tables, 1, 4); + + for cpu_id in 0..cpu_num { + push_le(tables, 17, 1); + push_le(tables, 15, 1); + push_le(tables, 1, 1); + push_le(tables, cpu_id as u64, 4); + push_le(tables, cpu_id as u64, 4); + push_le(tables, 1, 4); + } + + push_le(tables, 20, 1); + push_le(tables, 13, 1); + push_le(tables, 1, 1); + push_le(tables, 3, 1); + push_le(tables, 0, 1); + push_le(tables, 0xffff, 8); + + push_le(tables, 21, 1); + push_le(tables, 19, 1); + push_le(tables, 1, 1); + push_le(tables, 0x2ff0_0000, 8); + push_le(tables, 0x40, 4); + push_le(tables, 0xc0, 4); + + push_le(tables, 22, 1); + push_le(tables, 17, 1); + push_le(tables, 1, 1); + push_le(tables, 0x1000_0000, 8); + push_le(tables, 0x1000, 2); + push_le(tables, 0, 2); + push_le(tables, 0x40, 2); + + end_acpi_table(tables, start); +} + +fn build_srat(tables: &mut Vec, cpu_num: u16, ram_regions: &[FwCfgRamRegion]) { + let start = begin_acpi_table(tables, b"SRAT", 1); + push_le(tables, 1, 4); + push_le(tables, 0, 8); + + for cpu_id in 0..cpu_num { + push_le(tables, 0, 1); + push_le(tables, 16, 1); + push_le(tables, 0, 1); + push_le(tables, cpu_id as u64, 1); + push_le(tables, 1, 4); + push_le(tables, 0, 1); + push_le(tables, 0, 3); + push_le(tables, 0, 4); + } + + for region in ram_regions { + if region.size != 0 { + push_srat_memory(tables, region.base, region.size); + } + } + + end_acpi_table(tables, start); +} + +fn push_srat_memory(tables: &mut Vec, base: u64, length: u64) { + push_le(tables, 1, 1); + push_le(tables, 40, 1); + push_le(tables, 0, 4); + push_le(tables, 0, 2); + push_le(tables, base, 4); + push_le(tables, base >> 32, 4); + push_le(tables, length, 4); + push_le(tables, length >> 32, 4); + push_le(tables, 0, 4); + push_le(tables, 1, 4); + push_le(tables, 0, 8); +} + +fn build_spcr(tables: &mut Vec) { + let start = begin_acpi_table(tables, b"SPCR", 2); + push_le(tables, 0, 1); + push_le(tables, 0, 3); + push_gas(tables, 0, 8, 0, 1, 0x1fe0_01e0); + push_le(tables, 0, 1); + push_le(tables, 0, 1); + push_le(tables, 66, 4); + push_le(tables, 7, 1); + push_le(tables, 0, 1); + push_le(tables, 1, 1); + push_le(tables, 0, 1); + push_le(tables, 3, 1); + push_le(tables, 0, 1); + push_le(tables, 0xffff, 2); + push_le(tables, 0xffff, 2); + push_le(tables, 0, 1); + push_le(tables, 0, 1); + push_le(tables, 0, 1); + push_le(tables, 0, 4); + push_le(tables, 0, 1); + push_le(tables, 0, 4); + push_le(tables, 100_000_000, 4); + push_le(tables, 115_200, 4); + push_le(tables, 0, 2); + push_le(tables, 0, 2); + end_acpi_table(tables, start); +} + +fn build_mcfg(tables: &mut Vec) { + let start = begin_acpi_table(tables, b"MCFG", 1); + push_le(tables, 0, 8); + push_le(tables, VIRT_PCI_CFG_BASE, 8); + push_le(tables, 0, 2); + push_le(tables, 0, 1); + push_le(tables, (VIRT_PCI_CFG_SIZE - 1) >> 20, 1); + push_le(tables, 0, 4); + end_acpi_table(tables, start); +} + +fn build_rsdt(tables: &mut Vec, table_offsets: &[u32]) { + let start = begin_acpi_table(tables, b"RSDT", 1); + for _ in table_offsets { + push_le(tables, 0, 4); + } + end_acpi_table(tables, start); +} + +fn build_rsdp(rsdp: &mut Vec) { + rsdp.extend_from_slice(b"RSD PTR "); + push_le(rsdp, 0, 1); + rsdp.extend_from_slice(ACPI_OEM_ID); + push_le(rsdp, 0, 1); + push_le(rsdp, 0, 4); +} + +fn begin_acpi_table(tables: &mut Vec, signature: &[u8; 4], revision: u8) -> usize { + let start = tables.len(); + tables.extend_from_slice(signature); + push_le(tables, 0, 4); + push_le(tables, revision as u64, 1); + push_le(tables, 0, 1); + tables.extend_from_slice(ACPI_OEM_ID); + tables.extend_from_slice(ACPI_OEM_TABLE_ID); + push_le(tables, 1, 4); + tables.extend_from_slice(b"BXPC"); + push_le(tables, 1, 4); + start +} + +fn end_acpi_table(tables: &mut [u8], start: usize) { + let length = (tables.len() - start) as u32; + tables[start + 4..start + 8].copy_from_slice(&length.to_le_bytes()); +} + +fn build_loongarch_dsdt_aml() -> Vec { + let mut scope_body = Vec::new(); + scope_body.extend(aml_device("COMA", build_coma_aml())); + scope_body.extend(aml_device("PCI0", build_pci0_aml())); + + let mut aml = Vec::new(); + aml.extend(aml_scope("_SB_", scope_body)); + aml.extend(aml_scope( + "\\", + aml_name_decl( + "_S5_", + aml_package(&[aml_int(5), aml_int(0), aml_int(0), aml_int(0)]), + ), + )); + aml +} + +fn build_coma_aml() -> Vec { + let mut body = Vec::new(); + body.extend(aml_name_decl("_HID", aml_string("PNP0501"))); + body.extend(aml_name_decl("_UID", aml_int(0))); + body.extend(aml_name_decl("_CCA", aml_int(1))); + body.extend(aml_name_decl("_CRS", serial_crs_aml())); + body.extend_from_slice(&[ + 0x08, 0x5f, 0x44, 0x53, 0x44, 0x12, 0x32, 0x02, 0x11, 0x13, 0x0a, 0x10, 0x14, 0xd8, 0xff, + 0xda, 0xba, 0x6e, 0x8c, 0x4d, 0x8a, 0x91, 0xbc, 0x9b, 0xbf, 0x4a, 0xa3, 0x01, 0x12, 0x1b, + 0x01, 0x12, 0x18, 0x02, 0x0d, 0x63, 0x6c, 0x6f, 0x63, 0x6b, 0x2d, 0x66, 0x72, 0x65, 0x71, + 0x75, 0x65, 0x6e, 0x63, 0x79, 0x00, 0x0c, 0x00, 0xe1, 0xf5, 0x05, + ]); + body +} + +fn build_pci0_aml() -> Vec { + let mut body = Vec::new(); + body.extend(aml_name_decl("_HID", aml_string("PNP0A08"))); + body.extend(aml_name_decl("_CID", aml_string("PNP0A03"))); + body.extend(aml_name_decl("_SEG", aml_int(0))); + body.extend(aml_name_decl("_BBN", aml_int(0))); + body.extend(aml_name_decl("_UID", aml_int(0))); + body.extend(aml_name_decl("_CCA", aml_int(1))); + body.extend(aml_name_decl("_PRT", pci_route_package_aml())); + + for gsi in 0..4 { + body.extend(aml_device(&format!("GSI{gsi}"), build_gsi_link_aml(gsi))); + } + + body.extend(aml_method( + "_CBA", + 0, + aml_return(aml_int(VIRT_PCI_CFG_BASE)), + )); + body.extend(aml_name_decl("_CRS", pci_crs_aml())); + body.extend(aml_device("RES0", build_pci_res0_aml())); + body +} + +fn pci_route_package_aml() -> Vec { + const PCI_SLOT_MAX: usize = 32; + const PCI_NUM_PINS: usize = 4; + + let mut entries = Vec::new(); + for slot in 0..PCI_SLOT_MAX { + for pin in 0..PCI_NUM_PINS { + let gsi = (pin + slot) % PCI_NUM_PINS; + let address = ((slot as u64) << 16) | 0xffff; + entries.push(aml_package(&[ + aml_int(address), + aml_int(pin as u64), + aml_name_ref(&format!("GSI{gsi}")), + aml_int(0), + ])); + } + } + aml_package_with_count(entries, (PCI_SLOT_MAX * PCI_NUM_PINS) as u8) +} + +fn build_gsi_link_aml(gsi: usize) -> Vec { + let irq = 80 + gsi as u8; + let mut body = Vec::new(); + body.extend(aml_name_decl("_HID", aml_string("PNP0C0F"))); + body.extend(aml_name_decl("_UID", aml_int(gsi as u64))); + body.extend(aml_name_decl("_PRS", interrupt_crs_aml(irq, false))); + body.extend(aml_name_decl("_CRS", interrupt_crs_aml(irq, false))); + body.extend(aml_method("_SRS", 1, Vec::new())); + body +} + +fn build_pci_res0_aml() -> Vec { + let mut body = Vec::new(); + body.extend(aml_name_decl("_HID", aml_string("PNP0C02"))); + body.extend(aml_name_decl("_CRS", pci_res0_crs_aml())); + body +} + +fn aml_scope(name: &str, body: Vec) -> Vec { + let mut content = aml_name_ref(name); + content.extend(body); + aml_pkg_op(&[0x10], content) +} + +fn aml_device(name: &str, body: Vec) -> Vec { + let mut content = aml_name_ref(name); + content.extend(body); + aml_pkg_op(&[0x5b, 0x82], content) +} + +fn aml_method(name: &str, arg_count: u8, body: Vec) -> Vec { + let mut content = aml_name_ref(name); + content.push(arg_count & 0x7); + content.extend(body); + aml_pkg_op(&[0x14], content) +} + +fn aml_pkg_op(opcode: &[u8], content: Vec) -> Vec { + let mut out = Vec::new(); + out.extend_from_slice(opcode); + out.extend(aml_pkg_len(content.len())); + out.extend(content); + out +} + +fn aml_pkg_len(content_len: usize) -> Vec { + for len_len in 1..=4 { + let total_len = content_len + len_len; + let max_len = 1usize << (4 + 8 * (len_len - 1)); + if total_len < max_len { + if len_len == 1 { + return vec![total_len as u8]; + } + let mut bytes = Vec::with_capacity(len_len); + bytes.push((((len_len - 1) as u8) << 6) | ((total_len as u8) & 0x0f)); + let mut remaining = total_len >> 4; + for _ in 1..len_len { + bytes.push((remaining & 0xff) as u8); + remaining >>= 8; + } + return bytes; + } + } + unreachable!("AML package is too large") +} + +fn aml_name_decl(name: &str, value: Vec) -> Vec { + let mut out = Vec::new(); + out.push(0x08); + out.extend(aml_name_ref(name)); + out.extend(value); + out +} + +fn aml_name_ref(name: &str) -> Vec { + if name == "\\" { + return vec![0x5c]; + } + let bytes = name.as_bytes(); + assert_eq!(bytes.len(), 4, "AML short names must be 4 bytes"); + bytes.to_vec() +} + +fn aml_string(value: &str) -> Vec { + let mut out = Vec::with_capacity(value.len() + 2); + out.push(0x0d); + out.extend_from_slice(value.as_bytes()); + out.push(0); + out +} + +fn aml_int(value: u64) -> Vec { + match value { + 0 => vec![0x00], + 1 => vec![0x01], + 2..=0xff => vec![0x0a, value as u8], + 0x100..=0xffff => { + let mut out = vec![0x0b]; + out.extend_from_slice(&(value as u16).to_le_bytes()); + out + } + 0x1_0000..=0xffff_ffff => { + let mut out = vec![0x0c]; + out.extend_from_slice(&(value as u32).to_le_bytes()); + out + } + _ => { + let mut out = vec![0x0e]; + out.extend_from_slice(&value.to_le_bytes()); + out + } + } +} + +fn aml_package(elements: &[Vec]) -> Vec { + aml_package_with_count(elements.to_vec(), elements.len() as u8) +} + +fn aml_package_with_count(elements: Vec>, count: u8) -> Vec { + let mut content = vec![count]; + for element in elements { + content.extend(element); + } + aml_pkg_op(&[0x12], content) +} + +fn aml_return(value: Vec) -> Vec { + let mut out = vec![0xa4]; + out.extend(value); + out +} + +fn serial_crs_aml() -> Vec { + vec![ + 0x11, 0x3c, 0x0a, 0x39, 0x8a, 0x2b, 0x00, 0x00, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0xe0, 0x01, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0xdf, 0x02, 0xe0, 0x1f, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x06, 0x00, 0x09, 0x01, 0x42, 0x00, 0x00, 0x00, 0x79, + 0x00, + ] +} + +fn interrupt_crs_aml(irq: u8, shared: bool) -> Vec { + vec![ + 0x11, + 0x0e, + 0x0a, + 0x0b, + 0x89, + 0x06, + 0x00, + 0x01, + if shared { 0x09 } else { 0x01 }, + irq, + 0x00, + 0x00, + 0x00, + 0x79, + 0x00, + ] +} + +fn pci_crs_aml() -> Vec { + vec![ + 0x11, 0x4e, 0x05, 0x0a, 0x5a, 0x88, 0x0d, 0x00, 0x02, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7f, 0x00, 0x00, 0x00, 0x80, 0x00, 0x87, 0x17, 0x00, 0x01, 0x0c, 0x03, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, + 0x01, 0x00, 0x8a, 0x2b, 0x00, 0x00, 0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, + 0x00, 0x00, 0x00, 0x79, 0x00, + ] +} + +fn pci_res0_crs_aml() -> Vec { + vec![ + 0x11, 0x33, 0x0a, 0x30, 0x8a, 0x2b, 0x00, 0x00, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x27, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, + ] +} + +fn push_gas(out: &mut Vec, space: u8, bit_width: u8, bit_offset: u8, access: u8, addr: u64) { + out.push(space); + out.push(bit_width); + out.push(bit_offset); + out.push(access); + push_le(out, addr, 8); +} + +fn push_loader_allocate(out: &mut Vec, file: &str, align: u32, zone: u8) { + let mut entry = [0u8; QEMU_LOADER_ENTRY_SIZE]; + entry[0..4].copy_from_slice(&QEMU_LOADER_CMD_ALLOCATE.to_le_bytes()); + write_loader_file(&mut entry[4..60], file); + entry[60..64].copy_from_slice(&align.to_le_bytes()); + entry[64] = zone; + out.extend_from_slice(&entry); +} + +fn push_loader_add_pointer( + out: &mut Vec, + pointer_file: &str, + pointer_offset: u32, + pointer_size: u8, + pointee_file: &str, + pointee_offset: u32, +) { + let mut entry = [0u8; QEMU_LOADER_ENTRY_SIZE]; + entry[0..4].copy_from_slice(&QEMU_LOADER_CMD_ADD_POINTER.to_le_bytes()); + write_loader_file(&mut entry[4..60], pointer_file); + write_loader_file(&mut entry[60..116], pointee_file); + entry[116..120].copy_from_slice(&pointer_offset.to_le_bytes()); + entry[120] = pointer_size; + let _ = pointee_offset; + out.extend_from_slice(&entry); +} + +fn push_loader_add_checksum(out: &mut Vec, file: &str, start: usize, length: usize) { + let mut entry = [0u8; QEMU_LOADER_ENTRY_SIZE]; + entry[0..4].copy_from_slice(&QEMU_LOADER_CMD_ADD_CHECKSUM.to_le_bytes()); + write_loader_file(&mut entry[4..60], file); + entry[60..64].copy_from_slice(&((start + 9) as u32).to_le_bytes()); + entry[64..68].copy_from_slice(&(start as u32).to_le_bytes()); + entry[68..72].copy_from_slice(&(length as u32).to_le_bytes()); + out.extend_from_slice(&entry); +} + +fn write_loader_file(dst: &mut [u8], file: &str) { + let bytes = file.as_bytes(); + let len = core::cmp::min(bytes.len(), dst.len().saturating_sub(1)); + dst[..len].copy_from_slice(&bytes[..len]); +} + +fn write_le_at(out: &mut [u8], value: u64, offset: usize, size: u8) { + let bytes = value.to_le_bytes(); + out[offset..offset + size as usize].copy_from_slice(&bytes[..size as usize]); +} + +fn push_le(out: &mut Vec, value: u64, size: usize) { + out.extend_from_slice(&value.to_le_bytes()[..size]); +} + +enum FwCfgEntry<'a> { + Bytes(&'a [u8]), + Owned(Vec), +} + +impl<'a> FwCfgEntry<'a> { + fn as_slice(&'a self) -> &'a [u8] { + match self { + Self::Bytes(bytes) => bytes, + Self::Owned(bytes) => bytes, + } + } +} + +impl BaseDeviceOps for FwCfg { + fn emu_type(&self) -> EmuDeviceType { + EmuDeviceType::FwCfg + } + + fn address_range(&self) -> GuestPhysAddrRange { + GuestPhysAddrRange::from_start_size(self.base, self.size) + } + + fn handle_read(&self, addr: GuestPhysAddr, width: AccessWidth) -> AxResult { + match addr.as_usize() - self.base.as_usize() { + FW_CFG_DATA_OFFSET => Ok(self.read_data(width)), + FW_CFG_SELECTOR_OFFSET => Ok(self.state.lock().selected as usize), + _ => Ok(0), + } + } + + fn handle_write(&self, addr: GuestPhysAddr, width: AccessWidth, val: usize) -> AxResult { + let offset = addr.as_usize() - self.base.as_usize(); + if offset == FW_CFG_SELECTOR_OFFSET { + self.write_selector(width, val); + } + Ok(()) + } +} diff --git a/virtualization/axdevice/src/lib.rs b/virtualization/axdevice/src/lib.rs index b5c89e03d8..d26962361e 100644 --- a/virtualization/axdevice/src/lib.rs +++ b/virtualization/axdevice/src/lib.rs @@ -30,6 +30,9 @@ mod adapter; mod config; mod device; mod factory; +mod fw_cfg; +#[cfg(target_arch = "loongarch64")] +mod loongarch_pch_pic; mod range_alloc; mod registration; @@ -46,6 +49,9 @@ pub use factory::{ DeviceBuildContext, DeviceFactory, DeviceFactoryRegistry, IrqResolver, register_builtin_factories, }; +pub use fw_cfg::{FwCfg, FwCfgPlatformConfig, FwCfgRamRegion}; +#[cfg(target_arch = "loongarch64")] +pub use loongarch_pch_pic::LoongArchPchPic; pub use registration::{DeviceBundle, DeviceRegistration, PollableDeviceOps}; #[cfg(target_arch = "x86_64")] pub use x86_vlapic::IoApicInterrupt; diff --git a/virtualization/axdevice/src/loongarch_pch_pic.rs b/virtualization/axdevice/src/loongarch_pch_pic.rs new file mode 100644 index 0000000000..25af2f6262 --- /dev/null +++ b/virtualization/axdevice/src/loongarch_pch_pic.rs @@ -0,0 +1,407 @@ +use core::sync::atomic::{AtomicUsize, Ordering}; + +use ax_errno::AxResult; +use ax_kspin::SpinNoIrq as Mutex; +use axdevice_base::{AccessWidth, BaseDeviceOps, EmuDeviceType}; +use axvm_types::{GuestPhysAddr, GuestPhysAddrRange}; + +const PCH_PIC_INT_ID_LO: usize = 0x000; +const PCH_PIC_INT_ID_HI: usize = 0x004; +const PCH_PIC_INT_MASK_LO: usize = 0x020; +const PCH_PIC_INT_MASK_HI: usize = 0x024; +const PCH_PIC_HTMSI_EN_LO: usize = 0x040; +const PCH_PIC_HTMSI_EN_HI: usize = 0x044; +const PCH_PIC_INT_EDGE_LO: usize = 0x060; +const PCH_PIC_INT_EDGE_HI: usize = 0x064; +const PCH_PIC_INT_CLEAR_LO: usize = 0x080; +const PCH_PIC_INT_CLEAR_HI: usize = 0x084; +const PCH_PIC_AUTO_CTRL0_LO: usize = 0x0c0; +const PCH_PIC_AUTO_CTRL0_HI: usize = 0x0c4; +const PCH_PIC_AUTO_CTRL1_LO: usize = 0x0e0; +const PCH_PIC_AUTO_CTRL1_HI: usize = 0x0e4; +const PCH_PIC_ROUTE_ENTRY_BASE: usize = 0x100; +const PCH_PIC_HTMSI_VEC_BASE: usize = 0x200; +const PCH_PIC_INT_IRR_LO: usize = 0x380; +const PCH_PIC_INT_IRR_HI: usize = 0x384; +const PCH_PIC_INT_ISR_LO: usize = 0x3a0; +const PCH_PIC_INT_ISR_HI: usize = 0x3a4; +const PCH_PIC_POL_LO: usize = 0x3e0; +const PCH_PIC_POL_HI: usize = 0x3e4; +const PCH_PIC_IRQ_COUNT: usize = 64; +const PCH_PIC_INT_ID_VAL: usize = 0x0700_0000; +const PCH_PIC_INT_ID_VER: usize = 0x1; +const PCH_PIC_IO_LOG_LIMIT: usize = 256; +const PCH_PIC_IRQ_LOG_LIMIT: usize = 64; +const PCH_PIC_LEVEL_LOG_LIMIT: usize = 64; + +static PCH_PIC_IO_LOGS: AtomicUsize = AtomicUsize::new(0); +static PCH_PIC_IRQ_LOGS: AtomicUsize = AtomicUsize::new(0); +static PCH_PIC_LEVEL_LOGS: AtomicUsize = AtomicUsize::new(0); + +#[derive(Clone, Debug)] +struct PchPicState { + int_mask: u64, + htmsi_en: u64, + intedge: u64, + last_intirr: u64, + intirr: u64, + intisr: u64, + int_polarity: u64, + auto_ctrl0: u64, + auto_ctrl1: u64, + route_entry: [u8; PCH_PIC_IRQ_COUNT], + htmsi_vector: [u8; PCH_PIC_IRQ_COUNT], +} + +impl Default for PchPicState { + fn default() -> Self { + let mut state = Self { + int_mask: !0, + htmsi_en: 0, + intedge: 0, + last_intirr: 0, + intirr: 0, + intisr: 0, + int_polarity: 0, + auto_ctrl0: 0, + auto_ctrl1: 0, + route_entry: [0; PCH_PIC_IRQ_COUNT], + htmsi_vector: [0; PCH_PIC_IRQ_COUNT], + }; + for irq in 0..PCH_PIC_IRQ_COUNT { + state.route_entry[irq] = 1; + state.htmsi_vector[irq] = irq as u8; + } + state + } +} + +/// Minimal LS7A PCH-PIC model for LoongArch QEMU virt guests. +/// +/// Linux configures this irqchip through ACPI even when the backing PCI devices +/// are passthrough. The model must preserve the mask/IRR/ISR/route state so the +/// guest sees a coherent interrupt controller instead of changing the host PCH. +pub struct LoongArchPchPic { + base: GuestPhysAddr, + size: usize, + state: Mutex, +} + +impl LoongArchPchPic { + pub fn new(base: GuestPhysAddr, size: usize) -> Self { + Self { + base, + size, + state: Mutex::new(PchPicState::default()), + } + } + + /// Updates a PCH input source level and returns the EIOINTC source to assert, if any. + pub fn set_irq_level(&self, irq: usize, level: bool) -> Option { + let mut state = self.state.lock(); + if irq >= PCH_PIC_IRQ_COUNT { + return None; + } + + let mask = 1u64 << irq; + if level { + state.intirr |= mask; + state.last_intirr |= mask; + } else { + state.intirr &= !mask; + state.last_intirr &= !mask; + } + + let routed = update_irq(&mut state, mask, level); + log_pch_pic_level(&state, irq, level, routed); + routed + } + + /// Returns the pending EIOINTC source for an already-latched PCH source. + pub fn pending_vector(&self, irq: usize) -> Option { + let mut state = self.state.lock(); + if irq >= PCH_PIC_IRQ_COUNT { + return None; + } + + update_irq(&mut state, 1u64 << irq, true) + } +} + +impl BaseDeviceOps for LoongArchPchPic { + fn emu_type(&self) -> EmuDeviceType { + EmuDeviceType::LoongArchPchPic + } + + fn address_range(&self) -> GuestPhysAddrRange { + GuestPhysAddrRange::from_start_size(self.base, self.size) + } + + fn handle_read(&self, addr: GuestPhysAddr, width: AccessWidth) -> AxResult { + let offset = addr.as_usize() - self.base.as_usize(); + let state = self.state.lock(); + let value = match width { + AccessWidth::Byte => read_byte(&state, offset), + AccessWidth::Word => read_split_bytes(&state, offset, 2), + AccessWidth::Dword => read_dword(&state, offset), + AccessWidth::Qword => { + read_dword(&state, offset) | (read_dword(&state, offset + 4) << 32) + } + }; + log_pch_pic_io("read", offset, width, value); + Ok(value) + } + + fn handle_write(&self, addr: GuestPhysAddr, width: AccessWidth, val: usize) -> AxResult { + let offset = addr.as_usize() - self.base.as_usize(); + let mut state = self.state.lock(); + log_pch_pic_io("write", offset, width, val); + match width { + AccessWidth::Byte => write_byte(&mut state, offset, val as u8), + AccessWidth::Word => write_split_bytes(&mut state, offset, 2, val), + AccessWidth::Dword => write_dword(&mut state, offset, val as u32), + AccessWidth::Qword => { + write_dword(&mut state, offset, val as u32); + write_dword(&mut state, offset + 4, (val >> 32) as u32); + } + } + Ok(()) + } +} + +fn read_byte(state: &PchPicState, offset: usize) -> usize { + if let Some(index) = reg8_offset(offset) { + return match index { + PCH_PIC_ROUTE_ENTRY_BASE..=0x13f => pch_pic_irq_index(index, PCH_PIC_ROUTE_ENTRY_BASE) + .map(|irq| state.route_entry[irq] as usize) + .unwrap_or(0), + PCH_PIC_HTMSI_VEC_BASE..=0x23f => pch_pic_irq_index(index, PCH_PIC_HTMSI_VEC_BASE) + .map(|irq| state.htmsi_vector[irq] as usize) + .unwrap_or(0), + _ => 0, + }; + } + + match offset { + _ => { + let shift = (offset & 0x3) * 8; + (read_dword(state, offset & !0x3) >> shift) & 0xff + } + } +} + +fn write_byte(state: &mut PchPicState, offset: usize, val: u8) { + if let Some(index) = reg8_offset(offset) { + match index { + PCH_PIC_ROUTE_ENTRY_BASE..=0x13f => { + if let Some(irq) = pch_pic_irq_index(index, PCH_PIC_ROUTE_ENTRY_BASE) { + state.route_entry[irq] = val; + } + } + PCH_PIC_HTMSI_VEC_BASE..=0x23f => { + if let Some(irq) = pch_pic_irq_index(index, PCH_PIC_HTMSI_VEC_BASE) { + state.htmsi_vector[irq] = val; + } + } + _ => {} + } + return; + } + + match offset { + _ => { + let aligned = offset & !0x3; + let shift = (offset & 0x3) * 8; + let old = read_dword(state, aligned); + let new = (old & !(0xff << shift)) | ((val as usize) << shift); + write_dword(state, aligned, new as u32); + } + } +} + +fn read_split_bytes(state: &PchPicState, offset: usize, len: usize) -> usize { + let mut value = 0; + for idx in 0..len { + value |= read_byte(state, offset + idx) << (idx * 8); + } + value +} + +fn write_split_bytes(state: &mut PchPicState, offset: usize, len: usize, val: usize) { + for idx in 0..len { + write_byte(state, offset + idx, (val >> (idx * 8)) as u8); + } +} + +fn read_dword(state: &PchPicState, offset: usize) -> usize { + match offset { + PCH_PIC_INT_ID_LO => PCH_PIC_INT_ID_VAL, + PCH_PIC_INT_ID_HI => PCH_PIC_INT_ID_VER | ((PCH_PIC_IRQ_COUNT - 1) << 16), + PCH_PIC_INT_MASK_LO => state.int_mask as u32 as usize, + PCH_PIC_INT_MASK_HI => (state.int_mask >> 32) as u32 as usize, + PCH_PIC_HTMSI_EN_LO => state.htmsi_en as u32 as usize, + PCH_PIC_HTMSI_EN_HI => (state.htmsi_en >> 32) as u32 as usize, + PCH_PIC_INT_EDGE_LO => state.intedge as u32 as usize, + PCH_PIC_INT_EDGE_HI => (state.intedge >> 32) as u32 as usize, + PCH_PIC_AUTO_CTRL0_LO => state.auto_ctrl0 as u32 as usize, + PCH_PIC_AUTO_CTRL0_HI => (state.auto_ctrl0 >> 32) as u32 as usize, + PCH_PIC_AUTO_CTRL1_LO => state.auto_ctrl1 as u32 as usize, + PCH_PIC_AUTO_CTRL1_HI => (state.auto_ctrl1 >> 32) as u32 as usize, + PCH_PIC_INT_IRR_LO => state.intirr as u32 as usize, + PCH_PIC_INT_IRR_HI => (state.intirr >> 32) as u32 as usize, + PCH_PIC_INT_ISR_LO => (state.intisr & !state.int_mask) as u32 as usize, + PCH_PIC_INT_ISR_HI => ((state.intisr & !state.int_mask) >> 32) as u32 as usize, + PCH_PIC_POL_LO => state.int_polarity as u32 as usize, + PCH_PIC_POL_HI => (state.int_polarity >> 32) as u32 as usize, + PCH_PIC_ROUTE_ENTRY_BASE..=0x13f | PCH_PIC_HTMSI_VEC_BASE..=0x23f => { + read_split_bytes(state, offset, 4) + } + _ => 0, + } +} + +fn write_dword(state: &mut PchPicState, offset: usize, val: u32) { + match offset { + PCH_PIC_INT_MASK_LO => update_int_mask(state, val, false), + PCH_PIC_INT_MASK_HI => update_int_mask(state, val, true), + PCH_PIC_HTMSI_EN_LO => state.htmsi_en = replace_u32(state.htmsi_en, val, false), + PCH_PIC_HTMSI_EN_HI => state.htmsi_en = replace_u32(state.htmsi_en, val, true), + PCH_PIC_INT_EDGE_LO => state.intedge = replace_u32(state.intedge, val, false), + PCH_PIC_INT_EDGE_HI => state.intedge = replace_u32(state.intedge, val, true), + PCH_PIC_INT_CLEAR_LO => clear_irq(state, val as u64), + PCH_PIC_INT_CLEAR_HI => clear_irq(state, (val as u64) << 32), + PCH_PIC_AUTO_CTRL0_LO => state.auto_ctrl0 = replace_u32(state.auto_ctrl0, val, false), + PCH_PIC_AUTO_CTRL0_HI => state.auto_ctrl0 = replace_u32(state.auto_ctrl0, val, true), + PCH_PIC_AUTO_CTRL1_LO => state.auto_ctrl1 = replace_u32(state.auto_ctrl1, val, false), + PCH_PIC_AUTO_CTRL1_HI => state.auto_ctrl1 = replace_u32(state.auto_ctrl1, val, true), + PCH_PIC_INT_ISR_LO => state.intisr = replace_u32(state.intisr, val, false), + PCH_PIC_INT_ISR_HI => state.intisr = replace_u32(state.intisr, val, true), + PCH_PIC_POL_LO => state.int_polarity = replace_u32(state.int_polarity, val, false), + PCH_PIC_POL_HI => state.int_polarity = replace_u32(state.int_polarity, val, true), + PCH_PIC_ROUTE_ENTRY_BASE..=0x13f | PCH_PIC_HTMSI_VEC_BASE..=0x23f => { + write_split_bytes(state, offset, 4, val as usize) + } + _ => {} + } +} + +fn update_irq(state: &mut PchPicState, mask: u64, level: bool) -> Option { + let valid_irqs = if PCH_PIC_IRQ_COUNT >= u64::BITS as usize { + u64::MAX + } else { + (1u64 << PCH_PIC_IRQ_COUNT) - 1 + }; + let mask = mask & valid_irqs; + if mask == 0 { + return None; + } + + if level { + let pending = mask & state.intirr & !state.int_mask & !state.intisr; + if pending != 0 { + let irq = pending.trailing_zeros() as usize; + state.intisr |= 1u64 << irq; + log_pch_pic_irq(state, "assert", irq, level, mask); + return Some(state.htmsi_vector[irq] as usize); + } + } else { + let inactive = mask & state.intisr & !state.intirr; + if inactive != 0 { + let irq = inactive.trailing_zeros() as usize; + state.intisr &= !(1u64 << irq); + log_pch_pic_irq(state, "deassert", irq, level, mask); + return Some(state.htmsi_vector[irq] as usize); + } + } + + None +} + +fn pch_pic_irq_index(offset: usize, base: usize) -> Option { + let irq = offset - base; + (irq < PCH_PIC_IRQ_COUNT).then_some(irq) +} + +fn reg8_offset(offset: usize) -> Option { + (PCH_PIC_ROUTE_ENTRY_BASE..PCH_PIC_INT_ISR_LO) + .contains(&offset) + .then_some(offset) +} + +fn clear_irq(state: &mut PchPicState, mask: u64) { + state.intirr &= !mask; + state.last_intirr &= !mask; + state.intisr &= !mask; +} + +fn update_int_mask(state: &mut PchPicState, val: u32, high: bool) { + let old = state.int_mask; + state.int_mask = replace_u32(old, val, high); + + let old_part = if high { old >> 32 } else { old } as u32; + let newly_unmasked = old_part & !val; + if newly_unmasked != 0 { + let mask = if high { + (newly_unmasked as u64) << 32 + } else { + newly_unmasked as u64 + }; + let _ = update_irq(state, mask, true); + } + + let newly_masked = !old_part & val; + if newly_masked != 0 { + let mask = if high { + (newly_masked as u64) << 32 + } else { + newly_masked as u64 + }; + let _ = update_irq(state, mask, false); + } +} + +fn replace_u32(old: u64, val: u32, high: bool) -> u64 { + if high { + (old & 0x0000_0000_ffff_ffff) | ((val as u64) << 32) + } else { + (old & 0xffff_ffff_0000_0000) | val as u64 + } +} + +fn log_pch_pic_io(op: &str, offset: usize, width: AccessWidth, value: usize) { + let is_key_reg = matches!( + offset, + PCH_PIC_INT_MASK_LO + | PCH_PIC_INT_MASK_HI + | PCH_PIC_INT_CLEAR_LO + | PCH_PIC_INT_CLEAR_HI + | PCH_PIC_HTMSI_EN_LO + | PCH_PIC_HTMSI_EN_HI + ); + if is_key_reg || PCH_PIC_IO_LOGS.fetch_add(1, Ordering::Relaxed) < PCH_PIC_IO_LOG_LIMIT { + trace!( + "LoongArch guest PCH-PIC {op}: offset={:#x}, width={:?}, value={:#x}", + offset, width, value + ); + } +} + +fn log_pch_pic_level(state: &PchPicState, irq: usize, level: bool, routed: Option) { + if PCH_PIC_LEVEL_LOGS.fetch_add(1, Ordering::Relaxed) < PCH_PIC_LEVEL_LOG_LIMIT { + trace!( + "LoongArch guest PCH-PIC level: input={}, level={}, routed={:?}, int_mask={:#x}, \ + intirr={:#x}, intisr={:#x}, htvec={}", + irq, level, routed, state.int_mask, state.intirr, state.intisr, state.htmsi_vector[irq] + ); + } +} + +fn log_pch_pic_irq(state: &PchPicState, op: &str, irq: usize, level: bool, mask: u64) { + if PCH_PIC_IRQ_LOGS.fetch_add(1, Ordering::Relaxed) < PCH_PIC_IRQ_LOG_LIMIT { + trace!( + "LoongArch guest PCH-PIC irq {op}: input={}, level={}, mask={:#x}, int_mask={:#x}, \ + intirr={:#x}, intisr={:#x}, htvec={}", + irq, level, mask, state.int_mask, state.intirr, state.intisr, state.htmsi_vector[irq] + ); + } +} diff --git a/virtualization/axvcpu/src/arch_vcpu.rs b/virtualization/axvcpu/src/arch_vcpu.rs index 6bceb32526..e8fb8637a9 100644 --- a/virtualization/axvcpu/src/arch_vcpu.rs +++ b/virtualization/axvcpu/src/arch_vcpu.rs @@ -13,6 +13,7 @@ // limitations under the License. use ax_errno::AxResult; +use ax_page_table_entry::MappingFlags; use axvm_types::{GuestPhysAddr, HostPhysAddr, InterruptTriggerMode, VCpuId, VMId}; use crate::exit::AxVCpuExitReason; @@ -77,6 +78,15 @@ pub trait AxArchVCpu: Sized { /// Sets the value of a general-purpose register. fn set_gpr(&mut self, reg: usize, val: usize); + /// Decodes the last architecture-specific memory fault as MMIO when possible. + fn decode_mmio_fault( + &mut self, + _fault_addr: GuestPhysAddr, + _access_flags: MappingFlags, + ) -> Option { + None + } + /// Inject an interrupt to the VCpu. /// /// It's guaranteed (for implementors, and required for callers) that this function is called diff --git a/virtualization/axvm-types/src/lib.rs b/virtualization/axvm-types/src/lib.rs index e044988343..4aa42d0d08 100644 --- a/virtualization/axvm-types/src/lib.rs +++ b/virtualization/axvm-types/src/lib.rs @@ -232,6 +232,8 @@ pub enum EmulatedDeviceType { InterruptController = 0x1, /// Console (serial) device. Console = 0x2, + /// QEMU fw_cfg MMIO device. + FwCfg = 0x3, /// An emulated device that provides Inter-VM Communication (IVC) channel. /// /// This device is used for communication between different VMs, @@ -253,6 +255,8 @@ pub enum EmulatedDeviceType { X86IoApic = 0x23, /// x86 virtual PIT/8254 timer device. X86Pit = 0x24, + /// LoongArch virtual PCH-PIC device. + LoongArchPchPic = 0x25, // 0x30: PPPT (PLIC Partial Passthrough) devices. /// RISC-V PLIC Partial Passthrough Global device. @@ -280,6 +284,7 @@ impl Display for EmulatedDeviceType { fn fmt(&self, f: &mut Formatter<'_>) -> core::fmt::Result { match self { EmulatedDeviceType::Console => write!(f, "console"), + EmulatedDeviceType::FwCfg => write!(f, "fw_cfg"), EmulatedDeviceType::InterruptController => write!(f, "interrupt controller"), EmulatedDeviceType::GPPTRedistributor => { write!(f, "gic partial passthrough redistributor") @@ -288,6 +293,7 @@ impl Display for EmulatedDeviceType { EmulatedDeviceType::GPPTITS => write!(f, "gic partial passthrough its"), EmulatedDeviceType::X86IoApic => write!(f, "x86 io apic"), EmulatedDeviceType::X86Pit => write!(f, "x86 pit"), + EmulatedDeviceType::LoongArchPchPic => write!(f, "loongarch pch pic"), EmulatedDeviceType::PPPTGlobal => write!(f, "plic partial passthrough global"), // EmulatedDeviceType::IOMMU => write!(f, "iommu"), // EmulatedDeviceType::ICCSRE => write!(f, "interrupt icc sre"), @@ -304,16 +310,18 @@ impl Display for EmulatedDeviceType { impl EmulatedDeviceType { /// All known emulated device types. - pub const ALL: [Self; 13] = [ + pub const ALL: [Self; 15] = [ EmulatedDeviceType::Dummy, EmulatedDeviceType::InterruptController, EmulatedDeviceType::Console, + EmulatedDeviceType::FwCfg, EmulatedDeviceType::IVCChannel, EmulatedDeviceType::GPPTRedistributor, EmulatedDeviceType::GPPTDistributor, EmulatedDeviceType::GPPTITS, EmulatedDeviceType::X86IoApic, EmulatedDeviceType::X86Pit, + EmulatedDeviceType::LoongArchPchPic, EmulatedDeviceType::PPPTGlobal, EmulatedDeviceType::VirtioBlk, EmulatedDeviceType::VirtioNet, @@ -348,12 +356,14 @@ impl EmulatedDeviceType { 0x0 => Some(EmulatedDeviceType::Dummy), 0x1 => Some(EmulatedDeviceType::InterruptController), 0x2 => Some(EmulatedDeviceType::Console), + 0x3 => Some(EmulatedDeviceType::FwCfg), 0xA => Some(EmulatedDeviceType::IVCChannel), 0x20 => Some(EmulatedDeviceType::GPPTRedistributor), 0x21 => Some(EmulatedDeviceType::GPPTDistributor), 0x22 => Some(EmulatedDeviceType::GPPTITS), 0x23 => Some(EmulatedDeviceType::X86IoApic), 0x24 => Some(EmulatedDeviceType::X86Pit), + 0x25 => Some(EmulatedDeviceType::LoongArchPchPic), 0x30 => Some(EmulatedDeviceType::PPPTGlobal), 0xE1 => Some(EmulatedDeviceType::VirtioBlk), 0xE2 => Some(EmulatedDeviceType::VirtioNet), diff --git a/virtualization/axvm/src/arch.rs b/virtualization/axvm/src/arch.rs index 903268f018..741280ebf6 100644 --- a/virtualization/axvm/src/arch.rs +++ b/virtualization/axvm/src/arch.rs @@ -233,6 +233,25 @@ mod loongarch64 { ); } } + + fn inject_external_interrupt( + vm_id: usize, + vcpu_id: usize, + vector: usize, + physical_irq: usize, + ) { + if let Err(err) = crate::runtime::vcpus::queue_external_interrupt( + vm_id, + vcpu_id, + vector, + physical_irq, + ) { + warn!( + "failed to queue LoongArch external interrupt vector={vector:#x}, \ + physical_irq={physical_irq:#x} for VM[{vm_id}] VCpu[{vcpu_id}]: {err:?}" + ); + } + } } } diff --git a/virtualization/axvm/src/config.rs b/virtualization/axvm/src/config.rs index 26d955edfc..0deca0c098 100644 --- a/virtualization/axvm/src/config.rs +++ b/virtualization/axvm/src/config.rs @@ -38,6 +38,9 @@ pub struct AxVCpuConfig { /// LoongArch Linux boot stack top. #[cfg(target_arch = "loongarch64")] pub boot_stack_top: usize, + /// Whether the LoongArch guest should be entered like firmware after CPU reset. + #[cfg(target_arch = "loongarch64")] + pub firmware_boot: bool, } /// Ramdisk image information. @@ -106,6 +109,10 @@ pub fn adjusted_kernel_load_gpa( boot_protocol: VMBootProtocol, bios_load_gpa: Option, ) -> Option { + if boot_protocol == VMBootProtocol::Uefi { + return None; + } + if !main_memory.is_identical() { return None; } @@ -150,6 +157,16 @@ impl AxVMConfig { &self.image_config } + /// Clears the configured DTB load address when no guest DTB is available. + pub fn clear_dtb_load_gpa(&mut self) { + self.image_config.dtb_load_gpa = None; + } + + /// Sets the DTB load address used as an architecture boot argument. + pub fn set_dtb_load_gpa(&mut self, dtb_load_gpa: GuestPhysAddr) { + self.image_config.dtb_load_gpa = Some(dtb_load_gpa); + } + /// Returns whether VM images are loaded from the host filesystem. pub fn images_loaded_from_filesystem(&self) -> bool { self.image_config.loaded_from_filesystem @@ -215,7 +232,7 @@ impl AxVMConfig { /// Removes passthrough device from the VM configuration. pub fn remove_pass_through_device(&mut self, device: PassThroughDeviceConfig) { - self.pass_through_devices.retain(|d| d == &device); + self.pass_through_devices.retain(|d| d != &device); } /// Clears all passthrough devices from the VM configuration. diff --git a/virtualization/axvm/src/lib.rs b/virtualization/axvm/src/lib.rs index 61a5868c45..db41cf313c 100644 --- a/virtualization/axvm/src/lib.rs +++ b/virtualization/axvm/src/lib.rs @@ -47,12 +47,12 @@ pub(crate) use host::{ task::{AxTaskExt, AxTaskRef, TaskInner, WaitQueue, WaitQueueHandle as HostWaitQueueHandle}, }; pub use irq::InterruptFabric; -#[cfg(target_arch = "loongarch64")] -pub use manager::inject_vm_vcpu_interrupt; pub use manager::{ AxvmRuntime, current_vcpu_id, current_vm_id, get_vm_by_id, get_vm_list, inject_current_vcpu_interrupt, register_vm, }; +#[cfg(target_arch = "loongarch64")] +pub use manager::{inject_vm_vcpu_external_interrupt, inject_vm_vcpu_interrupt}; pub use task::{AsVCpuTask, VCpuTask}; pub use vm::{AxVCpuRef, AxVM, AxVMRef, VMMemoryRegion, VMStatus}; diff --git a/virtualization/axvm/src/manager.rs b/virtualization/axvm/src/manager.rs index 779acdeafc..ba2b961c1d 100644 --- a/virtualization/axvm/src/manager.rs +++ b/virtualization/axvm/src/manager.rs @@ -99,6 +99,36 @@ pub fn inject_vm_vcpu_interrupt(vm_id: VMId, vcpu_id: usize, vector: usize) -> A crate::runtime::vcpus::queue_interrupt(vm_id, vcpu_id, vector) } +/// Inject a routed external interrupt into a VM's vCPU. +#[cfg(target_arch = "loongarch64")] +pub fn inject_vm_vcpu_external_interrupt( + vm_id: VMId, + vcpu_id: usize, + vector: usize, + physical_irq: usize, +) -> AxResult { + use crate::AsVCpuTask; + + let current = crate::host::task::current_task(); + if let Some(task) = current.try_as_vcpu_task() + && task.vm().id() == vm_id + && task.vcpu.id() == vcpu_id + { + let Some(vector) = task + .vm() + .loongarch_external_irq_vector(vector, physical_irq) + else { + return Ok(()); + }; + return task + .vcpu + .get_arch_vcpu() + .inject_external_interrupt(vector, physical_irq); + } + + crate::runtime::vcpus::queue_external_interrupt(vm_id, vcpu_id, vector, physical_irq) +} + /// Return the current VM ID from the vCPU currently executing on this CPU. pub fn current_vm_id() -> Option { get_current_vcpu::().map(|vcpu| vcpu.vm_id()) diff --git a/virtualization/axvm/src/runtime/mod.rs b/virtualization/axvm/src/runtime/mod.rs index 183e58cb34..e39d8c0cb7 100644 --- a/virtualization/axvm/src/runtime/mod.rs +++ b/virtualization/axvm/src/runtime/mod.rs @@ -57,11 +57,19 @@ pub fn start() { } // Do not exit until all VMs are stopped. + info!( + "VMM wait enter, running VM count: {}", + RUNNING_VM_COUNT.load(Ordering::Acquire) + ); crate::host::task::wait_queue_wait_until(&VMM, || { let vm_count = RUNNING_VM_COUNT.load(Ordering::Acquire); - debug!("a VM exited, current running VM count: {vm_count}"); + info!("VMM wait condition check, running VM count: {vm_count}"); vm_count == 0 }); + info!( + "VMM wait leave, running VM count: {}", + RUNNING_VM_COUNT.load(Ordering::Acquire) + ); } pub fn add_running_vm_count(count: usize) { diff --git a/virtualization/axvm/src/runtime/vcpus.rs b/virtualization/axvm/src/runtime/vcpus.rs index 531d9908ea..a64394bc4f 100644 --- a/virtualization/axvm/src/runtime/vcpus.rs +++ b/virtualization/axvm/src/runtime/vcpus.rs @@ -27,6 +27,16 @@ use crate::{ const KERNEL_STACK_SIZE: usize = 0x40000; // 256 KiB +#[derive(Clone, Copy, Debug)] +enum PendingInterrupt { + Normal(usize), + #[cfg(target_arch = "loongarch64")] + LoongArchExternal { + vector: usize, + physical_irq: usize, + }, +} + /// A global map that holds the vCPU task state for each VM. static VM_VCPU_TASKS: Mutex>> = Mutex::new(BTreeMap::new()); fn get_vm_vcpus(vm_id: usize) -> Option> { @@ -43,7 +53,7 @@ pub struct VMVCpus { // A map of tasks associated with the VCpus of this VM, keyed by vCPU ID. vcpu_task_list: Mutex>, // Pending virtual interrupts that must be injected by the owning vCPU task. - pending_interrupts: Mutex>>, + pending_interrupts: Mutex>>, /// The number of currently running or halting VCpus. Used to track when the VM is fully /// shutdown. /// @@ -90,11 +100,38 @@ impl VMVCpus { .cloned() .ok_or_else(|| ax_err_type!(NotFound, format!("vCPU {vcpu_id} task not found")))?; let mut pending = self.pending_interrupts.lock(); - pending.entry(vcpu_id).or_default().push(vector); + pending + .entry(vcpu_id) + .or_default() + .push(PendingInterrupt::Normal(vector)); Ok(task.cpu_id() as usize) } - fn drain_pending_interrupts(&self, vcpu_id: usize) -> Vec { + #[cfg(target_arch = "loongarch64")] + fn queue_external_interrupt( + &self, + vcpu_id: usize, + vector: usize, + physical_irq: usize, + ) -> AxResult { + let task = self + .vcpu_task_list + .lock() + .get(&vcpu_id) + .cloned() + .ok_or_else(|| ax_err_type!(NotFound, format!("vCPU {vcpu_id} task not found")))?; + let mut pending = self.pending_interrupts.lock(); + pending + .entry(vcpu_id) + .or_default() + .push(PendingInterrupt::LoongArchExternal { + vector, + physical_irq, + }); + Ok(task.cpu_id() as usize) + } + + fn drain_pending_interrupts(&self, vcpu_id: usize) -> Vec { let mut pending = self.pending_interrupts.lock(); pending .get_mut(&vcpu_id) @@ -222,19 +259,80 @@ pub(crate) fn queue_interrupt(vm_id: usize, vcpu_id: usize, vector: usize) -> Ax Ok(()) } +#[cfg(target_arch = "loongarch64")] +pub(crate) fn queue_external_interrupt( + vm_id: usize, + vcpu_id: usize, + vector: usize, + physical_irq: usize, +) -> AxResult { + let vm = crate::get_vm_by_id(vm_id) + .ok_or_else(|| ax_err_type!(NotFound, format!("VM[{vm_id}] not found")))?; + if matches!( + vm.vm_status(), + crate::VMStatus::Stopping | crate::VMStatus::Stopped + ) { + return Err(ax_err_type!( + BadState, + format!("VM[{vm_id}] is not accepting interrupts") + )); + } + + let vm_vcpus = get_vm_vcpus(vm_id) + .ok_or_else(|| ax_err_type!(NotFound, format!("VM[{vm_id}] vCPU resources not found")))?; + let cpu_id = vm_vcpus.queue_external_interrupt(vcpu_id, vector, physical_irq)?; + vm_vcpus.notify_all(); + crate::host::task::send_ipi(cpu_id); + Ok(()) +} + pub(crate) fn inject_pending_interrupts(vm_id: usize, vcpu_id: usize, vcpu: &VCpuRef) { let Some(vm_vcpus) = get_vm_vcpus(vm_id) else { warn!("VM[{vm_id}] vCPU resources not found, cannot drain VCpu[{vcpu_id}] interrupts"); return; }; - for vector in vm_vcpus.drain_pending_interrupts(vcpu_id) { - trace!("Injecting queued interrupt {vector:#x} into VM[{vm_id}] VCpu[{vcpu_id}]"); - if let Err(err) = vcpu.inject_interrupt(vector) { - warn!( - "Failed to inject queued interrupt {vector:#x} into VM[{vm_id}] VCpu[{vcpu_id}]: \ - {err:?}" - ); + for interrupt in vm_vcpus.drain_pending_interrupts(vcpu_id) { + match interrupt { + PendingInterrupt::Normal(vector) => { + trace!("Injecting queued interrupt {vector:#x} into VM[{vm_id}] VCpu[{vcpu_id}]"); + if let Err(err) = vcpu.inject_interrupt(vector) { + warn!( + "Failed to inject queued interrupt {vector:#x} into VM[{vm_id}] \ + VCpu[{vcpu_id}]: {err:?}" + ); + } + } + #[cfg(target_arch = "loongarch64")] + PendingInterrupt::LoongArchExternal { + vector, + physical_irq, + } => { + let Some(vm) = crate::get_vm_by_id(vm_id) else { + warn!("VM[{vm_id}] not found while injecting queued LoongArch external IRQ"); + continue; + }; + let Some(vector) = vm.loongarch_external_irq_vector(vector, physical_irq) else { + trace!( + "Queued LoongArch external interrupt physical_irq={physical_irq:#x} is \ + masked in VM[{vm_id}]" + ); + continue; + }; + trace!( + "Injecting queued LoongArch external interrupt vector={vector:#x}, \ + physical_irq={physical_irq:#x} into VM[{vm_id}] VCpu[{vcpu_id}]" + ); + if let Err(err) = vcpu + .get_arch_vcpu() + .inject_external_interrupt(vector, physical_irq) + { + warn!( + "Failed to inject queued LoongArch external interrupt vector={vector:#x}, \ + physical_irq={physical_irq:#x} into VM[{vm_id}] VCpu[{vcpu_id}]: {err:?}" + ); + } + } } } } @@ -475,203 +573,221 @@ fn vcpu_run() { super::x86_irq::enable_ioapic_irq_forwarding(&vm, &vcpu); mark_vcpu_running(vm_id); + let mut first_run_logged = false; loop { inject_pending_interrupts(vm_id, vcpu_id, &vcpu); #[cfg(target_arch = "x86_64")] super::x86_irq::drain_pending_ioapic_irqs(&vm, &vcpu); + if !first_run_logged { + info!("VM[{vm_id}] VCpu[{vcpu_id}] entering vm.run_vcpu"); + first_run_logged = true; + } match vm.run_vcpu(vcpu_id) { - Ok(exit_reason) => match exit_reason { - AxVCpuExitReason::Hypercall { nr, args } => { - debug!("Hypercall [{nr}] args {args:x?}"); - use crate::runtime::hvc::HyperCall; - - match HyperCall::new(vm.clone(), nr, args) { - Ok(hypercall) => { - let ret_val = match hypercall.execute() { - Ok(ret_val) => ret_val as isize, - Err(err) => { - warn!("Hypercall [{nr:#x}] failed: {err:?}"); - -1 - } - }; - vcpu.set_return_value(ret_val as usize); - } - Err(err) => { - warn!("Hypercall [{nr:#x}] failed: {err:?}"); + Ok(exit_reason) => { + #[cfg(target_arch = "loongarch64")] + trace!("VM[{vm_id}] VCpu[{vcpu_id}] vm.run_vcpu returned: {exit_reason:?}"); + + match exit_reason { + AxVCpuExitReason::Hypercall { nr, args } => { + debug!("Hypercall [{nr}] args {args:x?}"); + use crate::runtime::hvc::HyperCall; + + match HyperCall::new(vm.clone(), nr, args) { + Ok(hypercall) => { + let ret_val = match hypercall.execute() { + Ok(ret_val) => ret_val as isize, + Err(err) => { + warn!("Hypercall [{nr:#x}] failed: {err:?}"); + -1 + } + }; + vcpu.set_return_value(ret_val as usize); + } + Err(err) => { + warn!("Hypercall [{nr:#x}] failed: {err:?}"); + } } } - } - AxVCpuExitReason::FailEntry { - hardware_entry_failure_reason, - } => { - warn!( - "VM[{vm_id}] VCpu[{vcpu_id}] run failed with exit code \ - {hardware_entry_failure_reason}" - ); - } - AxVCpuExitReason::ExternalInterrupt { vector } => { - debug!("VM[{vm_id}] run VCpu[{vcpu_id}] get irq {vector}"); - - // TODO: maybe move this irq dispatcher to lower layer to accelerate the interrupt handling - #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv64")))] - crate::host::arceos::dispatch_host_irq(vector as usize); - #[cfg(target_arch = "riscv64")] - vcpu.with_current_cpu_set(|| { - crate::host::arceos::dispatch_host_irq(vector as usize); - vcpu.get_arch_vcpu().latch_hvip_from_hw(); - }); - crate::check_timer_events(); - #[cfg(target_arch = "x86_64")] - super::x86_irq::forward_passthrough_irq_from_vmexit( - &vm, - &vcpu, - vector as usize, - ); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); - } - AxVCpuExitReason::PreemptionTimer => { - crate::timer::check_events(); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_due_pit_irq0(&vm, &vcpu); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); - } - AxVCpuExitReason::InterruptEnd { vector: _vector } => { - #[cfg(target_arch = "x86_64")] - if let Some(vector) = _vector { - super::x86_irq::inject_pending_ioapic_irq_after_eoi(&vm, &vcpu, vector); + AxVCpuExitReason::FailEntry { + hardware_entry_failure_reason, + } => { + warn!( + "VM[{vm_id}] VCpu[{vcpu_id}] run failed with exit code \ + {hardware_entry_failure_reason}" + ); } - } - AxVCpuExitReason::Halt => { - debug!("VM[{vm_id}] run VCpu[{vcpu_id}] Halt"); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_due_pit_irq0(&vm, &vcpu); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); - #[cfg(target_arch = "x86_64")] - continue; - #[cfg(not(target_arch = "x86_64"))] - wait(&vm_vcpus) - } - AxVCpuExitReason::Idle => { - trace!("VM[{vm_id}] run VCpu[{vcpu_id}] Idle"); - #[cfg(target_arch = "loongarch64")] - { + AxVCpuExitReason::ExternalInterrupt { vector } => { + debug!("VM[{vm_id}] run VCpu[{vcpu_id}] get irq {vector}"); + + // TODO: maybe move this irq dispatcher to lower layer to accelerate the interrupt handling + #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv64")))] + crate::host::arceos::dispatch_host_irq(vector as usize); + #[cfg(target_arch = "riscv64")] + vcpu.with_current_cpu_set(|| { + crate::host::arceos::dispatch_host_irq(vector as usize); + vcpu.get_arch_vcpu().latch_hvip_from_hw(); + }); crate::check_timer_events(); - if vcpu.get_arch_vcpu().has_enabled_pending_interrupt() { - continue; - } - let idle_timeout = vcpu.get_arch_vcpu().idle_wait_timeout(); - ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(true); - ax_std::os::arceos::modules::ax_hal::asm::enable_irqs(); - ax_std::os::arceos::modules::ax_hal::time::busy_wait(idle_timeout); - ax_std::os::arceos::modules::ax_hal::asm::disable_irqs(); - ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(false); + #[cfg(target_arch = "x86_64")] + super::x86_irq::forward_passthrough_irq_from_vmexit( + &vm, + &vcpu, + vector as usize, + ); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); } - #[cfg(not(target_arch = "loongarch64"))] - { - crate::check_timer_events(); + AxVCpuExitReason::PreemptionTimer => { + crate::timer::check_events(); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_due_pit_irq0(&vm, &vcpu); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); } - } - AxVCpuExitReason::Nothing => {} - AxVCpuExitReason::CpuDown { _state } => { - warn!("VM[{vm_id}] run VCpu[{vcpu_id}] CpuDown state {_state:#x}"); - wait(&vm_vcpus) - } - AxVCpuExitReason::CpuUp { - target_cpu, - entry_point, - arg, - } => { - info!( - "VM[{vm_id}]'s VCpu[{vcpu_id}] try to boot target_cpu [{target_cpu}] \ - entry_point={entry_point:x} arg={arg:#x}" - ); - - // Get the mapping relationship between all vCPUs and physical CPUs from the configuration - let vcpu_mappings = vm.get_vcpu_affinities_pcpu_ids(); - - // Find the vCPU ID corresponding to the physical ID - let Some(target_vcpu_id) = - vcpu_mappings.iter().find_map(|(vcpu_id, _, phys_id)| { - (*phys_id == target_cpu as usize).then_some(*vcpu_id) - }) - else { - warn!("Physical CPU ID {target_cpu} not found in VM configuration"); - vcpu.set_return_value(usize::MAX); + AxVCpuExitReason::InterruptEnd { vector: _vector } => { + #[cfg(target_arch = "x86_64")] + if let Some(vector) = _vector { + super::x86_irq::inject_pending_ioapic_irq_after_eoi(&vm, &vcpu, vector); + } + } + AxVCpuExitReason::Halt => { + debug!("VM[{vm_id}] run VCpu[{vcpu_id}] Halt"); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_due_pit_irq0(&vm, &vcpu); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); + #[cfg(target_arch = "x86_64")] continue; - }; - - match vcpu_on(vm.clone(), target_vcpu_id, entry_point, arg as _) { - Ok(()) => { - #[cfg(not(target_arch = "riscv64"))] - vcpu.set_gpr(0, 0); - #[cfg(target_arch = "riscv64")] - vcpu.set_gpr(RiscvGprIndex::A0 as usize, 0); + #[cfg(not(target_arch = "x86_64"))] + wait(&vm_vcpus) + } + AxVCpuExitReason::Idle => { + trace!("VM[{vm_id}] run VCpu[{vcpu_id}] Idle"); + #[cfg(target_arch = "loongarch64")] + { + crate::check_timer_events(); + if vcpu.get_arch_vcpu().has_enabled_pending_interrupt() { + trace!( + "VM[{vm_id}] VCpu[{vcpu_id}] skips idle wait because guest \ + has enabled pending interrupt" + ); + continue; + } + let idle_timeout = vcpu.get_arch_vcpu().idle_wait_timeout(); + trace!( + "VM[{vm_id}] VCpu[{vcpu_id}] host idle wait for {idle_timeout:?}" + ); + ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(true); + ax_std::os::arceos::modules::ax_hal::asm::enable_irqs(); + ax_std::os::arceos::modules::ax_hal::time::busy_wait(idle_timeout); + ax_std::os::arceos::modules::ax_hal::asm::disable_irqs(); + ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(false); + } + #[cfg(not(target_arch = "loongarch64"))] + { + crate::check_timer_events(); } - Err(err) => { - warn!("Failed to boot VM[{vm_id}] VCpu[{target_vcpu_id}]: {err:?}"); + } + AxVCpuExitReason::Nothing => {} + AxVCpuExitReason::CpuDown { _state } => { + warn!("VM[{vm_id}] run VCpu[{vcpu_id}] CpuDown state {_state:#x}"); + wait(&vm_vcpus) + } + AxVCpuExitReason::CpuUp { + target_cpu, + entry_point, + arg, + } => { + info!( + "VM[{vm_id}]'s VCpu[{vcpu_id}] try to boot target_cpu [{target_cpu}] \ + entry_point={entry_point:x} arg={arg:#x}" + ); + + // Get the mapping relationship between all vCPUs and physical CPUs from the configuration + let vcpu_mappings = vm.get_vcpu_affinities_pcpu_ids(); + + // Find the vCPU ID corresponding to the physical ID + let Some(target_vcpu_id) = + vcpu_mappings.iter().find_map(|(vcpu_id, _, phys_id)| { + (*phys_id == target_cpu as usize).then_some(*vcpu_id) + }) + else { + warn!("Physical CPU ID {target_cpu} not found in VM configuration"); vcpu.set_return_value(usize::MAX); + continue; + }; + + match vcpu_on(vm.clone(), target_vcpu_id, entry_point, arg as _) { + Ok(()) => { + #[cfg(not(target_arch = "riscv64"))] + vcpu.set_gpr(0, 0); + #[cfg(target_arch = "riscv64")] + vcpu.set_gpr(RiscvGprIndex::A0 as usize, 0); + } + Err(err) => { + warn!("Failed to boot VM[{vm_id}] VCpu[{target_vcpu_id}]: {err:?}"); + vcpu.set_return_value(usize::MAX); + } } } - } - AxVCpuExitReason::SystemDown => { - warn!("VM[{vm_id}] run VCpu[{vcpu_id}] SystemDown"); - if let Err(err) = vm.shutdown() { - warn!("VM[{vm_id}] shutdown failed: {err:?}"); + AxVCpuExitReason::SystemDown => { + warn!("VM[{vm_id}] run VCpu[{vcpu_id}] SystemDown"); + if let Err(err) = vm.shutdown() { + warn!("VM[{vm_id}] shutdown failed: {err:?}"); + } + // Notify all vCPUs to wake up to check the shutdown flag + notify_all_vcpus(vm_id); } - // Notify all vCPUs to wake up to check the shutdown flag - notify_all_vcpus(vm_id); - } - AxVCpuExitReason::SendIPI { - target_cpu, - target_cpu_aux, - send_to_all, - send_to_self, - vector, - } => { - debug!( - "VM[{vm_id}] run VCpu[{vcpu_id}] SendIPI, target_cpu={target_cpu:#x}, \ - target_cpu_aux={target_cpu_aux:#x}, vector={vector}", - ); - let targets = ipi_targets( - &vm, - vcpu_id, + AxVCpuExitReason::SendIPI { target_cpu, target_cpu_aux, send_to_all, send_to_self, - ); - if targets.is_empty() { - warn!( - "VM[{vm_id}] SendIPI has no target: target_cpu={target_cpu:#x}, \ - target_cpu_aux={target_cpu_aux:#x}" + vector, + } => { + debug!( + "VM[{vm_id}] run VCpu[{vcpu_id}] SendIPI, target_cpu={target_cpu:#x}, \ + target_cpu_aux={target_cpu_aux:#x}, vector={vector}", ); - continue; - } + let targets = ipi_targets( + &vm, + vcpu_id, + target_cpu, + target_cpu_aux, + send_to_all, + send_to_self, + ); + if targets.is_empty() { + warn!( + "VM[{vm_id}] SendIPI has no target: target_cpu={target_cpu:#x}, \ + target_cpu_aux={target_cpu_aux:#x}" + ); + continue; + } - if targets.get(vcpu_id) { - crate::inject_current_vcpu_interrupt(vector as _) - .expect("failed to inject self IPI into current vCPU"); + if targets.get(vcpu_id) { + crate::inject_current_vcpu_interrupt(vector as _) + .expect("failed to inject self IPI into current vCPU"); + } + let mut remote_targets = targets; + remote_targets.set(vcpu_id, false); + if !remote_targets.is_empty() + && let Err(err) = + vm.inject_interrupt_to_vcpu(remote_targets, vector as _) + { + warn!( + "Failed to inject interrupt {vector} to VM[{vm_id}] targets \ + {remote_targets:?}: {err:?}" + ); + } } - let mut remote_targets = targets; - remote_targets.set(vcpu_id, false); - if !remote_targets.is_empty() - && let Err(err) = vm.inject_interrupt_to_vcpu(remote_targets, vector as _) - { - warn!( - "Failed to inject interrupt {vector} to VM[{vm_id}] targets \ - {remote_targets:?}: {err:?}" - ); + e => { + warn!("VM[{vm_id}] run VCpu[{vcpu_id}] unhandled vmexit: {e:?}"); } } - e => { - warn!("VM[{vm_id}] run VCpu[{vcpu_id}] unhandled vmexit: {e:?}"); - } - }, + } Err(err) => { error!("VM[{vm_id}] run VCpu[{vcpu_id}] get error {err:?}"); if let Err(err) = vm.shutdown() { diff --git a/virtualization/axvmconfig/src/lib.rs b/virtualization/axvmconfig/src/lib.rs index e2edb0b47d..3ebc22ae91 100644 --- a/virtualization/axvmconfig/src/lib.rs +++ b/virtualization/axvmconfig/src/lib.rs @@ -590,14 +590,14 @@ impl VMKernelConfig { match self.effective_boot_protocol() { VMBootProtocol::Uefi => { - if arch != "x86_64" { + if !matches!(arch, "x86_64" | "loongarch64") { warn!( - "boot_protocol=uefi is only supported on x86_64; rejecting config on \ - {arch}" + "boot_protocol=uefi is only supported on x86_64 and loongarch64; \ + rejecting config on {arch}" ); return Err(ax_errno::ax_err_type!( InvalidInput, - "UEFI boot is only supported on x86_64" + "UEFI boot is only supported on x86_64 and loongarch64" )); } if self.boot_firmware_path().is_none() { diff --git a/virtualization/axvmconfig/src/test.rs b/virtualization/axvmconfig/src/test.rs index 976f862258..acc8f9f0b1 100644 --- a/virtualization/axvmconfig/src/test.rs +++ b/virtualization/axvmconfig/src/test.rs @@ -191,7 +191,7 @@ fn test_boot_config_validation_requires_uefi_inputs() { } #[test] -fn test_boot_config_validation_rejects_x86_firmware_protocols_on_other_arches() { +fn test_boot_config_validation_rejects_unsupported_firmware_protocols_on_other_arches() { let uefi_config = crate::VMKernelConfig { enable_bios: true, boot_protocol: Some(VMBootProtocol::Uefi), @@ -213,7 +213,7 @@ fn test_boot_config_validation_rejects_x86_firmware_protocols_on_other_arches() assert!( uefi_config .validate_boot_config_for_arch("loongarch64") - .is_err() + .is_ok() ); assert!(uefi_config.validate_boot_config_for_arch("x86_64").is_ok()); @@ -258,7 +258,10 @@ fn test_emu_dev_type_from_usize() { ); } - assert_eq!(EmulatedDeviceType::from_usize(0x3), None); + assert_eq!( + EmulatedDeviceType::from_usize(0x3), + Some(EmulatedDeviceType::FwCfg) + ); } #[test] @@ -266,7 +269,7 @@ fn test_rejects_unknown_emulated_device_type() { const EXAMPLE_DEVICE_CONFIG: &str = r#" passthrough_devices = [] emu_devices = [ - ["bad-device", 0x1000, 0x1000, 0, 0x3, []], + ["bad-device", 0x1000, 0x1000, 0, 0x4, []], ] "#; @@ -367,6 +370,7 @@ fn test_emulated_device_type_removable() { assert!(!EmulatedDeviceType::Dummy.removable()); assert!(!EmulatedDeviceType::Console.removable()); + assert!(!EmulatedDeviceType::FwCfg.removable()); assert!(!EmulatedDeviceType::IVCChannel.removable()); assert!(!EmulatedDeviceType::GPPTDistributor.removable()); assert!(!EmulatedDeviceType::GPPTITS.removable()); @@ -384,6 +388,7 @@ fn test_emulated_device_type_display() { "interrupt controller" ); assert_eq!(format!("{}", EmulatedDeviceType::Console), "console"); + assert_eq!(format!("{}", EmulatedDeviceType::FwCfg), "fw_cfg"); assert_eq!(format!("{}", EmulatedDeviceType::IVCChannel), "ivc channel"); assert_eq!( format!("{}", EmulatedDeviceType::GPPTRedistributor), diff --git a/virtualization/loongarch_vcpu/src/context_frame.rs b/virtualization/loongarch_vcpu/src/context_frame.rs index 7e85cb8815..bb50c8b191 100644 --- a/virtualization/loongarch_vcpu/src/context_frame.rs +++ b/virtualization/loongarch_vcpu/src/context_frame.rs @@ -111,6 +111,17 @@ pub struct LoongArchContextFrame { pub host_badi: usize, pub host_tlbrbadv: usize, pub host_tlbrera: usize, + pub host_pgdl: usize, + pub host_pgdh: usize, + pub host_pwcl: usize, + pub host_pwch: usize, + pub host_stlbps: usize, + pub host_tlbrentry: usize, + pub host_asid: usize, + pub host_eentry: usize, + pub host_ecfg: usize, + pub guest_tlbrentry: usize, + pub guest_eentry: usize, } impl LoongArchContextFrame { @@ -134,6 +145,32 @@ impl LoongArchContextFrame { } } + pub fn gpr(&self, index: usize) -> usize { + match index { + 0 => 0, + 1..=31 => self.x[index], + _ => panic!("invalid general-purpose register index {index}"), + } + } + + pub fn guest_exception_pc(&self) -> usize { + if self.host_tlbrera & 0x1 != 0 { + self.host_tlbrera & !0x1 + } else if self.host_era != 0 { + self.host_era + } else { + self.gcsr_era + } + } + + pub fn advance_guest_pc(&mut self) { + let next_pc = self.guest_exception_pc().wrapping_add(4); + self.sepc = next_pc; + self.gcsr_era = next_pc; + self.host_era = next_pc; + self.host_tlbrera = next_pc; + } + pub fn get_a0(&self) -> usize { self.x[4] } diff --git a/virtualization/loongarch_vcpu/src/exception.S b/virtualization/loongarch_vcpu/src/exception.S index 922511727c..92ac0add40 100644 --- a/virtualization/loongarch_vcpu/src/exception.S +++ b/virtualization/loongarch_vcpu/src/exception.S @@ -5,23 +5,82 @@ .equ CSR_CRMD, 0x0 .equ CSR_PRMD, 0x1 .equ CSR_ECFG, 0x4 +.equ CSR_EENTRY, 0xc +.equ CSR_ASID, 0x18 +.equ CSR_PGDL, 0x19 +.equ CSR_PGDH, 0x1a .equ CSR_BADI, 0x8 .equ CSR_SAVE0, 0x30 .equ CSR_SAVE1, 0x31 .equ CSR_PGD, 0x1b +.equ CSR_PWCL, 0x1c +.equ CSR_PWCH, 0x1d +.equ CSR_STLBPS, 0x1e .equ CSR_TLBRERA, 0x8a +.equ CSR_TLBRENTRY, 0x88 .equ CSR_TLBRSAVE, 0x8b .equ CSR_TLBRELO0, 0x8c .equ CSR_TLBRELO1, 0x8d .equ CSR_TLBREHI, 0x8e .equ CSR_TLBRPRMD, 0x8f .equ CSR_GSTAT_PVM, 0x2 -.equ CSR_PRMD_PIE, 0x4 .equ CSR_TLBRPRMD_PGM, 0x8 .equ CSR_GTLBC_TGID, 0xff0000 -.equ CSR_GTLBC_TGID0, 0x0 .equ CSR_TIMER_IE, 0x800 .equ CSR_CRMD_IE, 0x4 +.equ STAGE2_PWCL, 0x13e4d52c +.equ STAGE2_PWCH, 0x267 +.equ STAGE2_STLBPS, 12 +.equ STAGE2_ASID, 1 +.equ ECFG_VS_MASK, 0x70000 +.equ ECFG_VS_5, 0x50000 + +.macro SWITCH_TO_GUEST_TRANSLATION + ld.d $t0, $sp, {guest_tlbrentry} + csrwr $t0, CSR_TLBRENTRY + ld.d $t0, $sp, {guest_eentry} + csrwr $t0, CSR_EENTRY + csrrd $t1, CSR_ECFG + li.d $t0, ECFG_VS_MASK + andn $t1, $t1, $t0 + li.d $t0, ECFG_VS_5 + or $t1, $t1, $t0 + csrwr $t1, CSR_ECFG + + li.d $t0, STAGE2_PWCL + csrwr $t0, CSR_PWCL + li.d $t0, STAGE2_PWCH + csrwr $t0, CSR_PWCH + li.d $t0, STAGE2_STLBPS + csrwr $t0, CSR_STLBPS + csrwr $a1, CSR_PGDL + csrwr $a1, CSR_PGDH + li.d $t0, STAGE2_ASID + csrwr $t0, CSR_ASID + invtlb 0x0, $r0, $r0 +.endm + +.macro RESTORE_HOST_TRANSLATION + ld.d $t0, $sp, {host_eentry} + csrwr $t0, CSR_EENTRY + ld.d $t0, $sp, {host_ecfg} + csrwr $t0, CSR_ECFG + ld.d $t0, $sp, {host_tlbrentry} + csrwr $t0, CSR_TLBRENTRY + ld.d $t0, $sp, {host_asid} + csrwr $t0, CSR_ASID + ld.d $t0, $sp, {host_pwcl} + csrwr $t0, CSR_PWCL + ld.d $t0, $sp, {host_pwch} + csrwr $t0, CSR_PWCH + ld.d $t0, $sp, {host_stlbps} + csrwr $t0, CSR_STLBPS + ld.d $t0, $sp, {host_pgdl} + csrwr $t0, CSR_PGDL + ld.d $t0, $sp, {host_pgdh} + csrwr $t0, CSR_PGDH + invtlb 0x0, $r0, $r0 +.endm .macro SAVE_GUEST_REGS st.d $r0, $sp, 0 @@ -225,25 +284,16 @@ li.d $t0, CSR_CRMD_IE csrxchg $zero, $t0, CSR_CRMD - li.d $t0, CSR_PRMD_PIE - csrwr $t0, CSR_PRMD + csrwr $zero, CSR_PRMD csrrd $t1, CSR_TLBRERA li.d $t0, -2 and $t1, $t1, $t0 csrwr $t1, CSR_TLBRERA - csrrd $t1, CSR_GTLBC - li.d $t0, CSR_GTLBC_TGID - andn $t1, $t1, $t0 - ori $t1, $t1, CSR_GTLBC_TGID0 - csrwr $t1, CSR_GTLBC - - li.d $t0, CSR_GSTAT_PVM - csrxchg $t0, $t0, CSR_GSTAT - csrrd $t0, CSR_ECFG - ori $t0, $t0, CSR_TIMER_IE + li.d $t1, CSR_TIMER_IE + andn $t0, $t0, $t1 csrwr $t0, CSR_ECFG .endm @@ -391,6 +441,9 @@ and $t1, $t1, $t0 csrwr $t1, CSR_TLBRPRMD + li.d $t0, CSR_GSTAT_PVM + csrxchg $t0, $t0, CSR_GSTAT + ld.d $r1, $sp, 8 ld.d $r2, $sp, 16 ld.d $r4, $sp, 32 @@ -428,9 +481,10 @@ .global _run_guest _run_guest: move $t1, $ra - addi.d $t0, $a0, 792 + addi.d $t0, $a0, {ctx_size} csrwr $t0, 0x33 move $sp, $a0 + SWITCH_TO_GUEST_TRANSLATION PREPARE_GUEST_ENTRY RESTORE_GUEST_REGS ertn @@ -467,9 +521,10 @@ _guest_tlb_refill_vector: DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 csrwr $sp, 0x502 csrrd $sp, 0x33 - addi.d $sp, $sp, -792 + addi.d $sp, $sp, -{ctx_size} SAVE_GUEST_REGS ENTER_HOST_MODE + RESTORE_HOST_TRANSLATION li.d $a0, 0 b _guest_exit @@ -604,9 +659,10 @@ _irq_handler_vector: DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 csrwr $sp, 0x502 csrrd $sp, 0x33 - addi.d $sp, $sp, -792 + addi.d $sp, $sp, -{ctx_size} SAVE_GUEST_REGS ENTER_HOST_MODE + RESTORE_HOST_TRANSLATION li.d $a0, 1 b _guest_exit @@ -615,9 +671,10 @@ _sync_handler_vector: DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 csrwr $sp, 0x502 csrrd $sp, 0x33 - addi.d $sp, $sp, -792 + addi.d $sp, $sp, -{ctx_size} SAVE_GUEST_REGS ENTER_HOST_MODE + RESTORE_HOST_TRANSLATION li.d $a0, 0 b _guest_exit @@ -626,8 +683,9 @@ _hvc_handler_vector: DISABLE_TIMER_IRQ_WITH_SAVED_GUEST_T0_T1 csrwr $sp, 0x502 csrrd $sp, 0x33 - addi.d $sp, $sp, -792 + addi.d $sp, $sp, -{ctx_size} SAVE_GUEST_REGS ENTER_HOST_MODE + RESTORE_HOST_TRANSLATION li.d $a0, 0 b _guest_exit diff --git a/virtualization/loongarch_vcpu/src/exception.rs b/virtualization/loongarch_vcpu/src/exception.rs index e46a782e64..dc04012649 100644 --- a/virtualization/loongarch_vcpu/src/exception.rs +++ b/virtualization/loongarch_vcpu/src/exception.rs @@ -1,5 +1,6 @@ use alloc::boxed::Box; use core::{ + mem::offset_of, sync::atomic::{AtomicUsize, Ordering}, time::Duration, }; @@ -40,6 +41,7 @@ const CSR_ESTAT: usize = 0x5; const CSR_ERA: usize = 0x6; const CSR_BADV: usize = 0x7; const CSR_BADI: usize = 0x8; +const CSR_BADI_U16: u16 = 0x8; const CSR_EENTRY: usize = 0xc; const CSR_TLBIDX: usize = 0x10; const CSR_TLBEHI: usize = 0x11; @@ -95,21 +97,88 @@ const GUEST_RAM_END: usize = QEMU_VIRT_MMIO_START; const EIOINTC_ISR_BASE: usize = 0x1800; const EIOINTC_ISR_REG_COUNT: usize = 4; const EIOINTC_ISR_END: usize = EIOINTC_ISR_BASE + EIOINTC_ISR_REG_COUNT * 8; +const EIOINTC_VECTOR_COUNT: usize = EIOINTC_ISR_REG_COUNT * 64; +const EIOINTC_HWI_BASE: usize = INT_HWI0; +const EIOINTC_NODEMAP_BASE: usize = 0x14a0; +const EIOINTC_NODEMAP_END: usize = 0x14c0; +const EIOINTC_IPMAP_BASE: usize = 0x14c0; +const EIOINTC_IPMAP_END: usize = 0x14c8; +const EIOINTC_ENABLE_BASE: usize = 0x1600; +const EIOINTC_ENABLE_END: usize = 0x1620; +const EIOINTC_BOUNCE_BASE: usize = 0x1680; +const EIOINTC_BOUNCE_END: usize = 0x16a0; +const EIOINTC_ISR_COMPAT_BASE: usize = 0x1700; +const EIOINTC_ISR_COMPAT_END: usize = 0x1720; +const EIOINTC_COREMAP_BASE: usize = 0x1c00; +const EIOINTC_COREMAP_END: usize = 0x1d00; +const EIOINTC_GUEST_OWNED_BASE: usize = 0x1400; +const EIOINTC_GUEST_OWNED_END: usize = 0x2000; const MAX_IOCSR_VMS: usize = 16; const MAX_IOCSR_CPUS: usize = 16; const LOONGARCH_IOCSR_IPI_STATUS: usize = 0x1000; const LOONGARCH_IOCSR_IPI_EN: usize = 0x1004; const LOONGARCH_IOCSR_IPI_SET: usize = 0x1008; const LOONGARCH_IOCSR_IPI_CLEAR: usize = 0x100c; +const LOONGARCH_IOCSR_MAIL_BUF0: usize = 0x1020; +const LOONGARCH_IOCSR_MAIL_BUF3: usize = 0x1038; const LOONGARCH_IOCSR_IPI_SEND: usize = 0x1040; +const LOONGARCH_IOCSR_MBUF_SEND: usize = 0x1048; +const LOONGARCH_IOCSR_ANY_SEND: usize = 0x1158; +const LOONGARCH_IOCSR_ANY_SEND_BUF_SHIFT: usize = 32; const IOCSR_SEND_CPU_SHIFT: usize = 16; const IOCSR_SEND_CPU_MASK: usize = 0x3ff; +const IOCSR_SEND_BYTE_MASK_SHIFT: usize = 27; const IOCSR_IPI_ACTION_MASK: usize = 0x1f; +const IOCSR_MBUF_SEND_BOX_SHIFT: usize = 2; +const IOCSR_MBUF_SEND_BUF_SHIFT: usize = 32; +const IOCSR_MBUF_SEND_H32_MASK: usize = 0xffff_ffff_0000_0000; +const IOCSR_MAIL_BUF_COUNT: usize = 4; +const EIOINTC_NODEMAP_WORDS: usize = 8; +const EIOINTC_IPMAP_WORDS: usize = 2; +const EIOINTC_ENABLE_WORDS_PER_VCPU: usize = 8; +const EIOINTC_BOUNCE_WORDS: usize = 8; +const EIOINTC_COREMAP_WORDS: usize = 64; +const EXTIOI_VIRT_FEATURES: usize = 0x4000_0000; +const EXTIOI_VIRT_CONFIG: usize = 0x4000_0004; +const EXTIOI_HAS_VIRT_EXTENSION: usize = 1 << 0; +const EXTIOI_HAS_ENABLE_OPTION: usize = 1 << 1; +const EXTIOI_HAS_INT_ENCODE: usize = 1 << 2; +const EXTIOI_HAS_CPU_ENCODE: usize = 1 << 3; +const EXTIOI_ENABLE_CPU_ENCODE: usize = 1 << 3; static IOCSR_IPI_STATUS_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS] = [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS]; static IOCSR_IPI_ENABLE_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS] = [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS]; +static IOCSR_MAIL_BUF_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * IOCSR_MAIL_BUF_COUNT] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * IOCSR_MAIL_BUF_COUNT]; +static EIOINTC_ISR_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_ISR_REG_COUNT] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_ISR_REG_COUNT]; +static EIOINTC_NODEMAP_WORDS_STORAGE: [AtomicUsize; + MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_NODEMAP_WORDS] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_NODEMAP_WORDS]; +static EIOINTC_IPMAP_WORDS_STORAGE: [AtomicUsize; + MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_IPMAP_WORDS] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_IPMAP_WORDS]; +static EIOINTC_ENABLE_WORDS: [AtomicUsize; + MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_ENABLE_WORDS_PER_VCPU] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_ENABLE_WORDS_PER_VCPU]; +static EIOINTC_BOUNCE_WORDS_STORAGE: [AtomicUsize; + MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_BOUNCE_WORDS] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_BOUNCE_WORDS]; +static EIOINTC_COREMAP_WORDS_STORAGE: [AtomicUsize; + MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_COREMAP_WORDS] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_COREMAP_WORDS]; +static EIOINTC_VIRT_CONFIG_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS] = + [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS]; +static NESTED_FAULT_LOGS: AtomicUsize = AtomicUsize::new(0); +static SYNC_EXIT_LOGS: AtomicUsize = AtomicUsize::new(0); +static IOCSR_EXIT_LOGS: AtomicUsize = AtomicUsize::new(0); +static EIOINTC_TRACE_LOGS: AtomicUsize = AtomicUsize::new(0); +static TARGET_GSPR_LOGS: AtomicUsize = AtomicUsize::new(0); +static TARGET_IOCSR_LOGS: AtomicUsize = AtomicUsize::new(0); +static IDLE_EXIT_LOGS: AtomicUsize = AtomicUsize::new(0); +static GUEST_TIMER_LOGS: AtomicUsize = AtomicUsize::new(0); #[repr(u8)] #[derive(Debug, Clone, Copy, PartialEq, Eq)] @@ -143,13 +212,7 @@ fn is_host_tlb_refill(ctx: &LoongArchContextFrame) -> bool { } fn get_guest_pc(ctx: &LoongArchContextFrame) -> usize { - if is_host_tlb_refill(ctx) { - ctx.host_tlbrera & !0x1 - } else if ctx.host_era != 0 { - ctx.host_era - } else { - ctx.gcsr_era - } + ctx.guest_exception_pc() } fn direct_map_guest_addr_to_gpa(addr: usize) -> usize { @@ -157,6 +220,13 @@ fn direct_map_guest_addr_to_gpa(addr: usize) -> usize { addr & 0x0000_ffff_ffff_ffff } else if matches!(addr >> 44, 0x8..=0xa) { addr & 0x0000_0fff_ffff_ffff + } else if (0xffff_8000_0000..0xffff_c000_0000).contains(&addr) { + let gpa = addr - 0xffff_8000_0000; + if is_known_guest_physical_addr(gpa) { + gpa + } else { + addr + } } else { addr } @@ -213,12 +283,329 @@ fn iocsr_vcpu_index(vm_id: VMId, vcpu_id: VCpuId) -> Option { } } -fn read_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId, addr: usize) -> Option { +fn iocsr_mail_buf_index(vcpu_index: usize, addr: usize) -> Option { + if !(LOONGARCH_IOCSR_MAIL_BUF0..=LOONGARCH_IOCSR_MAIL_BUF3).contains(&addr) + || !(addr - LOONGARCH_IOCSR_MAIL_BUF0).is_multiple_of(8) + { + return None; + } + + Some(vcpu_index * IOCSR_MAIL_BUF_COUNT + (addr - LOONGARCH_IOCSR_MAIL_BUF0) / 8) +} + +fn eiointc_isr_index(vcpu_index: usize, reg: usize) -> usize { + vcpu_index * EIOINTC_ISR_REG_COUNT + reg +} + +fn eiointc_word_index(vcpu_index: usize, words_per_vcpu: usize, word: usize) -> usize { + vcpu_index * words_per_vcpu + word +} + +fn read_atomic_u32_slots( + slots: &[AtomicUsize], + vcpu_index: usize, + words_per_vcpu: usize, + addr: usize, + base: usize, + len: usize, +) -> usize { + let word = (addr - base) >> 2; + let value = slots + .get(eiointc_word_index(vcpu_index, words_per_vcpu, word)) + .map(|slot| slot.load(Ordering::Acquire) as u32 as usize) + .unwrap_or(0); + if len == 8 { + value + | (slots + .get(eiointc_word_index(vcpu_index, words_per_vcpu, word + 1)) + .map(|slot| (slot.load(Ordering::Acquire) as u32 as usize) << 32) + .unwrap_or(0)) + } else { + value + } +} + +fn write_atomic_u32_slots( + slots: &[AtomicUsize], + vcpu_index: usize, + words_per_vcpu: usize, + addr: usize, + base: usize, + len: usize, + value: usize, +) { + let word = (addr - base) >> 2; + if let Some(slot) = slots.get(eiointc_word_index(vcpu_index, words_per_vcpu, word)) { + slot.store(value as u32 as usize, Ordering::Release); + } + if len == 8 + && let Some(slot) = slots.get(eiointc_word_index(vcpu_index, words_per_vcpu, word + 1)) + { + slot.store((value >> 32) as u32 as usize, Ordering::Release); + } +} + +fn eiointc_isr_word(vcpu_index: usize, word: usize) -> usize { + EIOINTC_ISR_WORDS + .get(eiointc_isr_index(vcpu_index, word / 2)) + .map(|slot| { + let value = slot.load(Ordering::Acquire); + if word.is_multiple_of(2) { + value as u32 as usize + } else { + (value >> 32) as u32 as usize + } + }) + .unwrap_or(0) +} + +fn clear_eiointc_isr_word(vcpu_index: usize, word: usize, value: usize) { + if let Some(slot) = EIOINTC_ISR_WORDS.get(eiointc_isr_index(vcpu_index, word / 2)) { + let shift = (word % 2) * 32; + let mask = (value as u32 as usize) << shift; + slot.fetch_and(!mask, Ordering::AcqRel); + } +} + +fn read_eiointc_isr_slots(vcpu_index: usize, addr: usize, base: usize, len: usize) -> usize { + let word = (addr - base) >> 2; + let value = eiointc_isr_word(vcpu_index, word); + if len == 8 { + value | (eiointc_isr_word(vcpu_index, word + 1) << 32) + } else { + value + } +} + +fn clear_eiointc_isr_slots(vcpu_index: usize, addr: usize, base: usize, len: usize, value: usize) { + let word = (addr - base) >> 2; + clear_eiointc_isr_word(vcpu_index, word, value); + if len == 8 { + clear_eiointc_isr_word(vcpu_index, word + 1, value >> 32); + } +} + +fn eiointc_enable_word(vcpu_index: usize, word: usize) -> usize { + EIOINTC_ENABLE_WORDS[eiointc_word_index(vcpu_index, EIOINTC_ENABLE_WORDS_PER_VCPU, word)] + .load(Ordering::Acquire) +} + +fn eiointc_ipmap_word(vcpu_index: usize, word: usize) -> usize { + EIOINTC_IPMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_IPMAP_WORDS, word)] + .load(Ordering::Acquire) +} + +fn eiointc_coremap_word(vcpu_index: usize, word: usize) -> usize { + EIOINTC_COREMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_COREMAP_WORDS, word)] + .load(Ordering::Acquire) +} + +fn eiointc_virt_config(vcpu_index: usize) -> usize { + EIOINTC_VIRT_CONFIG_WORDS[vcpu_index].load(Ordering::Acquire) +} + +fn eiointc_group_for_source(vcpu_index: usize, source: usize) -> Option { + let ipmap_index = source >> 7; + let ipmap_byte = (source >> 5) & 0x3; + let ipmap = eiointc_ipmap_word(vcpu_index, ipmap_index); + let pin_mask = (ipmap >> (ipmap_byte * 8)) & 0xff; + if pin_mask == 0 { + None + } else { + Some(pin_mask.trailing_zeros() as usize) + } +} + +fn eiointc_source_targets_vcpu0(vcpu_index: usize, source: usize) -> bool { + let word = source >> 2; + let byte = source & 0x3; + let route = (eiointc_coremap_word(vcpu_index, word) >> (byte * 8)) & 0xff; + + if eiointc_virt_config(vcpu_index) & EXTIOI_ENABLE_CPU_ENCODE != 0 { + route == 0 || route == 1 + } else { + route & 0x1 != 0 + } +} + +fn eiointc_cpu_irq_for_source(vcpu_index: usize, source: usize) -> Option { + let pin = eiointc_group_for_source(vcpu_index, source)?; + if !eiointc_source_targets_vcpu0(vcpu_index, source) { + return None; + } + + if pin <= INT_HWI7 - INT_HWI0 { + Some(INT_HWI0 + pin) + } else { + None + } +} + +fn guest_eiointc_pending_hwi(vcpu_index: usize) -> Option { + for word in 0..EIOINTC_ENABLE_WORDS_PER_VCPU { + let pending = eiointc_isr_word(vcpu_index, word) & eiointc_enable_word(vcpu_index, word); + if pending == 0 { + continue; + } + for bit in 0..u32::BITS as usize { + if pending & (1usize << bit) != 0 { + let source = word * u32::BITS as usize + bit; + if let Some(hwi) = eiointc_cpu_irq_for_source(vcpu_index, source) { + return Some(hwi); + } + } + } + } + None +} + +fn update_guest_eiointc_irq(ctx: &mut LoongArchContextFrame, vcpu_index: usize) { + let hwi_bits = HWI_MASK; + if let Some(hwi) = guest_eiointc_pending_hwi(vcpu_index) { + ctx.gcsr_estat = (ctx.gcsr_estat & !hwi_bits) | (1usize << hwi); + crate::registers::set_hwi_interrupts(1usize << hwi); + } else { + ctx.gcsr_estat &= !hwi_bits; + crate::registers::set_hwi_interrupts(0); + } +} + +pub(crate) fn init_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId) { + let Some(vcpu_index) = iocsr_vcpu_index(vm_id, vcpu_id) else { + return; + }; + + for word in 0..EIOINTC_NODEMAP_WORDS { + let value = ((1usize << (word * 2 + 1)) << 16) | (1usize << (word * 2)); + EIOINTC_NODEMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_NODEMAP_WORDS, word)] + .store(value as u32 as usize, Ordering::Release); + } + for word in 0..EIOINTC_ENABLE_WORDS_PER_VCPU { + EIOINTC_ENABLE_WORDS[eiointc_word_index(vcpu_index, EIOINTC_ENABLE_WORDS_PER_VCPU, word)] + .store(u32::MAX as usize, Ordering::Release); + EIOINTC_BOUNCE_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_BOUNCE_WORDS, word)] + .store(u32::MAX as usize, Ordering::Release); + } + for word in 0..EIOINTC_IPMAP_WORDS { + EIOINTC_IPMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_IPMAP_WORDS, word)] + .store(0x0101_0101, Ordering::Release); + } + for word in 0..EIOINTC_COREMAP_WORDS { + EIOINTC_COREMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_COREMAP_WORDS, word)] + .store(0x0101_0101, Ordering::Release); + } +} + +fn iocsr_access_len_from_ty(ty: usize) -> usize { + match ty { + 0 | 4 => 1, + 1 | 5 => 2, + 2 | 6 => 4, + 3 | 7 => 8, + _ => 0, + } +} + +pub(crate) fn inject_guest_eiointc_vector( + vm_id: VMId, + vcpu_id: VCpuId, + vector: usize, +) -> Option { + if vector >= EIOINTC_VECTOR_COUNT { + return None; + } + + let vcpu_index = iocsr_vcpu_index(vm_id, vcpu_id)?; + let reg = vector / 64; + let bit = vector % 64; + let new = EIOINTC_ISR_WORDS[eiointc_isr_index(vcpu_index, reg)] + .fetch_or(1usize << bit, Ordering::AcqRel) + | (1usize << bit); + log_eiointc_trace("inject", vm_id, vcpu_id, reg, vector, new); + eiointc_cpu_irq_for_source(vcpu_index, vector).or(Some(EIOINTC_HWI_BASE + reg)) +} + +fn read_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId, addr: usize, len: usize) -> Option { let index = iocsr_vcpu_index(vm_id, vcpu_id)?; match addr { LOONGARCH_IOCSR_IPI_STATUS => Some(IOCSR_IPI_STATUS_WORDS[index].load(Ordering::Acquire)), LOONGARCH_IOCSR_IPI_EN => Some(IOCSR_IPI_ENABLE_WORDS[index].load(Ordering::Acquire)), LOONGARCH_IOCSR_IPI_SET | LOONGARCH_IOCSR_IPI_CLEAR | LOONGARCH_IOCSR_IPI_SEND => Some(0), + LOONGARCH_IOCSR_MAIL_BUF0..=LOONGARCH_IOCSR_MAIL_BUF3 => iocsr_mail_buf_index(index, addr) + .map(|mail_index| IOCSR_MAIL_BUF_WORDS[mail_index].load(Ordering::Acquire)), + LOONGARCH_IOCSR_MBUF_SEND => Some(0), + LOONGARCH_IOCSR_ANY_SEND => Some(0), + EXTIOI_VIRT_FEATURES => Some( + EXTIOI_HAS_VIRT_EXTENSION + | EXTIOI_HAS_ENABLE_OPTION + | EXTIOI_HAS_INT_ENCODE + | EXTIOI_HAS_CPU_ENCODE, + ), + EXTIOI_VIRT_CONFIG => Some(EIOINTC_VIRT_CONFIG_WORDS[index].load(Ordering::Acquire)), + EIOINTC_NODEMAP_BASE..EIOINTC_NODEMAP_END => Some(read_atomic_u32_slots( + &EIOINTC_NODEMAP_WORDS_STORAGE, + index, + EIOINTC_NODEMAP_WORDS, + addr, + EIOINTC_NODEMAP_BASE, + len, + )), + EIOINTC_IPMAP_BASE..EIOINTC_IPMAP_END => Some(read_atomic_u32_slots( + &EIOINTC_IPMAP_WORDS_STORAGE, + index, + EIOINTC_IPMAP_WORDS, + addr, + EIOINTC_IPMAP_BASE, + len, + )), + EIOINTC_ENABLE_BASE..EIOINTC_ENABLE_END => Some(read_atomic_u32_slots( + &EIOINTC_ENABLE_WORDS, + index, + EIOINTC_ENABLE_WORDS_PER_VCPU, + addr, + EIOINTC_ENABLE_BASE, + len, + )), + EIOINTC_BOUNCE_BASE..EIOINTC_BOUNCE_END => Some(read_atomic_u32_slots( + &EIOINTC_BOUNCE_WORDS_STORAGE, + index, + EIOINTC_BOUNCE_WORDS, + addr, + EIOINTC_BOUNCE_BASE, + len, + )), + EIOINTC_ISR_COMPAT_BASE..EIOINTC_ISR_COMPAT_END => { + let value = read_eiointc_isr_slots(index, addr, EIOINTC_ISR_COMPAT_BASE, len); + log_eiointc_trace( + "read", + vm_id, + vcpu_id, + (addr - EIOINTC_ISR_COMPAT_BASE) / 8, + addr - EIOINTC_ISR_COMPAT_BASE, + value, + ); + Some(value) + } + EIOINTC_ISR_BASE..EIOINTC_ISR_END => { + let value = read_eiointc_isr_slots(index, addr, EIOINTC_ISR_BASE, len); + log_eiointc_trace( + "read", + vm_id, + vcpu_id, + (addr - EIOINTC_ISR_BASE) / 8, + addr - EIOINTC_ISR_BASE, + value, + ); + Some(value) + } + EIOINTC_COREMAP_BASE..EIOINTC_COREMAP_END => Some(read_atomic_u32_slots( + &EIOINTC_COREMAP_WORDS_STORAGE, + index, + EIOINTC_COREMAP_WORDS, + addr, + EIOINTC_COREMAP_BASE, + len, + )), _ => None, } } @@ -228,6 +615,7 @@ fn write_guest_iocsr( vm_id: VMId, vcpu_id: VCpuId, addr: usize, + len: usize, value: usize, ) -> Option { let index = iocsr_vcpu_index(vm_id, vcpu_id)?; @@ -253,9 +641,13 @@ fn write_guest_iocsr( LOONGARCH_IOCSR_IPI_SEND => { let target_cpu = (value >> IOCSR_SEND_CPU_SHIFT) & IOCSR_SEND_CPU_MASK; let action = value & IOCSR_IPI_ACTION_MASK; - if target_cpu == vcpu_id { - IOCSR_IPI_STATUS_WORDS[index].fetch_or(1usize << action, Ordering::AcqRel); - ctx.gcsr_estat |= IPI_BIT; + if let Some(target_index) = iocsr_vcpu_index(vm_id, target_cpu) { + IOCSR_IPI_STATUS_WORDS[target_index].fetch_or(1usize << action, Ordering::AcqRel); + if target_cpu == vcpu_id { + ctx.gcsr_estat |= IPI_BIT; + } else { + host::inject_interrupt(vm_id, target_cpu, INT_IPI); + } } else { log::debug!( "LoongArch guest IOCSR IPI_SEND ignored for unsupported target_cpu={} \ @@ -266,10 +658,173 @@ fn write_guest_iocsr( } Some(AxVCpuExitReason::Nothing) } + LOONGARCH_IOCSR_MAIL_BUF0..=LOONGARCH_IOCSR_MAIL_BUF3 => { + if let Some(mail_index) = iocsr_mail_buf_index(index, addr) { + IOCSR_MAIL_BUF_WORDS[mail_index].store(value, Ordering::Release); + } + Some(AxVCpuExitReason::Nothing) + } + LOONGARCH_IOCSR_MBUF_SEND => { + let target_cpu = (value >> IOCSR_SEND_CPU_SHIFT) & IOCSR_SEND_CPU_MASK; + let mail_word = (value >> IOCSR_MBUF_SEND_BOX_SHIFT) & 0x7; + let mail_buf = mail_word / 2; + let is_high_word = mail_word % 2 == 1; + if mail_buf < IOCSR_MAIL_BUF_COUNT { + if let Some(target_index) = iocsr_vcpu_index(vm_id, target_cpu) { + let mail_index = target_index * IOCSR_MAIL_BUF_COUNT + mail_buf; + let old = IOCSR_MAIL_BUF_WORDS[mail_index].load(Ordering::Acquire); + let new = if is_high_word { + (old & !IOCSR_MBUF_SEND_H32_MASK) | (value & IOCSR_MBUF_SEND_H32_MASK) + } else { + let low = value >> IOCSR_MBUF_SEND_BUF_SHIFT; + (old & IOCSR_MBUF_SEND_H32_MASK) | low + }; + IOCSR_MAIL_BUF_WORDS[mail_index].store(new, Ordering::Release); + } else { + log::debug!( + "LoongArch guest IOCSR MBUF_SEND ignored for unsupported target_cpu={} \ + mail_buf={}", + target_cpu, + mail_buf + ); + } + } + if target_cpu == vcpu_id { + ctx.gcsr_estat |= IPI_BIT; + } + Some(AxVCpuExitReason::Nothing) + } + LOONGARCH_IOCSR_ANY_SEND => { + let target_cpu = (value >> IOCSR_SEND_CPU_SHIFT) & IOCSR_SEND_CPU_MASK; + let target = value & 0xffff; + if target_cpu == vcpu_id { + write_guest_iocsr_send_data( + ctx, + vm_id, + vcpu_id, + target, + value, + LOONGARCH_IOCSR_ANY_SEND_BUF_SHIFT, + ); + } + Some(AxVCpuExitReason::Nothing) + } + EXTIOI_VIRT_CONFIG => { + EIOINTC_VIRT_CONFIG_WORDS[index].store(value, Ordering::Release); + update_guest_eiointc_irq(ctx, index); + Some(AxVCpuExitReason::Nothing) + } + EIOINTC_NODEMAP_BASE..EIOINTC_NODEMAP_END => { + write_atomic_u32_slots( + &EIOINTC_NODEMAP_WORDS_STORAGE, + index, + EIOINTC_NODEMAP_WORDS, + addr, + EIOINTC_NODEMAP_BASE, + len, + value, + ); + Some(AxVCpuExitReason::Nothing) + } + EIOINTC_IPMAP_BASE..EIOINTC_IPMAP_END => { + write_atomic_u32_slots( + &EIOINTC_IPMAP_WORDS_STORAGE, + index, + EIOINTC_IPMAP_WORDS, + addr, + EIOINTC_IPMAP_BASE, + len, + value, + ); + update_guest_eiointc_irq(ctx, index); + Some(AxVCpuExitReason::Nothing) + } + EIOINTC_ENABLE_BASE..EIOINTC_ENABLE_END => { + write_atomic_u32_slots( + &EIOINTC_ENABLE_WORDS, + index, + EIOINTC_ENABLE_WORDS_PER_VCPU, + addr, + EIOINTC_ENABLE_BASE, + len, + value, + ); + update_guest_eiointc_irq(ctx, index); + Some(AxVCpuExitReason::Nothing) + } + EIOINTC_BOUNCE_BASE..EIOINTC_BOUNCE_END => { + write_atomic_u32_slots( + &EIOINTC_BOUNCE_WORDS_STORAGE, + index, + EIOINTC_BOUNCE_WORDS, + addr, + EIOINTC_BOUNCE_BASE, + len, + value, + ); + Some(AxVCpuExitReason::Nothing) + } + EIOINTC_ISR_COMPAT_BASE..EIOINTC_ISR_COMPAT_END => { + clear_eiointc_isr_slots(index, addr, EIOINTC_ISR_COMPAT_BASE, len, value); + update_guest_eiointc_irq(ctx, index); + Some(AxVCpuExitReason::Nothing) + } + EIOINTC_ISR_BASE..EIOINTC_ISR_END if is_eiointc_isr_addr(addr) => { + clear_eiointc_isr_slots(index, addr, EIOINTC_ISR_BASE, len, value); + update_guest_eiointc_irq(ctx, index); + log_eiointc_trace( + "clear", + vm_id, + vcpu_id, + (addr - EIOINTC_ISR_BASE) / 8, + addr - EIOINTC_ISR_BASE, + read_eiointc_isr_slots(index, addr, EIOINTC_ISR_BASE, len), + ); + Some(AxVCpuExitReason::Nothing) + } + EIOINTC_COREMAP_BASE..EIOINTC_COREMAP_END => { + write_atomic_u32_slots( + &EIOINTC_COREMAP_WORDS_STORAGE, + index, + EIOINTC_COREMAP_WORDS, + addr, + EIOINTC_COREMAP_BASE, + len, + value, + ); + update_guest_eiointc_irq(ctx, index); + Some(AxVCpuExitReason::Nothing) + } + EIOINTC_GUEST_OWNED_BASE..EIOINTC_GUEST_OWNED_END => Some(AxVCpuExitReason::Nothing), _ => None, } } +fn write_guest_iocsr_send_data( + ctx: &mut LoongArchContextFrame, + vm_id: VMId, + vcpu_id: VCpuId, + target: usize, + value: usize, + data_shift: usize, +) { + let preserve_mask = (value >> IOCSR_SEND_BYTE_MASK_SHIFT) & 0xf; + let mut data = (value >> data_shift) as u32 as usize; + + if preserve_mask != 0 { + let old = read_guest_iocsr(vm_id, vcpu_id, target, 4).unwrap_or(0) as u32; + let mut byte_mask = 0u32; + for byte in 0..4 { + if preserve_mask & (1 << byte) != 0 { + byte_mask |= 0xff << (byte * 8); + } + } + data = ((old & byte_mask) as usize) | (data & !(byte_mask as usize)); + } + + let _ = write_guest_iocsr(ctx, vm_id, vcpu_id, target, 4, data); +} + fn should_inject_guest_virtual_fault( ctx: &LoongArchContextFrame, badv: usize, @@ -329,14 +884,33 @@ fn inject_guest_regular_exception( ctx.sepc = ctx.gcsr_eentry + ecode * guest_exception_vector_size(ctx); } -fn inject_guest_interrupt(ctx: &mut LoongArchContextFrame, vector: usize) { - let pc = get_guest_pc(ctx); +fn inject_guest_interrupt_at(ctx: &mut LoongArchContextFrame, vector: usize, pc: usize) { ctx.gcsr_prmd = (ctx.gcsr_prmd & !0b111) | (ctx.gcsr_crmd & (CSR_CRMD_PLV_MASK | CSR_CRMD_IE)); ctx.gcsr_era = pc; ctx.gcsr_crmd &= !(CSR_CRMD_PLV_MASK | CSR_CRMD_IE); ctx.sepc = ctx.gcsr_eentry + (64 + vector) * guest_exception_vector_size(ctx); } +pub(crate) fn inject_enabled_pending_interrupt( + ctx: &mut LoongArchContextFrame, + vm_id: VMId, + vcpu_id: VCpuId, +) -> bool { + if let Some(index) = iocsr_vcpu_index(vm_id, vcpu_id) { + update_guest_eiointc_irq(ctx, index); + } + let pending_enabled = ctx.gcsr_estat & ctx.gcsr_ectl & LOCAL_INTERRUPT_MASK; + if ctx.gcsr_eentry != 0 + && ctx.gcsr_crmd & CSR_CRMD_IE != 0 + && let Some(vector) = decode_interrupt_vector(pending_enabled) + { + inject_guest_interrupt_at(ctx, vector, get_guest_pc(ctx)); + true + } else { + false + } +} + fn inject_guest_tlb_refill(ctx: &mut LoongArchContextFrame, badv: usize) { let pc = get_guest_pc(ctx); let page_shift = match ctx.gcsr_stlbps & CSR_TLBREHI_PS_MASK { @@ -370,6 +944,10 @@ fn get_badi(ctx: &LoongArchContextFrame) -> usize { ctx.host_badi } +pub(crate) fn current_badi() -> usize { + unsafe { crate::registers::csr_read::() } +} + fn get_guest_interrupt_status(ctx: &LoongArchContextFrame) -> usize { ctx.host_estat & LOCAL_INTERRUPT_MASK } @@ -402,7 +980,7 @@ fn extract_field(value: usize, offset: usize, width: usize) -> usize { } fn advance_guest_pc(ctx: &mut LoongArchContextFrame) { - ctx.sepc = get_guest_pc(ctx).wrapping_add(4); + ctx.advance_guest_pc(); } fn emulate_cpucfg(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { @@ -620,12 +1198,28 @@ fn register_guest_timer( if init_ticks == 0 { ctx.gcsr_tval = 0; ctx.gcsr_estat |= TIMER_BIT; + if GUEST_TIMER_LOGS.fetch_add(1, Ordering::Relaxed) < 64 { + log::warn!( + "LoongArch guest timer immediate: tcfg={:#x}, estat={:#x}", + ctx.gcsr_tcfg, + ctx.gcsr_estat + ); + } return; } ctx.gcsr_tval = init_ticks as usize; let delay_ns = host::ticks_to_nanos(init_ticks); let deadline_ns = host::current_time_nanos().saturating_add(delay_ns); + if GUEST_TIMER_LOGS.fetch_add(1, Ordering::Relaxed) < 64 { + log::warn!( + "LoongArch guest timer arm: tcfg={:#x}, init_ticks={}, delay_ns={}, deadline_ns={}", + ctx.gcsr_tcfg, + init_ticks, + delay_ns, + deadline_ns + ); + } let token = host::register_timer( Duration::from_nanos(deadline_ns), Box::new(move |_| host::inject_interrupt(vm_id, vcpu_id, INT_TIMER)), @@ -653,6 +1247,16 @@ fn write_guest_timer_csr( ctx.gcsr_ticlr = value; if value & CSR_TICLR_TI != 0 { ctx.gcsr_estat &= !TIMER_BIT; + if GUEST_TIMER_LOGS.fetch_add(1, Ordering::Relaxed) < 64 { + log::warn!( + "LoongArch guest timer clear: tcfg={:#x}, ticlr={:#x}, periodic={}, \ + estat={:#x}", + ctx.gcsr_tcfg, + value, + guest_timer_periodic(ctx), + ctx.gcsr_estat + ); + } if guest_timer_periodic(ctx) { register_guest_timer(ctx, vm_id, vcpu_id, guest_timer_token); } else { @@ -702,13 +1306,38 @@ fn emulate_cacop(ctx: &mut LoongArchContextFrame, _ins: usize) -> AxVCpuExitReas fn emulate_idle(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason { let level = extract_field(ins, 0, 15); - log::debug!("LoongArch guest idle request: level={:#x}", level); let pending_enabled = ctx.gcsr_estat & ctx.gcsr_ectl & LOCAL_INTERRUPT_MASK; + let idle_log_index = IDLE_EXIT_LOGS.fetch_add(1, Ordering::Relaxed); + if idle_log_index < 64 || idle_log_index.is_power_of_two() { + log::trace!( + "LoongArch guest idle: pc={:#x}, level={:#x}, pending_enabled={:#x}, eentry={:#x}, \ + crmd={:#x}, estat={:#x}, ecfg={:#x}, tcfg={:#x}, tval={:#x}, ticlr={:#x}", + get_guest_pc(ctx), + level, + pending_enabled, + ctx.gcsr_eentry, + ctx.gcsr_crmd, + ctx.gcsr_estat, + ctx.gcsr_ectl, + ctx.gcsr_tcfg, + ctx.gcsr_tval, + ctx.gcsr_ticlr, + ); + } if ctx.gcsr_eentry != 0 && ctx.gcsr_crmd & CSR_CRMD_IE != 0 && let Some(vector) = decode_interrupt_vector(pending_enabled) { - inject_guest_interrupt(ctx, vector); + if idle_log_index < 64 || idle_log_index.is_power_of_two() { + log::trace!( + "LoongArch guest idle has pending interrupt: pc={:#x}, vector={}, \ + pending_enabled={:#x}", + get_guest_pc(ctx), + vector, + pending_enabled, + ); + } + inject_guest_interrupt_at(ctx, vector, get_guest_pc(ctx).wrapping_add(4)); return AxVCpuExitReason::Nothing; } advance_guest_pc(ctx); @@ -725,90 +1354,156 @@ fn emulate_iocsr( let rd = extract_field(ins, 0, 5); let rj = extract_field(ins, 5, 5); let rj_value = ctx.x[rj]; + let len = iocsr_access_len_from_ty(ty); + let target_log = |ctx: &LoongArchContextFrame, op: &str, value: usize| { + if (ins == 0x0648_0f78 || get_guest_pc(ctx) == 0x9000_0000_00b9_7fe8) + && TARGET_IOCSR_LOGS.fetch_add(1, Ordering::Relaxed) < 128 + { + log::trace!( + "LoongArch target IOCSR {}: pc={:#x}, ins={:#x}, ty={}, rd={}, rj={}, addr={:#x}, \ + value={:#x}, a0={:#x}, a1={:#x}, a2={:#x}, s1={:#x}, s4={:#x}, crmd={:#x}, \ + estat={:#x}, ecfg={:#x}", + op, + get_guest_pc(ctx), + ins, + ty, + rd, + rj, + rj_value, + value, + ctx.get_a0(), + ctx.get_a1(), + ctx.get_a2(), + ctx.x[23], + ctx.x[20], + ctx.gcsr_crmd, + ctx.gcsr_estat, + ctx.gcsr_ectl, + ); + } + }; + let log_iocsr = |ctx: &LoongArchContextFrame, op: &str, value: usize| { + if IOCSR_EXIT_LOGS.fetch_add(1, Ordering::Relaxed) < 64 { + log::trace!( + "LoongArch IOCSR {}: pc={:#x}, ins={:#x}, ty={}, rd={}, rj={}, addr={:#x}, \ + value={:#x}", + op, + get_guest_pc(ctx), + ins, + ty, + rd, + rj, + rj_value, + value + ); + } + }; match ty { 0 => { - let value = read_guest_iocsr(vm_id, vcpu_id, rj_value).unwrap_or_else(|| { + let value = read_guest_iocsr(vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { let value: usize; unsafe { core::arch::asm!("iocsrrd.b {}, {}", out(reg) value, in(reg) rj_value); } value }); + log_iocsr(ctx, "read.b", value); + target_log(ctx, "read.b", value); ctx.set_gpr(rd, (value as i8) as isize as usize); } 1 => { - let value = read_guest_iocsr(vm_id, vcpu_id, rj_value).unwrap_or_else(|| { + let value = read_guest_iocsr(vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { let value: usize; unsafe { core::arch::asm!("iocsrrd.h {}, {}", out(reg) value, in(reg) rj_value); } value }); + log_iocsr(ctx, "read.h", value); + target_log(ctx, "read.h", value); ctx.set_gpr(rd, (value as i16) as isize as usize); } 2 => { - let value = read_guest_iocsr(vm_id, vcpu_id, rj_value).unwrap_or_else(|| { + let value = read_guest_iocsr(vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { let value: usize; unsafe { core::arch::asm!("iocsrrd.w {}, {}", out(reg) value, in(reg) rj_value); } value }); + log_iocsr(ctx, "read.w", value); + target_log(ctx, "read.w", value); ctx.set_gpr(rd, (value as i32) as isize as usize); } 3 => { - let value = read_guest_iocsr(vm_id, vcpu_id, rj_value).unwrap_or_else(|| { + let value = read_guest_iocsr(vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { let value: usize; unsafe { core::arch::asm!("iocsrrd.d {}, {}", out(reg) value, in(reg) rj_value); } value }); + log_iocsr(ctx, "read.d", value); + target_log(ctx, "read.d", value); ctx.set_gpr(rd, value); } 4 => { if let Some(reason) = - write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, ctx.x[rd] as u8 as usize) + write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, len, ctx.x[rd] as u8 as usize) { advance_guest_pc(ctx); return reason; } else { + log_iocsr(ctx, "write.b", ctx.x[rd] as u8 as usize); unsafe { core::arch::asm!("iocsrwr.b {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); } } } 5 => { - if let Some(reason) = - write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, ctx.x[rd] as u16 as usize) - { + if let Some(reason) = write_guest_iocsr( + ctx, + vm_id, + vcpu_id, + rj_value, + len, + ctx.x[rd] as u16 as usize, + ) { advance_guest_pc(ctx); return reason; } else { + log_iocsr(ctx, "write.h", ctx.x[rd] as u16 as usize); unsafe { core::arch::asm!("iocsrwr.h {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); } } } 6 => { - if let Some(reason) = - write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, ctx.x[rd] as u32 as usize) - { + if let Some(reason) = write_guest_iocsr( + ctx, + vm_id, + vcpu_id, + rj_value, + len, + ctx.x[rd] as u32 as usize, + ) { advance_guest_pc(ctx); return reason; } else { + log_iocsr(ctx, "write.w", ctx.x[rd] as u32 as usize); unsafe { core::arch::asm!("iocsrwr.w {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); } } } 7 => { - if let Some(reason) = write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, ctx.x[rd]) { + if let Some(reason) = write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, len, ctx.x[rd]) { advance_guest_pc(ctx); return reason; } else { let is_eiointc_complete = is_eiointc_isr_addr(rj_value); + log_iocsr(ctx, "write.d", ctx.x[rd]); unsafe { core::arch::asm!("iocsrwr.d {}, {}", in(reg) ctx.x[rd], in(reg) rj_value); } @@ -824,6 +1519,25 @@ fn emulate_iocsr( AxVCpuExitReason::Nothing } +fn log_eiointc_trace( + op: &str, + vm_id: VMId, + vcpu_id: VCpuId, + reg: usize, + vector_hint: usize, + value: usize, +) { + if EIOINTC_TRACE_LOGS.fetch_add(1, Ordering::Relaxed) < 128 { + log::trace!( + "LoongArch guest EIOINTC {op}: VM[{vm_id}] VCpu[{vcpu_id}] reg={}, vector_hint={}, \ + isr={:#x}", + reg, + vector_hint, + value + ); + } +} + fn emulate_gspr( ctx: &mut LoongArchContextFrame, vm_id: VMId, @@ -846,6 +1560,28 @@ fn emulate_gspr( let shift = 32 - len; ((ins >> shift) & ((1usize << len) - 1)) == opcode }; + let pc = get_guest_pc(ctx); + if (0x9000_0000_0159_0000..0x9000_0000_015a_0000).contains(&pc) + && TARGET_GSPR_LOGS.fetch_add(1, Ordering::Relaxed) < 64 + { + log::trace!( + "LoongArch target GSPR: pc={:#x}, ins={:#x}, rd={}, rj={}, csr={:#x}, iocsr_ty={}, \ + a0={:#x}, a1={:#x}, a2={:#x}, estat={:#x}, ecfg={:#x}, tcfg={:#x}, tval={:#x}", + pc, + ins, + extract_field(ins, 0, 5), + extract_field(ins, 5, 5), + extract_field(ins, 10, 14), + extract_field(ins, 10, 3), + ctx.get_a0(), + ctx.get_a1(), + ctx.get_a2(), + ctx.gcsr_estat, + ctx.gcsr_ectl, + ctx.gcsr_tcfg, + ctx.gcsr_tval, + ); + } if matches(OPCODE_CPUCFG, OPCODE_CPUCFG_LEN) { return emulate_cpucfg(ctx, ins); @@ -878,6 +1614,24 @@ pub fn handle_exception_sync( ) -> AxResult { let ecode = get_exception_code(ctx); let esubcode = get_exception_subcode(ctx); + if SYNC_EXIT_LOGS.fetch_add(1, Ordering::Relaxed) < 32 { + log::warn!( + "LoongArch guest sync exit: ecode={:#x}, esubcode={:#x}, guest_pc={:#x}, \ + host_era={:#x}, gera={:#x}, badv={:#x}, badi={:#x}, guest_is={:#x}, \ + host_estat={:#x}, tlbrbadv={:#x}, tlbrera={:#x}", + ecode, + esubcode, + get_guest_pc(ctx), + ctx.host_era, + ctx.gcsr_era, + get_badv(ctx), + get_badi(ctx), + get_guest_interrupt_status(ctx), + ctx.host_estat, + ctx.host_tlbrbadv, + ctx.host_tlbrera, + ); + } log::debug!( "LoongArch guest sync exit: ecode={:#x}, esubcode={:#x}, guest_pc={:#x}, host_era={:#x}, \ @@ -900,6 +1654,20 @@ pub fn handle_exception_sync( return Ok(AxVCpuExitReason::Nothing); } ctx.sepc = get_guest_pc(ctx); + if NESTED_FAULT_LOGS.fetch_add(1, Ordering::Relaxed) < 8 { + log::warn!( + "LoongArch nested fault from host refill: badv={:#x}, gpa={:#x}, pc={:#x}, \ + crmd={:#x}, eentry={:#x}, tlbrentry={:#x}, tlbrera={:#x}, host_estat={:#x}", + badv, + direct_map_guest_addr_to_gpa(badv), + get_guest_pc(ctx), + ctx.gcsr_crmd, + ctx.gcsr_eentry, + ctx.gcsr_tlbrentry, + ctx.host_tlbrera, + ctx.host_estat + ); + } return Ok(AxVCpuExitReason::NestedPageFault { addr: GuestPhysAddr::from(direct_map_guest_addr_to_gpa(badv)), access_flags: get_refill_access_flags(ctx), @@ -939,8 +1707,23 @@ pub fn handle_exception_sync( } else { access_flags |= MappingFlags::READ; } + if NESTED_FAULT_LOGS.fetch_add(1, Ordering::Relaxed) < 8 { + log::warn!( + "LoongArch nested fault from regular exception: ecode={:#x}, badv={:#x}, \ + gpa={:#x}, pc={:#x}, crmd={:#x}, eentry={:#x}, tlbrentry={:#x}, \ + host_estat={:#x}", + ecode, + badv, + direct_map_guest_addr_to_gpa(badv), + get_guest_pc(ctx), + ctx.gcsr_crmd, + ctx.gcsr_eentry, + ctx.gcsr_tlbrentry, + ctx.host_estat + ); + } Ok(AxVCpuExitReason::NestedPageFault { - addr: GuestPhysAddr::from(badv), + addr: GuestPhysAddr::from(direct_map_guest_addr_to_gpa(badv)), access_flags, }) } @@ -1019,7 +1802,21 @@ pub fn handle_exception_irq(ctx: &mut LoongArchContextFrame) -> AxResult(), + host_pgdl = const offset_of!(LoongArchContextFrame, host_pgdl), + host_pgdh = const offset_of!(LoongArchContextFrame, host_pgdh), + host_pwcl = const offset_of!(LoongArchContextFrame, host_pwcl), + host_pwch = const offset_of!(LoongArchContextFrame, host_pwch), + host_stlbps = const offset_of!(LoongArchContextFrame, host_stlbps), + host_tlbrentry = const offset_of!(LoongArchContextFrame, host_tlbrentry), + host_asid = const offset_of!(LoongArchContextFrame, host_asid), + host_eentry = const offset_of!(LoongArchContextFrame, host_eentry), + host_ecfg = const offset_of!(LoongArchContextFrame, host_ecfg), + guest_tlbrentry = const offset_of!(LoongArchContextFrame, guest_tlbrentry), + guest_eentry = const offset_of!(LoongArchContextFrame, guest_eentry), +); #[cfg(target_arch = "loongarch64")] #[unsafe(naked)] diff --git a/virtualization/loongarch_vcpu/src/host.rs b/virtualization/loongarch_vcpu/src/host.rs index 1132b6a335..f49244fd71 100644 --- a/virtualization/loongarch_vcpu/src/host.rs +++ b/virtualization/loongarch_vcpu/src/host.rs @@ -30,6 +30,9 @@ pub trait LoongArchVcpuHostIf { /// Queue an interrupt for a vCPU. fn inject_interrupt(vm_id: usize, vcpu_id: usize, vector: usize); + + /// Queue a routed external interrupt for a vCPU. + fn inject_external_interrupt(vm_id: usize, vcpu_id: usize, vector: usize, physical_irq: usize); } #[cfg(target_arch = "loongarch64")] diff --git a/virtualization/loongarch_vcpu/src/lib.rs b/virtualization/loongarch_vcpu/src/lib.rs index 4e8fb84dbe..e822a5d75f 100644 --- a/virtualization/loongarch_vcpu/src/lib.rs +++ b/virtualization/loongarch_vcpu/src/lib.rs @@ -6,6 +6,7 @@ extern crate alloc; mod context_frame; mod exception; pub mod host; +mod mmio; mod pcpu; mod registers; mod vcpu; diff --git a/virtualization/loongarch_vcpu/src/mmio.rs b/virtualization/loongarch_vcpu/src/mmio.rs new file mode 100644 index 0000000000..f92b8abc41 --- /dev/null +++ b/virtualization/loongarch_vcpu/src/mmio.rs @@ -0,0 +1,333 @@ +use axvcpu::{AccessWidth, AxVCpuExitReason, GuestPhysAddr, MappingFlags}; + +use crate::context_frame::LoongArchContextFrame; + +const INSN_RJ_SHIFT: usize = 5; +const INSN_REG_MASK: usize = 0x1f; +const MEMORY_ACCESS_OP_SHIFT: usize = 22; +const MEMORY_ACCESS_OP_MASK: usize = 0x3ff; +const MEMORY_ACCESS_IMM_SHIFT: usize = 10; +const MEMORY_ACCESS_IMM_MASK: usize = 0xfff; +const MEMORY_ACCESS_RD_SHIFT: usize = 0; +const LD_B_OP: usize = 0x0a0; +const LD_H_OP: usize = 0x0a1; +const LD_W_OP: usize = 0x0a2; +const LD_D_OP: usize = 0x0a3; +const ST_B_OP: usize = 0x0a4; +const ST_H_OP: usize = 0x0a5; +const ST_W_OP: usize = 0x0a6; +const ST_D_OP: usize = 0x0a7; +const LD_BU_OP: usize = 0x0a8; +const LD_HU_OP: usize = 0x0a9; +const LD_WU_OP: usize = 0x0aa; +const LDPTR_W_PREFIX: usize = 0x24; +const STPTR_W_PREFIX: usize = 0x25; +const LDPTR_D_PREFIX: usize = 0x26; +const STPTR_D_PREFIX: usize = 0x27; +const PTR_OP_SHIFT: usize = 24; +const PTR_OP_MASK: usize = 0xff; +const PTR_IMM_SHIFT: usize = 10; +const PTR_IMM_MASK: usize = 0x3fff; +const INDEXED_ACCESS_OP_SHIFT: usize = 15; +const INDEXED_ACCESS_OP_MASK: usize = 0x1ffff; +const LDX_BU_OP: usize = 0x7000; +const LDX_HU_OP: usize = 0x7008; +const LDX_W_OP: usize = 0x7010; +const LDX_D_OP: usize = 0x7018; +const STX_B_OP: usize = 0x7020; +const STX_H_OP: usize = 0x7028; +const STX_W_OP: usize = 0x7030; +const STX_D_OP: usize = 0x7038; +const LDX_B_OP: usize = 0x7040; +const LDX_H_OP: usize = 0x7048; +const LDX_WU_OP: usize = 0x7050; + +pub fn decode_mmio_fault( + ctx: &mut LoongArchContextFrame, + insn: usize, + fault_addr: GuestPhysAddr, + access_flags: MappingFlags, +) -> Option { + let access_flags = refine_access_flags_from_insn(insn, access_flags); + let fault_addr = fault_addr.as_usize(); + let op = (insn >> MEMORY_ACCESS_OP_SHIFT) & MEMORY_ACCESS_OP_MASK; + let rd = (insn >> MEMORY_ACCESS_RD_SHIFT) & INSN_REG_MASK; + let exit_reason = match op { + LD_B_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Byte, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: true, + }, + LD_H_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Word, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: true, + }, + LD_W_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Dword, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: true, + }, + LD_D_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Qword, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + LD_BU_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Byte, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + LD_HU_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Word, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + LD_WU_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Dword, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + ST_B_OP if access_flags.contains(MappingFlags::WRITE) => AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Byte, + data: ctx.gpr(rd) as u64, + }, + ST_H_OP if access_flags.contains(MappingFlags::WRITE) => AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Word, + data: ctx.gpr(rd) as u64, + }, + ST_W_OP if access_flags.contains(MappingFlags::WRITE) => AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Dword, + data: ctx.gpr(rd) as u64, + }, + ST_D_OP if access_flags.contains(MappingFlags::WRITE) => AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Qword, + data: ctx.gpr(rd) as u64, + }, + _ => { + return decode_ptr_mmio_fault(ctx, insn, fault_addr, access_flags) + .or_else(|| decode_indexed_mmio_fault(ctx, insn, fault_addr, access_flags)); + } + }; + + ctx.advance_guest_pc(); + Some(exit_reason) +} + +fn refine_access_flags_from_insn(insn: usize, fallback: MappingFlags) -> MappingFlags { + if is_load_insn(insn) { + MappingFlags::READ + } else if is_store_insn(insn) { + MappingFlags::WRITE + } else { + fallback + } +} + +fn is_load_insn(insn: usize) -> bool { + let op = (insn >> MEMORY_ACCESS_OP_SHIFT) & MEMORY_ACCESS_OP_MASK; + matches!( + op, + LD_B_OP | LD_H_OP | LD_W_OP | LD_D_OP | LD_BU_OP | LD_HU_OP | LD_WU_OP + ) || matches!( + (insn >> PTR_OP_SHIFT) & PTR_OP_MASK, + LDPTR_W_PREFIX | LDPTR_D_PREFIX + ) || matches!( + (insn >> INDEXED_ACCESS_OP_SHIFT) & INDEXED_ACCESS_OP_MASK, + LDX_B_OP | LDX_H_OP | LDX_W_OP | LDX_D_OP | LDX_BU_OP | LDX_HU_OP | LDX_WU_OP + ) +} + +fn is_store_insn(insn: usize) -> bool { + let op = (insn >> MEMORY_ACCESS_OP_SHIFT) & MEMORY_ACCESS_OP_MASK; + matches!(op, ST_B_OP | ST_H_OP | ST_W_OP | ST_D_OP) + || matches!( + (insn >> PTR_OP_SHIFT) & PTR_OP_MASK, + STPTR_W_PREFIX | STPTR_D_PREFIX + ) + || matches!( + (insn >> INDEXED_ACCESS_OP_SHIFT) & INDEXED_ACCESS_OP_MASK, + STX_B_OP | STX_H_OP | STX_W_OP | STX_D_OP + ) +} + +pub fn describe_mmio_fault( + ctx: &LoongArchContextFrame, + insn: usize, +) -> (usize, usize, usize, usize) { + let rj = (insn >> INSN_RJ_SHIFT) & INSN_REG_MASK; + let rj_value = ctx.gpr(rj); + let imm12 = sign_extend_12((insn >> MEMORY_ACCESS_IMM_SHIFT) & MEMORY_ACCESS_IMM_MASK); + let normal_addr = direct_mapped_guest_phys_addr(rj_value.wrapping_add(imm12)); + let imm14 = sign_extend_14((insn >> PTR_IMM_SHIFT) & PTR_IMM_MASK).wrapping_shl(2); + let ptr_addr = direct_mapped_guest_phys_addr(rj_value.wrapping_add(imm14)); + (rj, rj_value, normal_addr, ptr_addr) +} + +fn decode_ptr_mmio_fault( + ctx: &mut LoongArchContextFrame, + insn: usize, + fault_addr: usize, + access_flags: MappingFlags, +) -> Option { + let op = (insn >> PTR_OP_SHIFT) & PTR_OP_MASK; + let rd = (insn >> MEMORY_ACCESS_RD_SHIFT) & INSN_REG_MASK; + let exit_reason = match op { + LDPTR_W_PREFIX if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Dword, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: true, + }, + LDPTR_D_PREFIX if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Qword, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + STPTR_W_PREFIX if access_flags.contains(MappingFlags::WRITE) => { + AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Dword, + data: ctx.gpr(rd) as u64, + } + } + STPTR_D_PREFIX if access_flags.contains(MappingFlags::WRITE) => { + AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Qword, + data: ctx.gpr(rd) as u64, + } + } + _ => return decode_indexed_mmio_fault(ctx, insn, fault_addr, access_flags), + }; + + ctx.advance_guest_pc(); + Some(exit_reason) +} + +fn decode_indexed_mmio_fault( + ctx: &mut LoongArchContextFrame, + insn: usize, + fault_addr: usize, + access_flags: MappingFlags, +) -> Option { + let op = (insn >> INDEXED_ACCESS_OP_SHIFT) & INDEXED_ACCESS_OP_MASK; + let rd = (insn >> MEMORY_ACCESS_RD_SHIFT) & INSN_REG_MASK; + + let exit_reason = match op { + LDX_B_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Byte, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: true, + }, + LDX_H_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Word, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: true, + }, + LDX_W_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Dword, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: true, + }, + LDX_D_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Qword, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + LDX_BU_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Byte, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + LDX_HU_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Word, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + LDX_WU_OP if access_flags.contains(MappingFlags::READ) => AxVCpuExitReason::MmioRead { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Dword, + reg: rd, + reg_width: AccessWidth::Qword, + signed_ext: false, + }, + STX_B_OP if access_flags.contains(MappingFlags::WRITE) => AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Byte, + data: ctx.gpr(rd) as u64, + }, + STX_H_OP if access_flags.contains(MappingFlags::WRITE) => AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Word, + data: ctx.gpr(rd) as u64, + }, + STX_W_OP if access_flags.contains(MappingFlags::WRITE) => AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Dword, + data: ctx.gpr(rd) as u64, + }, + STX_D_OP if access_flags.contains(MappingFlags::WRITE) => AxVCpuExitReason::MmioWrite { + addr: GuestPhysAddr::from(fault_addr), + width: AccessWidth::Qword, + data: ctx.gpr(rd) as u64, + }, + _ => return None, + }; + + ctx.advance_guest_pc(); + Some(exit_reason) +} + +fn sign_extend_12(value: usize) -> usize { + ((value << (usize::BITS as usize - 12)) as isize >> (usize::BITS as usize - 12)) as usize +} + +fn sign_extend_14(value: usize) -> usize { + ((value << (usize::BITS as usize - 14)) as isize >> (usize::BITS as usize - 14)) as usize +} + +fn direct_mapped_guest_phys_addr(addr: usize) -> usize { + const DMW_PREFIX_MASK: usize = 0xf000_0000_0000_0000; + const DMW0_PREFIX: usize = 0x8000_0000_0000_0000; + const DMW1_PREFIX: usize = 0x9000_0000_0000_0000; + const DMW_PHYS_MASK: usize = 0x0000_ffff_ffff_ffff; + + match addr & DMW_PREFIX_MASK { + DMW0_PREFIX | DMW1_PREFIX => addr & DMW_PHYS_MASK, + _ => addr, + } +} diff --git a/virtualization/loongarch_vcpu/src/registers.rs b/virtualization/loongarch_vcpu/src/registers.rs index fccc39c8a8..a162ec6985 100644 --- a/virtualization/loongarch_vcpu/src/registers.rs +++ b/virtualization/loongarch_vcpu/src/registers.rs @@ -129,8 +129,8 @@ pub(crate) unsafe fn gstat_set_gid(gid: usize) { } #[inline(always)] -pub(crate) unsafe fn gstat_set_pvm(pvm: bool) { - set_csr_bit::(1, pvm); +pub(crate) unsafe fn gstat_set_pgm(pgm: bool) { + set_csr_bit::(2, pgm); } #[inline(always)] @@ -235,6 +235,16 @@ fn current_hwis() -> usize { (read_gintc() & GINTC_HWIS_MASK) >> GINTC_HWIS_SHIFT } +pub fn set_hwi_interrupts(mask: usize) { + let hwis = (mask >> INT_HWI0) & GINTC_HWIS_MASK; + unsafe { + let mut gintc = read_gintc(); + gintc &= !GINTC_HWIS_MASK; + gintc |= (hwis << GINTC_HWIS_SHIFT) & GINTC_HWIS_MASK; + write_gintc(gintc); + } +} + unsafe fn pulse_hwi(vector: usize) { let hwis_bit = 1 << (vector - INT_HWI0); @@ -260,15 +270,24 @@ pub fn inject_interrupt(vector: usize) { unsafe { if (INT_HWI0..=INT_HWI7).contains(&vector) { - if INJECT_INT_LOGS.fetch_add(1, Ordering::Relaxed) < 16 { - log::debug!( - "LoongArch vcpu pulse HWI: vector={}, gintc_before={:#x}, hwis_before={:#x}", + let log_index = INJECT_INT_LOGS.fetch_add(1, Ordering::Relaxed); + if log_index < 16 { + log::trace!( + "LoongArch vcpu pulse HWI before: vector={}, gintc={:#x}, hwis={:#x}", vector, read_gintc(), current_hwis() ); } pulse_hwi(vector); + if log_index < 16 { + log::trace!( + "LoongArch vcpu pulse HWI after: vector={}, gintc={:#x}, hwis={:#x}", + vector, + read_gintc(), + current_hwis() + ); + } } else { let estat = gcsr_read::(); gcsr_write::(estat | (1usize << vector)); diff --git a/virtualization/loongarch_vcpu/src/vcpu.rs b/virtualization/loongarch_vcpu/src/vcpu.rs index 03eb3544e4..2e94d49f8f 100644 --- a/virtualization/loongarch_vcpu/src/vcpu.rs +++ b/virtualization/loongarch_vcpu/src/vcpu.rs @@ -3,23 +3,24 @@ use ax_errno::AxResult; use ax_errno::ax_err; #[cfg(target_arch = "loongarch64")] use ax_memory_addr::VirtAddr; -#[cfg(target_arch = "loongarch64")] -use ax_page_table_multiarch::loongarch64::LA64MetaData; -use axvcpu::{AxArchVCpu, AxVCpuExitReason, GuestPhysAddr, HostPhysAddr, VCpuId, VMId}; +use axvcpu::{ + AxArchVCpu, AxVCpuExitReason, GuestPhysAddr, HostPhysAddr, MappingFlags, VCpuId, VMId, +}; #[cfg(target_arch = "loongarch64")] use loongArch64::register::prmd; #[cfg(target_arch = "loongarch64")] -use crate::exception::{TrapKind, handle_exception_irq, handle_exception_sync}; +use crate::exception::{TrapKind, current_badi, handle_exception_irq, handle_exception_sync}; use crate::{ context_frame::LoongArchContextFrame, host, registers::{ - CSR_ASID, CSR_CRMD, CSR_KSAVE_KSP, CSR_PGDH, CSR_PGDL, CSR_PRMD, CSR_PWCH, CSR_PWCL, - CSR_STLBPS, CSR_TLBRENTRY, INT_HWI0, INT_HWI7, INT_IPI, INT_TIMER, csr_read, csr_write, - gcfg_set_gpm_num, gcfg_set_matc, gcfg_set_toci, gcfg_set_toe, gcfg_set_tohu, gcfg_set_top, - gcfg_set_topi, gcfg_set_toti, get_ecfg_vs, gintc_set_hwi_passthrough, gstat_set_gid, - gstat_set_pvm, gtlbc_set_tgid, gtlbc_set_use_tgid, set_ecfg_line_enabled, set_ecfg_vs, + CSR_ASID, CSR_CRMD, CSR_ECFG, CSR_GCTL, CSR_GINTC, CSR_GSTAT, CSR_GTLBC, CSR_KSAVE_KSP, + CSR_PGDH, CSR_PGDL, CSR_PRMD, CSR_PWCH, CSR_PWCL, CSR_STLBPS, CSR_TLBRENTRY, INT_HWI0, + INT_HWI7, INT_IPI, INT_TIMER, csr_read, csr_write, gcfg_set_gpm_num, gcfg_set_matc, + gcfg_set_toci, gcfg_set_toe, gcfg_set_tohu, gcfg_set_top, gcfg_set_topi, gcfg_set_toti, + get_ecfg_vs, gintc_set_hwi_passthrough, gstat_set_gid, gstat_set_pgm, gtlbc_set_tgid, + gtlbc_set_use_tgid, set_ecfg_line_enabled, set_ecfg_vs, }, }; @@ -52,6 +53,8 @@ pub struct LoongArchVCpu { vcpu_id: VCpuId, cpu_id: usize, guest_timer_token: Option, + last_badi: usize, + entry_logged: bool, } #[cfg(target_arch = "loongarch64")] @@ -107,11 +110,11 @@ const GUEST_BOOT_VSEG: usize = 0x9000; const GUEST_BOOT_DMW: usize = (GUEST_BOOT_VSEG << GUEST_DMW_DA_BITS) | GUEST_DMW_PLV0 | GUEST_DMW_MAT_CC; #[cfg(target_arch = "loongarch64")] -const STAGE2_ASID: usize = 1; -#[cfg(target_arch = "loongarch64")] const CSR_CRMD_IE: usize = 1 << 2; #[cfg(target_arch = "loongarch64")] const LOCAL_INTERRUPT_MASK: usize = (1 << (INT_IPI + 1)) - 1; +#[cfg(target_arch = "loongarch64")] +const HOST_DMW_CACHED_BASE: usize = 0x9000_0000_0000_0000; #[derive(Clone, Debug, Default)] pub struct LoongArchVCpuCreateConfig { @@ -119,6 +122,7 @@ pub struct LoongArchVCpuCreateConfig { pub dtb_addr: usize, pub boot_args: [usize; 3], pub boot_stack_top: usize, + pub firmware_boot: bool, } #[derive(Clone, Debug, Default)] @@ -127,6 +131,30 @@ pub struct LoongArchVCpuSetupConfig { pub passthrough_timer: bool, pub boot_args: [usize; 3], pub boot_stack_top: usize, + pub firmware_boot: bool, +} + +#[cfg(target_arch = "loongarch64")] +#[derive(Clone, Copy, Debug)] +pub struct LoongArchVCpuDebugState { + pub sepc: usize, + pub gcsr_crmd: usize, + pub gcsr_ectl: usize, + pub gcsr_estat: usize, + pub gcsr_era: usize, + pub gcsr_badv: usize, + pub gcsr_eentry: usize, + pub gcsr_tcfg: usize, + pub gcsr_tval: usize, + pub gcsr_tlbrentry: usize, + pub gcsr_tlbrbadv: usize, + pub gcsr_tlbrera: usize, + pub host_estat: usize, + pub host_era: usize, + pub host_badv: usize, + pub host_tlbrbadv: usize, + pub host_tlbrera: usize, + pub last_badi: usize, } impl AxArchVCpu for LoongArchVCpu { @@ -135,7 +163,11 @@ impl AxArchVCpu for LoongArchVCpu { fn new(_vm_id: usize, _vcpu_id: usize, config: Self::CreateConfig) -> AxResult { let mut ctx = LoongArchContextFrame::default(); - if config.boot_args != [0; 3] { + if config.firmware_boot { + // Firmware reset entry keeps the initial argument registers in their + // reset state. The firmware obtains its early FDT via its own reset + // path, while OS direct boot receives DTB/EFI args from AxVM. + } else if config.boot_args != [0; 3] { ctx.set_argument(config.boot_args[0]); ctx.set_a1(config.boot_args[1]); ctx.set_a2(config.boot_args[2]); @@ -155,6 +187,8 @@ impl AxArchVCpu for LoongArchVCpu { vcpu_id: _vcpu_id, cpu_id: config.cpu_id, guest_timer_token: None, + last_badi: 0, + entry_logged: false, }) } @@ -170,7 +204,7 @@ impl AxArchVCpu for LoongArchVCpu { } fn setup(&mut self, config: Self::SetupConfig) -> AxResult { - if config.boot_args != [0; 3] { + if !config.firmware_boot && config.boot_args != [0; 3] { self.ctx.set_argument(config.boot_args[0]); self.ctx.set_a1(config.boot_args[1]); self.ctx.set_a2(config.boot_args[2]); @@ -188,12 +222,106 @@ impl AxArchVCpu for LoongArchVCpu { unsafe { self.enable_guest_mode(); } + if crate::exception::inject_enabled_pending_interrupt( + &mut self.ctx, + self.vm_id, + self.vcpu_id, + ) { + log::trace!( + "LoongArch guest pending interrupt injected before entry: VM[{}] VCpu[{}] \ + sepc={:#x}, era={:#x}, estat={:#x}, ecfg={:#x}", + self.vm_id, + self.vcpu_id, + self.ctx.sepc, + self.ctx.gcsr_era, + self.ctx.gcsr_estat, + self.ctx.gcsr_ectl + ); + } + if !self.entry_logged + || self.ctx.gcsr_estat & self.ctx.gcsr_ectl & (1usize << INT_HWI0) != 0 + { + let gintc = unsafe { csr_read::() }; + log::debug!( + "LoongArch guest first entry: VM[{}] VCpu[{}] sepc={:#x}, gera={:#x}, \ + a0={:#x}, a1={:#x}, a2={:#x}, sp={:#x}, stage2_root={:#x}, estat={:#x}, \ + ecfg={:#x}, gintc={:#x}", + self.vm_id, + self.vcpu_id, + self.ctx.sepc, + self.ctx.gcsr_era, + self.ctx.get_a0(), + self.ctx.get_a1(), + self.ctx.get_a2(), + self.ctx.x[3], + self.stage2_root.as_usize(), + self.ctx.gcsr_estat, + self.ctx.gcsr_ectl, + gintc, + ); + let ( + gstat, + gcfg, + gtlbc, + gintc, + host_crmd, + host_ecfg, + host_pgdl, + host_pgdh, + host_pwcl, + host_pwch, + host_stlbps, + host_tlbrentry, + ) = unsafe { + ( + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + csr_read::(), + ) + }; + log::debug!( + "LoongArch guest entry CSR: gstat={:#x}, gcfg={:#x}, gtlbc={:#x}, \ + gintc={:#x}, host_crmd={:#x}, host_ecfg={:#x}, host_pgdl={:#x}, \ + host_pgdh={:#x}, host_pwcl={:#x}, host_pwch={:#x}, host_stlbps={:#x}, \ + host_tlbrentry={:#x}", + gstat, + gcfg, + gtlbc, + gintc, + host_crmd, + host_ecfg, + host_pgdl, + host_pgdh, + host_pwcl, + host_pwch, + host_stlbps, + host_tlbrentry, + ); + self.entry_logged = true; + } log::debug!("LoongArch guest entry context:\n{}", self.ctx); let exit_reason = unsafe { save_host_sp(); self.run_guest() }; + log::trace!( + "LoongArch guest exit raw: VM[{}] VCpu[{}] reason={}, sepc={:#x}, gera={:#x}", + self.vm_id, + self.vcpu_id, + exit_reason, + self.ctx.sepc, + self.ctx.gcsr_era + ); let trap_kind = TrapKind::try_from(exit_reason as u8).expect("invalid TrapKind"); self.vmexit_handler(trap_kind) } @@ -211,13 +339,12 @@ impl AxArchVCpu for LoongArchVCpu { let _ = self.cpu_id; #[cfg(target_arch = "loongarch64")] unsafe { + log::debug!( + "LoongArch VCpu[{}] bind: save host translation", + self.vcpu_id + ); self.save_host_translation_state(); - self.activate_stage2_walk_state(); - self.install_host_exit_vectors(); - // Our guest-exit vector table uses 0x80-byte spacing between entries, - // i.e. 32 instructions, so CSR.ECFG.VS must be 5. - set_ecfg_vs(5); - self.enable_guest_mode(); + log::debug!("LoongArch VCpu[{}] bind: done", self.vcpu_id); } Ok(()) } @@ -235,11 +362,57 @@ impl AxArchVCpu for LoongArchVCpu { self.ctx.set_gpr(idx, val); } + fn decode_mmio_fault( + &mut self, + fault_addr: GuestPhysAddr, + access_flags: MappingFlags, + ) -> Option { + let gcsr_badi = self.ctx.gcsr_badi; + let exit = + crate::mmio::decode_mmio_fault(&mut self.ctx, self.last_badi, fault_addr, access_flags) + .or_else(|| { + if gcsr_badi == self.last_badi { + None + } else { + crate::mmio::decode_mmio_fault( + &mut self.ctx, + gcsr_badi, + fault_addr, + access_flags, + ) + } + }); + + if exit.is_none() { + let (rj, rj_value, normal_addr, ptr_addr) = + crate::mmio::describe_mmio_fault(&self.ctx, self.last_badi); + log::debug!( + "LoongArch MMIO decode failed: addr={:#x}, flags={:?}, sepc={:#x}, badi={:#x}, \ + gcsr_badi={:#x}, rj={}, rj_value={:#x}, normal_addr={:#x}, ptr_addr={:#x}", + fault_addr.as_usize(), + access_flags, + self.ctx.sepc, + self.last_badi, + gcsr_badi, + rj, + rj_value, + normal_addr, + ptr_addr + ); + } + + exit + } + fn inject_interrupt(&mut self, vector: usize) -> AxResult { if (INT_HWI0..=INT_HWI7).contains(&vector) { crate::registers::inject_interrupt(vector); } else if vector <= INT_IPI { self.ctx.gcsr_estat |= 1usize << vector; + } else if let Some(hwi) = + crate::exception::inject_guest_eiointc_vector(self.vm_id, self.vcpu_id, vector) + { + crate::registers::inject_interrupt(hwi); } else { log::warn!("Ignoring unsupported LoongArch interrupt vector {vector}"); } @@ -252,6 +425,55 @@ impl AxArchVCpu for LoongArchVCpu { } impl LoongArchVCpu { + #[cfg(target_arch = "loongarch64")] + pub fn debug_state(&self) -> LoongArchVCpuDebugState { + LoongArchVCpuDebugState { + sepc: self.ctx.sepc, + gcsr_crmd: self.ctx.gcsr_crmd, + gcsr_ectl: self.ctx.gcsr_ectl, + gcsr_estat: self.ctx.gcsr_estat, + gcsr_era: self.ctx.gcsr_era, + gcsr_badv: self.ctx.gcsr_badv, + gcsr_eentry: self.ctx.gcsr_eentry, + gcsr_tcfg: self.ctx.gcsr_tcfg, + gcsr_tval: self.ctx.gcsr_tval, + gcsr_tlbrentry: self.ctx.gcsr_tlbrentry, + gcsr_tlbrbadv: self.ctx.gcsr_tlbrbadv, + gcsr_tlbrera: self.ctx.gcsr_tlbrera, + host_estat: self.ctx.host_estat, + host_era: self.ctx.host_era, + host_badv: self.ctx.host_badv, + host_tlbrbadv: self.ctx.host_tlbrbadv, + host_tlbrera: self.ctx.host_tlbrera, + last_badi: self.last_badi, + } + } + + #[cfg(target_arch = "loongarch64")] + pub fn inject_external_interrupt(&mut self, vector: usize, physical_irq: usize) -> AxResult { + if let Some(hwi) = + crate::exception::inject_guest_eiointc_vector(self.vm_id, self.vcpu_id, vector) + { + self.ctx.gcsr_estat |= 1usize << hwi; + log::debug!( + "LoongArch guest external IRQ pending: VM[{}] VCpu[{}] physical_irq={}, \ + eiointc_hwi={}, routed_vector={}", + self.vm_id, + self.vcpu_id, + physical_irq, + hwi, + vector + ); + return self.inject_interrupt(hwi); + } + self.inject_interrupt(vector) + } + + #[cfg(target_arch = "loongarch64")] + fn host_dmw_alias(vaddr: VirtAddr) -> usize { + HOST_DMW_CACHED_BASE | host::virt_to_phys(vaddr).as_usize() + } + #[cfg(target_arch = "loongarch64")] pub fn has_enabled_pending_interrupt(&self) -> bool { self.ctx.gcsr_eentry != 0 @@ -287,8 +509,10 @@ impl LoongArchVCpu { fn init_hv(&mut self, config: LoongArchVCpuSetupConfig) { self.init_vm_context(config); #[cfg(target_arch = "loongarch64")] + crate::exception::init_guest_iocsr(self.vm_id, self.vcpu_id); + #[cfg(target_arch = "loongarch64")] unsafe { - gintc_set_hwi_passthrough(0xff); + gintc_set_hwi_passthrough(0); } } @@ -342,7 +566,7 @@ impl LoongArchVCpu { /// Save host translation CSRs to per-CPU storage before switching to stage2. #[cfg(target_arch = "loongarch64")] - unsafe fn save_host_translation_state(&self) { + unsafe fn save_host_translation_state(&mut self) { HOST_CRMD.write_current_raw(csr_read::()); HOST_PRMD.write_current_raw(csr_read::()); HOST_KSAVE_KSP.write_current_raw(csr_read::()); @@ -355,39 +579,28 @@ impl LoongArchVCpu { HOST_STAGE2_STLBPS.write_current_raw(csr_read::()); HOST_STAGE2_TLBRENTRY.write_current_raw(csr_read::()); HOST_STAGE2_ASID.write_current_raw(csr_read::()); - } - - /// Program stage2 page-walk CSRs from the VM's stage2 root. - #[cfg(target_arch = "loongarch64")] - unsafe fn activate_stage2_walk_state(&self) { - let root = self.stage2_root.as_usize(); - csr_write::(LA64MetaData::PWCL_VALUE as usize); - csr_write::(LA64MetaData::PWCH_VALUE as usize); - csr_write::(12); - csr_write::(root); - csr_write::(root); - csr_write::(STAGE2_ASID); - } - - /// Install host exit vector table (CSR.EENTRY) and TLB refill handler - /// (CSR.TLBRENTRY), then flush stale TLB entries. - #[cfg(target_arch = "loongarch64")] - unsafe fn install_host_exit_vectors(&self) { - let tlbrentry_vaddr = VirtAddr::from_ptr_of(_guest_tlb_refill_vector as *const ()); - let tlbrentry_paddr = host::virt_to_phys(tlbrentry_vaddr).as_usize(); - let guest_exit_eentry = core::ptr::addr_of!(_exception_vectors) as usize; - - csr_write::(tlbrentry_paddr); - csr_write::<{ crate::registers::CSR_EENTRY }>(guest_exit_eentry); - core::arch::asm!("invtlb 0x0, $r0, $r0"); + self.ctx.host_pgdl = HOST_STAGE2_PGDL.read_current_raw(); + self.ctx.host_pgdh = HOST_STAGE2_PGDH.read_current_raw(); + self.ctx.host_pwcl = HOST_STAGE2_PWCL.read_current_raw(); + self.ctx.host_pwch = HOST_STAGE2_PWCH.read_current_raw(); + self.ctx.host_stlbps = HOST_STAGE2_STLBPS.read_current_raw(); + self.ctx.host_tlbrentry = HOST_STAGE2_TLBRENTRY.read_current_raw(); + self.ctx.host_asid = HOST_STAGE2_ASID.read_current_raw(); + self.ctx.host_eentry = HOST_GUEST_EXIT_EENTRY.read_current_raw(); + self.ctx.host_ecfg = csr_read::(); + self.ctx.guest_tlbrentry = + Self::host_dmw_alias(VirtAddr::from_ptr_of(_guest_tlb_refill_vector as *const ())); + self.ctx.guest_eentry = Self::host_dmw_alias(VirtAddr::from_ptr_of(core::ptr::addr_of!( + _exception_vectors + ))); } /// Enable LVZ guest-mode hardware: GID, TGID, PGM, GCFG, GINTC, PRMD.PIE. #[cfg(target_arch = "loongarch64")] unsafe fn enable_guest_mode(&self) { - let guest_id = 0; + let guest_id = self.vm_id + 1; gstat_set_gid(guest_id); - gstat_set_pvm(true); + gstat_set_pgm(true); gtlbc_set_use_tgid(true); gtlbc_set_tgid(guest_id); gcfg_set_matc(0x1); @@ -438,17 +651,31 @@ impl LoongArchVCpu { "st.d $fp, $sp, 80", "st.d $tp, $sp, 88", "st.d $r21, $sp, 96", + "move $s0, $a0", "move $t0, $sp", "addi.d $t1, $a0, {host_stack_top_offset}", "st.d $t0, $t1, 0", - "bl {run_guest_asm}", + "la.pcrel $a0, {run_guest_asm}", + "bl {host_dmw_alias}", + "move $t0, $a0", + "move $a0, $s0", + "addi.d $a1, $a0, {stage2_root_offset}", + "ld.d $a1, $a1, 0", + "jirl $ra, $t0, 0", "bl {run_guest_panic}", host_stack_top_offset = const core::mem::size_of::(), + stage2_root_offset = const core::mem::size_of::() + core::mem::size_of::(), run_guest_asm = sym _run_guest, + host_dmw_alias = sym Self::host_dmw_alias_for_asm, run_guest_panic = sym Self::run_guest_panic, ); } + #[cfg(target_arch = "loongarch64")] + extern "C" fn host_dmw_alias_for_asm(ptr: usize) -> usize { + Self::host_dmw_alias(VirtAddr::from(ptr)) + } + #[cfg(target_arch = "loongarch64")] unsafe fn run_guest_panic() -> ! { panic!("run_guest_panic: control returned to run_guest"); @@ -456,6 +683,12 @@ impl LoongArchVCpu { #[cfg(target_arch = "loongarch64")] fn vmexit_handler(&mut self, exit_reason: TrapKind) -> AxResult { + self.last_badi = if self.ctx.host_badi != 0 { + self.ctx.host_badi + } else { + current_badi() + }; + match exit_reason { TrapKind::Synchronous => handle_exception_sync( &mut self.ctx, From a2bfbb89729c68d89ac3086c6fcbd960e49ef1ed Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 15 Jun 2026 09:17:35 +0800 Subject: [PATCH 20/50] opt log --- .../someboot/src/arch/loongarch64/trap.rs | 31 +--- os/axvisor/src/config.rs | 6 +- os/axvisor/src/images/mod.rs | 14 +- platforms/axplat-dyn/src/irq.rs | 2 +- .../somehal/src/arch/loongarch64/pch_pic.rs | 6 +- virtualization/axvm/src/runtime/vcpus.rs | 13 +- virtualization/axvm/src/vm.rs | 156 +++++++++++++++++- .../loongarch_vcpu/src/exception.rs | 6 +- 8 files changed, 174 insertions(+), 60 deletions(-) diff --git a/components/someboot/src/arch/loongarch64/trap.rs b/components/someboot/src/arch/loongarch64/trap.rs index 740a98b578..e1f0de1851 100644 --- a/components/someboot/src/arch/loongarch64/trap.rs +++ b/components/someboot/src/arch/loongarch64/trap.rs @@ -149,9 +149,9 @@ fn tlbrentry_addr() -> usize { virt_to_phys((eentry_addr() + 80 * VECSIZE) as *const u8) } -pub fn per_cpu_trap_init(is_primary: bool) { +pub fn per_cpu_trap_init(_is_primary: bool) { setup_vint_size(); - configure_exception_vector(is_primary); + configure_exception_vector(); } pub(crate) fn init_entries_for_secondary() { @@ -166,21 +166,11 @@ fn setup_vint_size() { } /// 配置异常向量 -fn configure_exception_vector(verbose: bool) { +fn configure_exception_vector() { let eentry_addr = eentry_addr(); - if verbose { - println!("Setting EENTRY to {:#x}", eentry_addr); - } eentry::set_eentry(eentry_addr); - let val = eentry::read().eentry(); - if verbose { - println!("EENTRY set to {:#x}", val); - } let tlbrentry_addr = tlbrentry_addr(); - if verbose { - println!("Setting TLBRENTRY to {:#x}", tlbrentry_addr); - } tlbrentry::set_tlbrentry(tlbrentry_addr); } @@ -196,7 +186,6 @@ fn do_vint(_tf: &mut TrapFrame) { #[unsafe(no_mangle)] extern "C" fn do_page_fault(tf: &TrapFrame, write: usize, address: usize) -> ! { crate::console::_write_str("[someboot trap] do_page_fault\n"); - println!("do_page_fault called"); let estat = estat::read(); let ecode = estat.ecode(); @@ -231,7 +220,6 @@ extern "C" fn do_page_fault(tf: &TrapFrame, write: usize, address: usize) -> ! { #[unsafe(no_mangle)] extern "C" fn do_tlb_refill(tf: &TrapFrame, address: usize) -> ! { crate::console::_write_str("[someboot trap] do_tlb_refill\n"); - println!("do_tlb_refill called"); panic_on_exception( "TLB REFILL", @@ -666,7 +654,6 @@ global_asm!( #[unsafe(no_mangle)] extern "C" fn do_reserved_exception(tf: &TrapFrame) -> ! { crate::console::_write_str("[someboot trap] do_reserved_exception\n"); - println!("*** do_reserved_exception 被调用 ***"); let estat = estat::read(); let ecode = estat.ecode(); let esubcode = estat.esubcode(); @@ -690,24 +677,12 @@ extern "C" fn do_reserved_exception(tf: &TrapFrame) -> ! { #[unsafe(no_mangle)] extern "C" fn do_address_error(tf: &TrapFrame, badv: usize) -> ! { crate::console::_write_str("[someboot trap] do_address_error\n"); - println!("\n*** do_address_error 被调用 ***"); - println!("BADV (错误地址): {:#x}", badv); let estat = estat::read(); let ecode = estat.ecode(); let esubcode = estat.esubcode(); - println!("ESTAT.ECODE: {:#x}", ecode); - println!("ESTAT.ESUBCODE: {:#x}", esubcode); - println!("ERA (PC): {:#x}", tf.era); - - // ADF 和 ADE 都使用 Ecode 0x8，这里统一处理 - // 根据子码或其他信息区分具体类型（如果需要） let fault_type = "Address Error"; - let _ = ecode; // 避免未使用警告 - - println!("异常类型: {}", fault_type); - println!("*** 开始 panic ***\n"); panic_on_exception( "ADDRESS ERROR", diff --git a/os/axvisor/src/config.rs b/os/axvisor/src/config.rs index 7f25465bc6..74d2324292 100644 --- a/os/axvisor/src/config.rs +++ b/os/axvisor/src/config.rs @@ -148,7 +148,7 @@ pub fn init_guest_vm(raw_cfg: &str) -> AxResult { feature = "fs", any(target_arch = "x86_64", target_arch = "loongarch64") ))] - info!( + debug!( "VM[{}] host filesystem release check: image_location={:?}, passthrough_devices={}, \ passthrough_addresses={}, required={}", vm_create_config.base.id, @@ -365,7 +365,7 @@ fn vm_alloc_memory_regions(vm_create_config: &AxVMCrateConfig, vm: &AxVMRef) -> }; for memory in &vm_create_config.kernel.memory_regions { - info!( + debug!( "VM[{}] allocating memory region: gpa={:#x}, size={:#x}, map_type={:?}", vm.id(), memory.gpa, @@ -405,7 +405,7 @@ fn vm_alloc_memory_regions(vm_create_config: &AxVMCrateConfig, vm: &AxVMRef) -> })?; } } - info!( + debug!( "VM[{}] memory region allocated: gpa={:#x}, size={:#x}, map_type={:?}", vm.id(), memory.gpa, diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index e6837af342..31f105073f 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -133,7 +133,7 @@ impl ImageLoader { pub fn load(&mut self) -> AxResult { self.config.kernel.validate_boot_config()?; - info!( + debug!( "Loading VM[{}] images into memory region: gpa={:#x}, hva={:#x}, size={:#}", self.vm.id(), self.main_memory.gpa, @@ -162,7 +162,7 @@ impl ImageLoader { /// Load VM images from memory /// into the guest VM's memory space based on the VM configuration. fn load_vm_images_from_memory(&mut self) -> AxResult { - info!("Loading VM[{}] images from memory", self.config.base.id); + debug!("Loading VM[{}] images from memory", self.config.base.id); let vm_imags = memory_images_for_vm(&self.config)?; @@ -383,7 +383,7 @@ impl ImageLoader { kernel: &'static [u8], ramdisk: Option<&'static [u8]>, ) -> AxResult { - info!( + debug!( "VM[{}] configuring LoongArch UEFI fw_cfg payloads from memory: kernel={} bytes, \ ramdisk={:?}", self.config.base.id, @@ -399,7 +399,7 @@ impl ImageLoader { let ram_regions = self.loongarch_uefi_ram_regions(); let dtb = build_loongarch_uefi_firmware_dtb(&ram_regions)?; - info!( + debug!( "VM[{}] loading internally generated LoongArch UEFI firmware DTB: {} bytes at \ {:#x}", self.config.base.id, @@ -423,7 +423,7 @@ impl ImageLoader { .memory_regions() .into_iter() .inspect(|region| { - info!( + trace!( "VM[{}] LoongArch UEFI firmware candidate RAM: gpa={:#x}, hpa={:#x}, size={:#x}", self.config.base.id, region.gpa.as_usize(), @@ -440,7 +440,7 @@ impl ImageLoader { .collect::>(); ram_regions.sort_by_key(|region| region.base); - info!( + debug!( "VM[{}] LoongArch UEFI firmware RAM regions: {:?}", self.config.base.id, ram_regions ); @@ -1233,7 +1233,7 @@ pub mod fs { None }; - info!( + debug!( "VM[{}] configuring LoongArch UEFI fw_cfg payloads from filesystem: kernel={} \ bytes, ramdisk={:?}", self.config.base.id, diff --git a/platforms/axplat-dyn/src/irq.rs b/platforms/axplat-dyn/src/irq.rs index 87eca7483b..be2aa44908 100644 --- a/platforms/axplat-dyn/src/irq.rs +++ b/platforms/axplat-dyn/src/irq.rs @@ -106,7 +106,7 @@ impl IrqIf for IrqIfImpl { impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { LOONGARCH_VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); - info!("LoongArch dynamic platform virtual IRQ injector registered"); + debug!("LoongArch dynamic platform virtual IRQ injector registered"); } fn register_guest_irq_route( diff --git a/platforms/somehal/src/arch/loongarch64/pch_pic.rs b/platforms/somehal/src/arch/loongarch64/pch_pic.rs index 1c8866f08d..14e11d95e2 100644 --- a/platforms/somehal/src/arch/loongarch64/pch_pic.rs +++ b/platforms/somehal/src/arch/loongarch64/pch_pic.rs @@ -64,7 +64,7 @@ pub fn debug_summary(inputs: &[usize]) { let pol1 = pic.read_w(PCH_PIC_POL + 4); let clr0 = pic.read_w(PCH_PIC_CLR); let clr1 = pic.read_w(PCH_PIC_CLR + 4); - info!( + debug!( "LoongArch PCH-PIC summary: base_vector={}, vector_count={}, mask=[{:#x},{:#x}], \ htmsi=[{:#x},{:#x}], edge=[{:#x},{:#x}], pol=[{:#x},{:#x}], clr=[{:#x},{:#x}]", pic.base_vector, @@ -86,7 +86,7 @@ pub fn debug_summary(inputs: &[usize]) { } let route = pic.read_b(PCH_INT_ROUTE + input); let htvec = pic.read_b(PCH_INT_HTVEC + input); - info!("LoongArch PCH-PIC input {input}: route={route:#x}, htvec={htvec:#x}"); + debug!("LoongArch PCH-PIC input {input}: route={route:#x}, htvec={htvec:#x}"); } }); } @@ -325,7 +325,7 @@ impl Interface for PchPic { ); return self.base_vector.into(); }; - info!( + debug!( "LoongArch ACPI PCH-PIC route: gsi={}, input={}, vector={}, trigger={:?}, \ polarity={:?}", route.gsi, route.controller_input, vector, route.trigger, route.polarity diff --git a/virtualization/axvm/src/runtime/vcpus.rs b/virtualization/axvm/src/runtime/vcpus.rs index a64394bc4f..8f9ea3867c 100644 --- a/virtualization/axvm/src/runtime/vcpus.rs +++ b/virtualization/axvm/src/runtime/vcpus.rs @@ -565,25 +565,20 @@ fn vcpu_run() { return; }; - info!("VM[{}] VCpu[{}] waiting for running", vm.id(), vcpu.id()); + debug!("VM[{}] VCpu[{}] waiting for running", vm.id(), vcpu.id()); wait_for(&vm_vcpus, || vm.running()); - info!("VM[{}] VCpu[{}] running...", vm.id(), vcpu.id()); + debug!("VM[{}] VCpu[{}] running...", vm.id(), vcpu.id()); #[cfg(target_arch = "x86_64")] super::x86_irq::enable_ioapic_irq_forwarding(&vm, &vcpu); mark_vcpu_running(vm_id); - let mut first_run_logged = false; loop { inject_pending_interrupts(vm_id, vcpu_id, &vcpu); #[cfg(target_arch = "x86_64")] super::x86_irq::drain_pending_ioapic_irqs(&vm, &vcpu); - if !first_run_logged { - info!("VM[{vm_id}] VCpu[{vcpu_id}] entering vm.run_vcpu"); - first_run_logged = true; - } match vm.run_vcpu(vcpu_id) { Ok(exit_reason) => { #[cfg(target_arch = "loongarch64")] @@ -700,7 +695,7 @@ fn vcpu_run() { entry_point, arg, } => { - info!( + debug!( "VM[{vm_id}]'s VCpu[{vcpu_id}] try to boot target_cpu [{target_cpu}] \ entry_point={entry_point:x} arg={arg:#x}" ); @@ -805,7 +800,7 @@ fn vcpu_run() { vm_id, vcpu_id ); wait_for(&vm_vcpus, || !vm.suspending()); - info!("VM[{}] VCpu[{}] resumed from suspend", vm_id, vcpu_id); + debug!("VM[{}] VCpu[{}] resumed from suspend", vm_id, vcpu_id); continue; } diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index 4c4fc0e106..6a5eecabf8 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -12,7 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -use alloc::{boxed::Box, format, sync::Arc, vec::Vec}; +use alloc::{boxed::Box, format, string::String, sync::Arc, vec::Vec}; use core::{alloc::Layout, fmt}; use ax_cpumask::CpuMask; @@ -20,9 +20,11 @@ use ax_errno::{AxError, AxResult, ax_err, ax_err_type}; use ax_kspin::SpinNoIrq as Mutex; use ax_memory_addr::{align_down_4k, align_up_4k}; use axaddrspace::{AddrSpace, MappingFlags}; +#[cfg(target_arch = "loongarch64")] +use axdevice::FwCfgRamRegion; use axdevice::{ - AxVmDeviceConfig, AxVmDevices, DeviceBuildContext, DeviceFactoryRegistry, - register_builtin_factories, + AxVmDeviceConfig, AxVmDevices, DeviceBuildContext, DeviceFactoryRegistry, FwCfg, + FwCfgPlatformConfig, register_builtin_factories, }; use axdevice_base::AccessWidth; #[cfg(target_arch = "aarch64")] @@ -82,6 +84,26 @@ struct AxVMInnerConst { unsafe impl Send for AxVMInnerConst {} unsafe impl Sync for AxVMInnerConst {} +struct PendingFwCfg { + base: GuestPhysAddr, + size: usize, + kernel: &'static [u8], + initrd: Option<&'static [u8]>, + cmdline: Option, + cpu_num: u16, + platform: FwCfgPlatformConfig, +} + +pub struct FwCfgDeviceConfig { + pub base: GuestPhysAddr, + pub size: usize, + pub kernel: &'static [u8], + pub initrd: Option<&'static [u8]>, + pub cmdline: Option, + pub cpu_num: u16, + pub platform: Option, +} + /// Represents a memory region in a virtual machine. #[derive(Debug, Clone)] pub struct VMMemoryRegion { @@ -176,6 +198,7 @@ pub struct AxVM { id: usize, inner_const: Once, inner_mut: Mutex, + pending_fw_cfg: Mutex>, } impl AxVM { @@ -198,6 +221,7 @@ impl AxVM { memory_regions: Vec::new(), vm_status: VMStatus::Loading, }), + pending_fw_cfg: Mutex::new(None), }); info!("VM created: id={}", result.id()); @@ -248,7 +272,7 @@ impl AxVM { let dtb_addr = inner_mut.config.image_config().dtb_load_gpa; let vcpu_id_pcpu_sets = inner_mut.config.phys_cpu_ls.get_vcpu_affinities_pcpu_ids(); - info!("dtb_load_gpa: {dtb_addr:?}"); + debug!("dtb_load_gpa: {dtb_addr:?}"); debug!("id: {}, VCpuIdPCpuSets: {vcpu_id_pcpu_sets:#x?}", self.id()); let mut vcpu_list = Vec::with_capacity(vcpu_id_pcpu_sets.len()); @@ -410,6 +434,8 @@ impl AxVM { } } + self.add_special_emulated_devices(&mut devices)?; + // Setup VCpus. for vcpu in &vcpu_list { #[cfg(target_arch = "aarch64")] @@ -605,6 +631,110 @@ impl AxVM { &self.inner_const().interrupt_fabric } + /// Assert a routed LoongArch platform IRQ in the guest interrupt model. + #[cfg(target_arch = "loongarch64")] + pub(crate) fn loongarch_external_irq_vector( + &self, + fallback_vector: usize, + physical_irq: usize, + ) -> Option { + match self + .get_devices() + .loongarch_pch_pic_assert_irq(fallback_vector) + { + Some(Some(vector)) => Some(vector), + Some(None) => None, + None => Some(fallback_vector), + } + } + + /// Queue a QEMU fw_cfg device that will be attached during VM initialization. + pub fn add_fw_cfg_device(&self, config: FwCfgDeviceConfig) -> AxResult { + let mut pending = self.pending_fw_cfg.lock(); + if pending.is_some() { + return ax_err!( + AlreadyExists, + format!("VM[{}] fw_cfg device already exists", self.id()) + ); + } + *pending = Some(PendingFwCfg { + base: config.base, + size: config.size, + kernel: config.kernel, + initrd: config.initrd, + cmdline: config.cmdline, + cpu_num: config.cpu_num, + platform: config + .platform + .unwrap_or_else(|| self.fw_cfg_platform_config()), + }); + debug!( + "VM[{}] queued fw_cfg device: base={:#x}, size={:#x}, kernel={} bytes, initrd={:?}", + self.id(), + config.base.as_usize(), + config.size, + config.kernel.len(), + config.initrd.map(|data| data.len()) + ); + Ok(()) + } + + fn add_special_emulated_devices(&self, devices: &mut AxVmDevices) -> AxResult { + if let Some(pending) = self.pending_fw_cfg.lock().take() { + debug!( + "VM[{}] adding fw_cfg MMIO device at [{:#x},{:#x})", + self.id(), + pending.base.as_usize(), + pending.base.as_usize() + pending.size + ); + devices.add_fw_cfg_dev(Arc::new(FwCfg::new( + pending.base, + pending.size, + pending.kernel, + pending.initrd, + pending.cmdline.as_deref(), + pending.cpu_num, + pending.platform, + )))?; + } + Ok(()) + } + + fn fw_cfg_platform_config(&self) -> FwCfgPlatformConfig { + #[cfg(target_arch = "loongarch64")] + { + let inner = self.inner_mut.lock(); + let mut ram_regions = inner + .memory_regions + .iter() + .map(|region| FwCfgRamRegion { + base: region.gpa.as_usize() as u64, + size: region.size() as u64, + }) + .filter(|region| region.size != 0) + .collect::>(); + ram_regions.sort_by_key(|region| region.base); + + if !ram_regions.is_empty() { + let ram_regions: &'static [FwCfgRamRegion] = + Box::leak(ram_regions.into_boxed_slice()); + debug!( + "VM[{}] LoongArch fw_cfg RAM regions: {:?}", + self.id(), + ram_regions + ); + return FwCfgPlatformConfig { + ram_regions, + srat_regions: ram_regions, + ..FwCfgPlatformConfig::default() + }; + } + } + + FwCfgPlatformConfig::default() + } + + /// Run a vCPU according to the given vcpu_id. /// /// ## Arguments @@ -653,8 +783,7 @@ impl AxVM { vcpu.set_gpr(reg, val); } AxVCpuExitReason::MmioWrite { addr, width, data } => { - self.get_devices() - .handle_mmio_write(addr, width, data as usize)?; + self.handle_mmio_write(addr, width, data as usize)?; } AxVCpuExitReason::IoRead { port, width } => { let val = self.get_devices().handle_port_read(port, width)?; @@ -711,6 +840,21 @@ impl AxVM { } } + fn handle_mmio_write(&self, addr: GuestPhysAddr, width: AccessWidth, data: usize) -> AxResult { + if let Some(fw_cfg) = self.get_devices().fw_cfg_for_dma_addr(addr) { + if let Some(desc_addr) = fw_cfg.write_dma_address(addr, width, data)? { + fw_cfg.process_dma( + desc_addr, + |gpa, buffer| self.read_from_guest(gpa, buffer), + |gpa, buffer| self.write_to_guest(gpa, buffer), + )?; + } + return Ok(()); + } + + self.get_devices().handle_mmio_write(addr, width, data) + } + fn handle_nested_page_fault(&self, addr: GuestPhysAddr, access_flags: MappingFlags) -> bool { let mut guard = self.inner_mut.lock(); let handled = guard.address_space.handle_page_fault(addr, access_flags); diff --git a/virtualization/loongarch_vcpu/src/exception.rs b/virtualization/loongarch_vcpu/src/exception.rs index dc04012649..6668347df3 100644 --- a/virtualization/loongarch_vcpu/src/exception.rs +++ b/virtualization/loongarch_vcpu/src/exception.rs @@ -1199,7 +1199,7 @@ fn register_guest_timer( ctx.gcsr_tval = 0; ctx.gcsr_estat |= TIMER_BIT; if GUEST_TIMER_LOGS.fetch_add(1, Ordering::Relaxed) < 64 { - log::warn!( + log::trace!( "LoongArch guest timer immediate: tcfg={:#x}, estat={:#x}", ctx.gcsr_tcfg, ctx.gcsr_estat @@ -1212,7 +1212,7 @@ fn register_guest_timer( let delay_ns = host::ticks_to_nanos(init_ticks); let deadline_ns = host::current_time_nanos().saturating_add(delay_ns); if GUEST_TIMER_LOGS.fetch_add(1, Ordering::Relaxed) < 64 { - log::warn!( + log::trace!( "LoongArch guest timer arm: tcfg={:#x}, init_ticks={}, delay_ns={}, deadline_ns={}", ctx.gcsr_tcfg, init_ticks, @@ -1296,7 +1296,7 @@ fn emulate_guest_csr( } fn emulate_cacop(ctx: &mut LoongArchContextFrame, _ins: usize) -> AxVCpuExitReason { - log::info!( + log::trace!( "LoongArch GSPR cacop emulation skipped at guest_pc={:#x}", get_guest_pc(ctx) ); From eaf4fba4bff8ff91766490faecc885524389c7c8 Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 15 Jun 2026 10:10:26 +0800 Subject: [PATCH 21/50] refactor(axvisor): drop legacy LoongArch ELF and zboot loaders --- Cargo.lock | 1 - os/axvisor/Cargo.toml | 1 - .../configs/board/qemu-loongarch64-linux.toml | 12 - .../loongarch/gintc-hwi-passthrough-freeze.md | 123 --------- os/axvisor/doc/loongarch/stage2-tlb-refill.md | 82 ------ os/axvisor/doc/qemu-quickstart.md | 20 +- os/axvisor/doc/qemu-quickstart_cn.md | 20 +- os/axvisor/scripts/quick-start.sh | 134 ++-------- .../loongarch64-unknown-none-softfloat.json | 1 - os/axvisor/src/images/loongarch_elf.rs | 165 ------------ os/axvisor/src/images/loongarch_image.rs | 103 -------- os/axvisor/src/images/loongarch_linux.rs | 240 ------------------ os/axvisor/src/images/loongarch_zboot.rs | 185 -------------- os/axvisor/src/images/mod.rs | 81 ------ .../axconfig.toml | 4 +- .../src/console.rs | 4 +- .../ax-plat-loongarch64-qemu-virt/src/irq.rs | 128 ---------- .../src/irq/eiointc.rs | 5 - .../ax-plat-loongarch64-qemu-virt/src/lib.rs | 4 +- .../ax-plat-loongarch64-qemu-virt/src/mem.rs | 5 +- .../ax-plat-loongarch64-qemu-virt/src/time.rs | 4 +- scripts/axbuild/src/axvisor/rootfs.rs | 66 ----- 22 files changed, 28 insertions(+), 1360 deletions(-) delete mode 100644 os/axvisor/configs/board/qemu-loongarch64-linux.toml delete mode 100644 os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md delete mode 100644 os/axvisor/doc/loongarch/stage2-tlb-refill.md delete mode 120000 os/axvisor/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json delete mode 100644 os/axvisor/src/images/loongarch_elf.rs delete mode 100644 os/axvisor/src/images/loongarch_image.rs delete mode 100644 os/axvisor/src/images/loongarch_linux.rs delete mode 100644 os/axvisor/src/images/loongarch_zboot.rs diff --git a/Cargo.lock b/Cargo.lock index a822563323..2bf3488575 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1541,7 +1541,6 @@ dependencies = [ "prettyplease", "proc-macro2", "quote", - "ruzstd", "spin 0.12.0", "syn 2.0.117", "tokio", diff --git a/os/axvisor/Cargo.toml b/os/axvisor/Cargo.toml index e6c6862f7f..bd56011b3d 100644 --- a/os/axvisor/Cargo.toml +++ b/os/axvisor/Cargo.toml @@ -62,7 +62,6 @@ log = "0.4" byte-unit = { version = "5", default-features = false, features = ["byte"] } fdt-parser = "0.4" hashbrown = "0.14" -ruzstd = { version = "0.8", default-features = false, features = ["hash"] } # System dependent modules provided by ArceOS. ax-std = { workspace = true, features = ["ext-ld", "paging", "irq", "multitask", "task-ext", "smp", "hv"] } diff --git a/os/axvisor/configs/board/qemu-loongarch64-linux.toml b/os/axvisor/configs/board/qemu-loongarch64-linux.toml deleted file mode 100644 index 06e413dfe1..0000000000 --- a/os/axvisor/configs/board/qemu-loongarch64-linux.toml +++ /dev/null @@ -1,12 +0,0 @@ -env = {AX_IP = "10.0.2.15", AX_GW = "10.0.2.2"} -features = [ - "ax-hal/loongarch64-qemu-virt", - "ax-driver/virtio-blk", - "ax-driver/plat-static", - "ept-level-4", - "fs", -] -log = "Info" -max_cpu_num = 1 -target = "loongarch64-unknown-none-softfloat" -vm_configs = [] diff --git a/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md b/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md deleted file mode 100644 index 507954ca68..0000000000 --- a/os/axvisor/doc/loongarch/gintc-hwi-passthrough-freeze.md +++ /dev/null @@ -1,123 +0,0 @@ -# LoongArch64 LVZ: GINTC HWI Passthrough 导致 Guest UART 控制台卡死 - -本文记录 LoongArch LVZ passthrough HWI 的一个关键问题：不能在每次 VM entry -时重写 GINTC passthrough 配置，否则可能清掉 guest pending HWI，导致 Linux guest -串口输入输出卡死。 - -## 现象 - -在 LoongArch64 QEMU-LVZ 上运行 Linux guest 时，guest shell 曾出现过随机卡死： - -- guest 内核没有崩溃； -- vCPU 循环还在运行； -- 控制台不再响应输入输出； -- 高频串口输出或连续输入更容易触发。 - -## 根因 - -GINTC 的 HWI 相关位里，`HWIC` 是 write-one-clear 语义。写入 `HWIC` 会清除 -对应的 `HWIS` pending 位。 - -如果 `gintc_set_hwi_passthrough(0xff)` 在每次 VM entry 都执行，并且写入了 -`HWIC=0xff`，就会出现这个竞态： - -```text -guest 运行 - -> timer 导致 VM exit - -> host 处理 exit - -> UART HWI 在此期间到达，暂存在 GINTC HWIS - -> host 准备重新进入 guest - -> 重写 GINTC，并写入 HWIC - -> HWIS pending 位被清掉 - -> guest 丢失 UART 中断 -``` - -guest 串口驱动依赖 UART 中断推进收发。中断被清掉后，guest 可能停在 idle 或等待 I/O -完成的位置，看起来就是 shell 卡死。 - -## GINTC 位语义 - -| 位域 | 名称 | 含义 | -|------|------|------| -| [7:0] | HWIS | HWI 中断 pending 状态（只读/写 1 清除） | -| [15:8] | HWIP | HWI passthrough 使能掩码 | -| [23:16] | HWIC | 写 1 清除对应 HWIS 位 | - -问题代码的核心是把 passthrough mask 同时写到了 `HWIP` 和 `HWIC`： - -```rust -pub(crate) unsafe fn gintc_set_hwi_passthrough(mask: usize) { - let mut gintc = read_gintc(); - gintc &= !GINTC_HWIP_MASK; - gintc &= !GINTC_HWIC_MASK; - gintc |= (mask << GINTC_HWIP_SHIFT) & GINTC_HWIP_MASK; - gintc |= (mask << GINTC_HWIC_SHIFT) & GINTC_HWIC_MASK; - write_gintc(gintc); -} -``` - -## 修复 - -修复分两部分。 - -第一，GINTC passthrough mask 只在 vCPU 初始化时配置一次，不放在每次 VM entry -都会执行的路径里： - -**文件**：`virtualization/loongarch_vcpu/src/vcpu.rs` - -```rust -// init_hv() — 只调用一次 -fn init_hv(&mut self, config: LoongArchVCpuSetupConfig) { - self.init_vm_context(config); - #[cfg(target_arch = "loongarch64")] - unsafe { - crate::registers::gintc_set_hwi_passthrough(0xff); - } -} - -// enable_guest_mode() — 不再调用 gintc_set_hwi_passthrough -unsafe fn enable_guest_mode(&self) { - // ... 其他 GID/TGID/PGM/GCFG 配置 ... - // gintc_set_hwi_passthrough 已移除 - prmd::set_pie(true); -} -``` - -第二，`gintc_set_hwi_passthrough()` 只更新 `HWIP`，不写 `HWIC`： - -```rust -pub(crate) unsafe fn gintc_set_hwi_passthrough(mask: usize) { - let mut gintc = read_gintc(); - gintc &= !GINTC_HWIP_MASK; - // 不再写 HWIC：写 HWIC 会清除 HWIS pending 位 - gintc |= (mask << GINTC_HWIP_SHIFT) & GINTC_HWIP_MASK; - write_gintc(gintc); -} -``` - -## 中断路径 - -``` - 外设 (UART) → PCH-PIC → EIOINTC → CPU 中断控制器 → CPU - ↕ - GINTC (LVZ) - ↓ - HWIP 使能 → passthrough 直达 guest - HWIS 记录 pending 状态 - HWIC 写 1 清除 pending -``` - -在 passthrough 模式下，外部硬件中断可以直接进入 guest。但如果 host 正在处理 -timer exit 或其他 VM exit，这段时间到达的 HWI 可能会先挂在 GINTC 的 `HWIS` 中。 -因此 VM entry 前的寄存器恢复路径必须避免清除 `HWIS`。 - -## 注意事项 - -1. 静态中断控制器配置不要放在高频 VM entry 路径中反复写。 -2. 写 `HWIC` 会清 pending HWI，不能把它当成普通配置位。 -3. 如果 guest shell 卡在 idle 但 vCPU loop 仍在运行，要优先检查 pending HWI 是否被丢弃。 - -## 相关文件 - -- `virtualization/loongarch_vcpu/src/vcpu.rs` -- `virtualization/loongarch_vcpu/src/registers.rs` diff --git a/os/axvisor/doc/loongarch/stage2-tlb-refill.md b/os/axvisor/doc/loongarch/stage2-tlb-refill.md deleted file mode 100644 index ded1cddf4c..0000000000 --- a/os/axvisor/doc/loongarch/stage2-tlb-refill.md +++ /dev/null @@ -1,82 +0,0 @@ -# LoongArch Stage-2 TLB Refill - -本文记录 LoongArch LVZ 下 AxVisor 处理 guest stage-2 缺页和 TLB refill 的关键路径。 - -## 背景 - -LoongArch guest 运行时，host 会把 stage-2 页表根写入 `CSR_PGDL/CSR_PGDH`，并把 -`CSR_TLBRENTRY` 指向 AxVisor 提供的 guest TLB refill 入口。 - -正常路径是： - -```text -guest 访问地址 - -> LVZ/stage-2 TLB miss - -> _guest_tlb_refill_vector 使用 lddir/ldpte 查 stage-2 页表 - -> 查到映射后 tlbfill - -> ertn 回 guest -``` - -这条路径在汇编里完成，不需要每次 miss 都回到 Rust。 - -## 缺页路径 - -如果 `_guest_tlb_refill_vector` 通过 `lddir/ldpte` 查不到 stage-2 映射，会进入 -VM exit。Rust 侧根据 `host_tlbrera` 判断这是 TLB refill 触发的 exit： - -```text -_guest_tlb_refill_vector - -> stage-2 PTE miss - -> vmexit_trampoline - -> handle_exception_sync() - -> AxVCpuExitReason::NestedPageFault - -> AxVM::handle_nested_page_fault() - -> address_space.handle_page_fault() -``` - -也就是说，LoongArch 当前没有在 Rust 侧手工写入某条 TLB entry。真正的补映射动作 -仍然发生在通用 `address_space.handle_page_fault()` 中；补完后，guest 再次进入时 -由 TLB refill 汇编重新 page walk 并 `tlbfill`。 - -## Guest Fault 与 Stage-2 Fault - -LoongArch Linux 自己也会产生 guest 虚拟地址缺页。AxVisor 需要区分两类情况： - -- guest 自己页表缺页：注入回 guest 的 TLB refill 或普通异常； -- stage-2 映射缺失：返回 `NestedPageFault`，由 AxVisor 补二阶段映射。 - -当前判断主要依赖： - -- guest 是否开启分页； -- fault 地址是否是 guest direct-map 地址； -- fault 地址是否落在已知 guest RAM/MMIO 范围； -- 是否来自 host TLB refill 入口。 - -这样可以避免把 Linux guest 自己应该处理的页表异常误当作 stage-2 缺页。 - -## 大页注意点 - -LoongArch stage-2 PTE 的物理地址位域不能混入软件 level 标记。当前实现只用 -`GH` 位表示 huge page： - -```text -is_huge == true -> set GH -physical address -> only kept in PHYS_ADDR_MASK -``` - -不要把 page-table level 写入 PTE 物理地址位域，否则 `lddir/ldpte` 硬件遍历时 -会读到被污染的物理地址，进而导致异常或反复缺页。 - -## 与其他架构区别 - -- x86 EPT、ARM Stage-2、RISC-V G-stage 通常直接依赖硬件 walker。 -- LoongArch 当前需要显式安装 guest TLB refill 入口，并在该入口中执行 - `lddir/ldpte/tlbfill`。 -- stage-2 miss 仍走 AxVisor 的通用 nested page fault 补映射逻辑。 - -## 后续工作 - -1. 继续验证 READ/WRITE/EXECUTE fault 的权限判断。 -2. 覆盖更多 guest direct-map VA 到 GPA 的转换场景。 -3. 确认映射权限变化或解除映射时的 TLB 失效策略。 -4. 用 Linux boot、rootfs I/O、用户态执行、设备 MMIO 分别验证。 diff --git a/os/axvisor/doc/qemu-quickstart.md b/os/axvisor/doc/qemu-quickstart.md index 1a8741a621..708380820a 100644 --- a/os/axvisor/doc/qemu-quickstart.md +++ b/os/axvisor/doc/qemu-quickstart.md @@ -171,14 +171,6 @@ Success indicator: `Hello, world!` appears in the output. ### AxVisor Shell (LoongArch64, requires QEMU-LVZ) -Install QEMU-LVZ once. The script reuses the local cache if it exists; otherwise it fetches the latest QEMU-LVZ source and builds it: - -```bash -./scripts/setup_qemu_lvz.sh -``` - -After that, quick-start and `cargo xtask axvisor qemu` auto-detect the cached binary: - ```bash ./scripts/quick-start.sh qemu-loongarch64 start ``` @@ -187,15 +179,7 @@ This command launches AxVisor directly and enters the built-in shell instead of Success indicator: `Welcome to AxVisor Shell!` appears in the output. -For the Linux guest flow with a virtio-blk rootfs, run: - -```bash -./scripts/quick-start.sh qemu-loongarch64 run --linux -``` - -The tracked VM template for this flow is `configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml`; quick-start copies it to `tmp/configs/linux-rootfs-smp1.toml`. The managed rootfs path is `tmp/axbuild/rootfs/rootfs-loongarch64-alpine.img`: if it is already present it is reused, otherwise `cargo xtask` downloads the latest matching archive from `rcore-os/tgosimages`. - -> **Note**: Stock `qemu-system-loongarch64` usually does not expose LoongArch virtualization extensions. Run `./scripts/setup_qemu_lvz.sh` once, or set `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` to a validated virtualization-capable binary. +> **Note**: Stock `qemu-system-loongarch64` usually does not expose LoongArch virtualization extensions. Use `QEMU-LVZ`, or set `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` to a validated virtualization-capable binary. ## 5. What Does setup_qemu.sh Do? @@ -227,7 +211,7 @@ QEMU is not installed. Run the `apt install` command from Step 1. ### `Hardware support: false` followed by a panic on LoongArch64 -AxVisor was launched with a LoongArch QEMU binary that does not provide virtualization extensions. Run `./scripts/setup_qemu_lvz.sh` once, or export `AXBUILD_QEMU_SYSTEM_LOONGARCH64` to point at a validated `qemu-system-loongarch64` binary before running `./scripts/quick-start.sh qemu-loongarch64 start`. +AxVisor was launched with a LoongArch QEMU binary that does not provide virtualization extensions. Switch to `QEMU-LVZ`, or export `AXBUILD_QEMU_SYSTEM_LOONGARCH64` to point at a validated `qemu-system-loongarch64` binary before running `./scripts/quick-start.sh qemu-loongarch64 start`. ### `Auto syncing from registry ... timed out` diff --git a/os/axvisor/doc/qemu-quickstart_cn.md b/os/axvisor/doc/qemu-quickstart_cn.md index 8e69cb1764..37ee3f140d 100644 --- a/os/axvisor/doc/qemu-quickstart_cn.md +++ b/os/axvisor/doc/qemu-quickstart_cn.md @@ -129,14 +129,6 @@ cargo xtask qemu \ ### AxVisor Shell（LoongArch64，需要 QEMU-LVZ） -首次使用先安装固定版本 QEMU-LVZ： - -```bash -./scripts/setup_qemu_lvz.sh -``` - -安装完成后，quick-start 会自动发现缓存中的 QEMU-LVZ： - ```bash ./scripts/quick-start.sh qemu-loongarch64 start ``` @@ -145,15 +137,7 @@ cargo xtask qemu \ 启动成功标志：输出中出现 `Welcome to AxVisor Shell!` -Linux guest 启动使用 virtio-blk rootfs： - -```bash -./scripts/quick-start.sh qemu-loongarch64 run --linux -``` - -该流程使用的仓库内 VM 模板是 `configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml`；quick-start 会复制到 `tmp/configs/linux-rootfs-smp1.toml`，再只修改临时配置中的镜像路径。 - -> **注意**：标准版 `qemu-system-loongarch64` 通常不会暴露 LoongArch 虚拟化扩展。请先运行一次 `./scripts/setup_qemu_lvz.sh`，或者通过 `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` 指向一个已经确认支持虚拟化扩展的二进制。 +> **注意**：标准版 `qemu-system-loongarch64` 通常不会暴露 LoongArch 虚拟化扩展。请使用 `QEMU-LVZ`，或者通过 `AXBUILD_QEMU_SYSTEM_LOONGARCH64=/path/to/qemu-system-loongarch64` 指向一个已经确认支持虚拟化扩展的二进制。 ## 5. setup_qemu.sh 做了什么 @@ -181,7 +165,7 @@ VM 配置中的 `kernel_path` 指向了不存在的文件。运行 `./scripts/se ### LoongArch64 下出现 `Hardware support: false`，随后 panic -这说明当前启动使用的 LoongArch QEMU 二进制没有提供虚拟化扩展。请先运行一次 `./scripts/setup_qemu_lvz.sh`，或在运行 `./scripts/quick-start.sh qemu-loongarch64 start` 前导出 `AXBUILD_QEMU_SYSTEM_LOONGARCH64`，把它指向一个已验证支持虚拟化扩展的 `qemu-system-loongarch64`。 +这说明当前启动使用的 LoongArch QEMU 二进制没有提供虚拟化扩展。请切换到 `QEMU-LVZ`，或在运行 `./scripts/quick-start.sh qemu-loongarch64 start` 前导出 `AXBUILD_QEMU_SYSTEM_LOONGARCH64`，把它指向一个已验证支持虚拟化扩展的 `qemu-system-loongarch64`。 ### `Auto syncing from registry ... timed out` diff --git a/os/axvisor/scripts/quick-start.sh b/os/axvisor/scripts/quick-start.sh index 18166856d7..07b1e66b77 100755 --- a/os/axvisor/scripts/quick-start.sh +++ b/os/axvisor/scripts/quick-start.sh @@ -26,16 +26,6 @@ error() { echo -e "${RED}[ERROR]${NC} $1" } -qemu_lvz_cache_binary() { - local cache_root="${AXVISOR_QEMU_LVZ_CACHE:-$HOME/.cache/axvisor/qemu-lvz}" - local latest="$cache_root/latest/bin/qemu-system-loongarch64" - if [[ -x "$latest" ]]; then - printf '%s\n' "$latest" - return 0 - fi - find "$cache_root" -mindepth 3 -maxdepth 3 -path '*/bin/qemu-system-loongarch64' -type f -executable 2>/dev/null | sort | head -n 1 -} - # Execute command and display it run_cmd() { echo -e "${BLUE}$@${NC}" @@ -105,8 +95,6 @@ Launch Options (for run/start commands): -a, --arceos Launch single ArceOS guest (default) QEMU LoongArch64: --axvisor Launch AxVisor shell smoke (default) - -l, --linux Launch single Linux guest with virtio-blk rootfs - --linux-rootfs Launch single Linux guest with virtio-blk rootfs QEMU x86_64: -n, --nimbos Launch single NimbOS guest (default) -l, --linux Launch single Linux guest @@ -137,9 +125,7 @@ Examples: # QEMU LoongArch64 $0 qemu-loongarch64 start --axvisor # One-step: prepare + launch AxVisor shell - $0 qemu-loongarch64 start --linux # One-step: launch Linux with virtio-blk rootfs - $0 qemu-loongarch64 start --linux-rootfs # Same as above - $0 qemu-loongarch64 start # Same as --axvisor (default) + $0 qemu-loongarch64 start # Same as above (default axvisor) # QEMU x86_64 $0 qemu-x86_64 start --nimbos # One-step: prepare + launch NimbOS @@ -178,19 +164,11 @@ EOF } run_axvisor_qemu() { - local axvisor_dir - local workspace_root - axvisor_dir="$(pwd)" - workspace_root="$(cd ../.. && pwd)" - run_cmd bash -c 'cd "$1" && shift && cargo xtask axvisor qemu "$@"' _ "$workspace_root" "$@" + run_cmd cargo xtask qemu "$@" } run_axvisor_uboot() { - local axvisor_dir - local workspace_root - axvisor_dir="$(pwd)" - workspace_root="$(cd ../.. && pwd)" - run_cmd bash -c 'cd "$1" && shift && cargo xtask axvisor uboot "$@"' _ "$workspace_root" "$@" + run_cmd cargo xtask uboot "$@" } ensure_ostool() { @@ -315,25 +293,20 @@ setup_qemu_loongarch64() { info "Preparing board config file..." run_cmd cp configs/board/qemu-loongarch64.toml tmp/configs/ - run_cmd cp configs/board/qemu-loongarch64-linux.toml tmp/configs/ - - info "Preparing Linux guest rootfs config file..." - run_cmd cp configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml tmp/configs/ info "Preparing QEMU config file..." run_cmd cp configs/qemu/qemu-loongarch64.toml tmp/configs/qemu-loongarch64-runtime.toml - local cached_qemu - cached_qemu="$(qemu_lvz_cache_binary)" - if [[ -n "${AXBUILD_QEMU_SYSTEM_LOONGARCH64:-}" ]]; then info "Using explicit LoongArch QEMU override: ${AXBUILD_QEMU_SYSTEM_LOONGARCH64}" - elif [[ -n "$cached_qemu" && -x "$cached_qemu" ]]; then - info "Detected cached QEMU-LVZ at $cached_qemu" + elif [[ -x "$HOME/QEMU-LVZ/build/qemu-system-loongarch64" ]]; then + info "Detected QEMU-LVZ at $HOME/QEMU-LVZ/build/qemu-system-loongarch64" + elif [[ -x "$HOME/qemu-lvz/build/qemu-system-loongarch64" ]]; then + info "Detected QEMU-LVZ at $HOME/qemu-lvz/build/qemu-system-loongarch64" elif command -v qemu-system-loongarch64 &> /dev/null; then warn "Using qemu-system-loongarch64 from PATH. Stock QEMU usually lacks LoongArch virtualization extensions; prefer QEMU-LVZ." else - warn "No LoongArch QEMU binary detected. Run ./scripts/setup_qemu_lvz.sh once, or set AXBUILD_QEMU_SYSTEM_LOONGARCH64." + warn "No LoongArch QEMU binary detected. Set AXBUILD_QEMU_SYSTEM_LOONGARCH64 or install QEMU-LVZ before running." fi info "=== QEMU LoongArch64 Preparation Complete ===" @@ -346,81 +319,6 @@ run_qemu_loongarch64_axvisor() { --qemu-config "$(pwd)/tmp/configs/qemu-loongarch64-runtime.toml" } -loongarch64_qemu_binary() { - local cached_qemu - cached_qemu="$(qemu_lvz_cache_binary)" - - if [[ -n "${AXBUILD_QEMU_SYSTEM_LOONGARCH64:-}" ]]; then - printf '%s\n' "${AXBUILD_QEMU_SYSTEM_LOONGARCH64}" - elif [[ -n "$cached_qemu" && -x "$cached_qemu" ]]; then - printf '%s\n' "$cached_qemu" - elif command -v qemu-system-loongarch64 &> /dev/null; then - command -v qemu-system-loongarch64 - else - return 1 - fi -} - -run_axvisor_qemu_with_loongarch64_qemu() { - local qemu_bin - local qemu_dir - qemu_bin="$(loongarch64_qemu_binary)" || { - error "LoongArch qemu-system-loongarch64 not found. Run ./scripts/setup_qemu_lvz.sh once, or set AXBUILD_QEMU_SYSTEM_LOONGARCH64." - exit 1 - } - qemu_dir="$(dirname "$qemu_bin")" - info "Using LoongArch QEMU: $qemu_bin" - "$qemu_bin" --version | head -n 1 - if [[ "$qemu_bin" == "$(command -v qemu-system-loongarch64 2>/dev/null || true)" ]]; then - warn "PATH qemu-system-loongarch64 may not support LoongArch LVZ. If boot fails, run ./scripts/setup_qemu_lvz.sh." - fi - PATH="$qemu_dir:$PATH" run_axvisor_qemu "$@" -} - -ensure_loongarch64_host_rootfs() { - local workspace_root="$1" - local rootfs="$workspace_root/tmp/axbuild/rootfs/rootfs-loongarch64-alpine.img" - if [[ -f "$rootfs" ]]; then - return 0 - fi - - info "Creating minimal AxVisor host rootfs: $rootfs" - run_cmd mkdir -p "$(dirname "$rootfs")" - run_cmd dd if=/dev/zero of="$rootfs" bs=1M count=1024 status=none - run_cmd mkfs.ext4 -q -F "$rootfs" -} - -ensure_loongarch64_guest_rootfs() { - local workspace_root="$1" - local rootfs="$workspace_root/tmp/axbuild/rootfs/rootfs-loongarch64-alpine.img" - - if [[ -f "$rootfs" ]]; then - info "Using cached LoongArch managed rootfs: $rootfs" - return 0 - fi - - info "LoongArch managed rootfs is missing; cargo xtask will download the latest tgosimages rootfs." -} - -run_qemu_loongarch64_linux() { - info "=== Launching QEMU LoongArch64 Linux Guest with virtio-blk rootfs ===" - setup_qemu_loongarch64 - - local workspace_root - workspace_root="$(cd ../.. && pwd)" - - ensure_loongarch64_guest_rootfs "$workspace_root" - - run_axvisor_qemu_with_loongarch64_qemu \ - --config "$(pwd)/tmp/configs/qemu-loongarch64-linux.toml" \ - --qemu-config "$(pwd)/tmp/configs/qemu-loongarch64-runtime.toml" \ - --vmconfigs "$(pwd)/tmp/configs/linux-rootfs-smp1.toml" -} - -run_qemu_loongarch64_linux_rootfs() { - run_qemu_loongarch64_linux -} - # ============================================================================ # QEMU x86_64 Architecture Setup # ============================================================================ @@ -1105,10 +1003,14 @@ cmd_run_qemu_loongarch64() { run_qemu_loongarch64_axvisor ;; -l|--linux) - run_qemu_loongarch64_linux - ;; - --linux-rootfs) - run_qemu_loongarch64_linux_rootfs + error "Unsupported combination: QEMU LoongArch64 quick start does not launch a Linux guest yet" + echo "" + echo "QEMU LoongArch64 quick start currently supports the following mode:" + echo " - AxVisor shell smoke (use --axvisor)" + echo "" + echo "To launch a Linux guest, please use:" + echo " $0 qemu-aarch64 start --linux" + exit 1 ;; -a|--arceos) error "Unsupported combination: QEMU LoongArch64 quick start does not launch an ArceOS guest yet" @@ -1140,8 +1042,6 @@ cmd_run_qemu_loongarch64() { echo "" echo "QEMU LoongArch64 platform supports the following options:" echo " --axvisor Launch AxVisor shell smoke" - echo " -l, --linux Launch Linux guest with virtio-blk rootfs" - echo " --linux-rootfs Launch Linux guest with virtio-blk rootfs" exit 1 ;; esac @@ -1150,7 +1050,7 @@ cmd_run_qemu_loongarch64() { cmd_start_qemu_loongarch64() { local mode="$1" case "$mode" in - --axvisor|-l|--linux|--linux-rootfs|"") + --axvisor|"") ;; *) cmd_run_qemu_loongarch64 "$mode" diff --git a/os/axvisor/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json b/os/axvisor/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json deleted file mode 120000 index 8df5a0686a..0000000000 --- a/os/axvisor/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json +++ /dev/null @@ -1 +0,0 @@ -/home/szy/work/hypervisor/uefi/no_uefi/tgoskits_glm/scripts/targets/no-pie/loongarch64-unknown-none-softfloat.json \ No newline at end of file diff --git a/os/axvisor/src/images/loongarch_elf.rs b/os/axvisor/src/images/loongarch_elf.rs deleted file mode 100644 index 0dea55a657..0000000000 --- a/os/axvisor/src/images/loongarch_elf.rs +++ /dev/null @@ -1,165 +0,0 @@ -use ax_errno::{AxResult, ax_err_type}; -use axvm::{AxVMRef, GuestPhysAddr}; - -use crate::images::{load_vm_image_from_memory, zero_vm_memory}; - -const ELF_MAGIC: &[u8; 4] = b"\x7fELF"; -const ELF_CLASS_64: u8 = 2; -const ELF_DATA_LE: u8 = 1; -const EM_LOONGARCH: u16 = 258; -const PT_LOAD: u32 = 1; -const LOONGARCH_DMW_MASK: u64 = (1u64 << 48) - 1; - -#[derive(Clone, Copy, Debug)] -pub struct ElfInfo { - pub entry: GuestPhysAddr, -} - -#[derive(Clone, Copy, Debug)] -struct ProgramHeader { - p_type: u32, - p_offset: u64, - p_paddr: u64, - p_filesz: u64, - p_memsz: u64, -} - -pub fn try_load(image: &[u8], vm: AxVMRef) -> AxResult> { - let Some(header) = Header::parse(image)? else { - return Ok(None); - }; - - for idx in 0..header.e_phnum { - let ph = read_program_header(image, &header, idx)?; - if ph.p_type != PT_LOAD || ph.p_memsz == 0 { - continue; - } - - let file_start = ph.p_offset as usize; - let file_size = ph.p_filesz as usize; - let file_end = file_start.checked_add(file_size).ok_or_else(|| { - ax_err_type!( - InvalidInput, - "LoongArch ELF LOAD segment file range overflows usize" - ) - })?; - let mem_size = ph.p_memsz as usize; - if file_end > image.len() { - return Err(ax_err_type!( - InvalidInput, - format!( - "LoongArch ELF LOAD segment exceeds image size: offset {:#x}, filesz {:#x}, image {:#x}", - ph.p_offset, - ph.p_filesz, - image.len() - ) - )); - } - if ph.p_filesz > ph.p_memsz { - return Err(ax_err_type!( - InvalidInput, - "LoongArch ELF LOAD segment filesz is larger than memsz" - )); - } - - let load_gpa = GuestPhysAddr::from((ph.p_paddr & LOONGARCH_DMW_MASK) as usize); - info!( - "Loading LoongArch ELF segment: paddr={:#x} -> gpa={:#x}, filesz={:#x}, memsz={:#x}", - ph.p_paddr, - load_gpa.as_usize(), - ph.p_filesz, - ph.p_memsz - ); - - zero_vm_memory(load_gpa, mem_size, vm.clone())?; - load_vm_image_from_memory(&image[file_start..file_end], load_gpa, vm.clone())?; - } - - Ok(Some(ElfInfo { - entry: GuestPhysAddr::from(header.e_entry as usize), - })) -} - -struct Header { - e_entry: u64, - e_phoff: u64, - e_phentsize: u16, - e_phnum: u16, -} - -impl Header { - fn parse(image: &[u8]) -> AxResult> { - if image.len() < 64 || &image[0..4] != ELF_MAGIC { - return Ok(None); - } - if image[4] != ELF_CLASS_64 || image[5] != ELF_DATA_LE { - return Err(ax_err_type!( - InvalidInput, - "LoongArch kernel ELF must be 64-bit little-endian" - )); - } - let machine = read_u16(image, 18)?; - if machine != EM_LOONGARCH { - return Ok(None); - } - - let e_phentsize = read_u16(image, 54)?; - if e_phentsize < 56 { - return Err(ax_err_type!( - InvalidInput, - format!("LoongArch ELF program header is too small: {e_phentsize}") - )); - } - - Ok(Some(Self { - e_entry: read_u64(image, 24)?, - e_phoff: read_u64(image, 32)?, - e_phentsize, - e_phnum: read_u16(image, 56)?, - })) - } -} - -fn read_program_header(image: &[u8], header: &Header, idx: u16) -> AxResult { - let start = (header.e_phoff as usize) - .checked_add(idx as usize * header.e_phentsize as usize) - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF phdr offset overflow"))?; - let end = start - .checked_add(header.e_phentsize as usize) - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF phdr end overflow"))?; - if end > image.len() { - return Err(ax_err_type!( - InvalidInput, - "LoongArch ELF program header exceeds image size" - )); - } - - Ok(ProgramHeader { - p_type: read_u32(image, start)?, - p_offset: read_u64(image, start + 8)?, - p_paddr: read_u64(image, start + 24)?, - p_filesz: read_u64(image, start + 32)?, - p_memsz: read_u64(image, start + 40)?, - }) -} - -fn read_u16(image: &[u8], offset: usize) -> AxResult { - let bytes = image - .get(offset..offset + 2) - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF u16 read out of range"))?; - Ok(u16::from_le_bytes(bytes.try_into().unwrap())) -} - -fn read_u32(image: &[u8], offset: usize) -> AxResult { - let bytes = image - .get(offset..offset + 4) - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF u32 read out of range"))?; - Ok(u32::from_le_bytes(bytes.try_into().unwrap())) -} - -fn read_u64(image: &[u8], offset: usize) -> AxResult { - let bytes = image - .get(offset..offset + 8) - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch ELF u64 read out of range"))?; - Ok(u64::from_le_bytes(bytes.try_into().unwrap())) -} diff --git a/os/axvisor/src/images/loongarch_image.rs b/os/axvisor/src/images/loongarch_image.rs deleted file mode 100644 index 0c39860e17..0000000000 --- a/os/axvisor/src/images/loongarch_image.rs +++ /dev/null @@ -1,103 +0,0 @@ -use ax_errno::{AxResult, ax_err_type}; -use axvm::{AxVMRef, GuestPhysAddr}; - -use crate::images::load_vm_image_from_memory; - -const LOONGARCH_IMAGE_MAGIC: &[u8; 8] = b"MZ\0\0\0\0\0\0"; -const HEADER_SIZE: usize = 0x40; -const KERNEL_ENTRY_OFFSET: usize = 0x8; -const IMAGE_SIZE_OFFSET: usize = 0x10; -const LOAD_OFFSET_OFFSET: usize = 0x18; -const PE_POINTER_OFFSET: usize = 0x3c; -const PE_HEADER_OFFSET: u32 = 0x40; - -#[derive(Clone, Copy, Debug)] -pub struct ImageInfo { - pub entry: GuestPhysAddr, - pub image_size: usize, - pub load_offset: GuestPhysAddr, -} - -pub fn try_load(image: &[u8], vm: AxVMRef) -> AxResult> { - let Some(info) = parse_info(image)? else { - return Ok(None); - }; - - validate_image_size(image, info.image_size)?; - let image = &image[..info.image_size]; - load_vm_image_from_memory(image, info.load_offset, vm)?; - Ok(Some(info)) -} - -pub fn parse_info(image: &[u8]) -> AxResult> { - let Some(header) = Header::parse(image)? else { - return Ok(None); - }; - - Ok(Some(ImageInfo { - entry: GuestPhysAddr::from(header.entry), - image_size: header.image_size, - load_offset: GuestPhysAddr::from(header.load_offset), - })) -} - -struct Header { - entry: usize, - image_size: usize, - load_offset: usize, -} - -impl Header { - fn parse(image: &[u8]) -> AxResult> { - if image.len() < HEADER_SIZE - || &image[..LOONGARCH_IMAGE_MAGIC.len()] != LOONGARCH_IMAGE_MAGIC - { - return Ok(None); - } - if read_u32(image, PE_POINTER_OFFSET)? != PE_HEADER_OFFSET { - return Ok(None); - } - - let image_size = read_u64(image, IMAGE_SIZE_OFFSET)? as usize; - if image_size == 0 { - return Err(ax_err_type!( - InvalidInput, - format!("LoongArch Linux Image size is invalid: header={image_size:#x}") - )); - } - - Ok(Some(Self { - entry: read_u64(image, KERNEL_ENTRY_OFFSET)? as usize, - image_size, - load_offset: read_u64(image, LOAD_OFFSET_OFFSET)? as usize, - })) - } -} - -fn validate_image_size(image: &[u8], image_size: usize) -> AxResult { - if image.len() < image_size { - return Err(ax_err_type!( - InvalidInput, - format!( - "LoongArch Linux Image size is invalid: image={:#x}, header={:#x}", - image.len(), - image_size - ) - )); - } - Ok(()) -} - -fn read_u32(image: &[u8], offset: usize) -> AxResult { - let bytes = image - .get(offset..offset + 4) - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch Image u32 read out of range"))?; - Ok(u32::from_le_bytes(bytes.try_into().unwrap())) -} - -fn read_u64(image: &[u8], offset: usize) -> AxResult { - let bytes = image - .get(offset..offset + 8) - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch Image u64 read out of range"))?; - Ok(u64::from_le_bytes(bytes.try_into().unwrap())) -} diff --git a/os/axvisor/src/images/loongarch_linux.rs b/os/axvisor/src/images/loongarch_linux.rs deleted file mode 100644 index dbc8fecb77..0000000000 --- a/os/axvisor/src/images/loongarch_linux.rs +++ /dev/null @@ -1,240 +0,0 @@ -use alloc::vec::Vec; - -use ax_errno::{AxResult, ax_err_type}; -use axvm::{AxVMRef, VMMemoryRegion}; -use axvmconfig::AxVMCrateConfig; - -use crate::images::load_vm_image_from_memory; - -const BOOTINFO_GPA: usize = 0x0008_0000; -const DTB_GPA: usize = 0x0010_0000; -const CMDLINE_GPA: usize = BOOTINFO_GPA; -const VENDOR_GPA: usize = BOOTINFO_GPA + 0x1000; -const SYSTAB_GPA: usize = BOOTINFO_GPA + 0x2000; -const CONFIG_TABLE_GPA: usize = BOOTINFO_GPA + 0x3000; -const BOOT_MEMMAP_GPA: usize = BOOTINFO_GPA + 0x4000; -const INITRD_TABLE_GPA: usize = BOOTINFO_GPA + 0x5000; -const BOOT_STACK_GPA: usize = 0x000f_0000; -const BOOT_STACK_SIZE: usize = 0x0001_0000; -const EFI_MEMORY_WB: u64 = 1 << 3; -const EFI_SYSTEM_TABLE_SIGNATURE: u64 = 0x5453_5953_2049_4249; -const EFI_2_10_SYSTEM_TABLE_REVISION: u32 = (2 << 16) | 10; -const EFI_MEMORY_DESCRIPTOR_VERSION: u32 = 1; -const EFI_LOADER_DATA: u32 = 2; -const EFI_CONVENTIONAL_MEMORY: u32 = 7; -const EFI_MEMORY_DESC_SIZE: usize = 40; -const DMA_IDENTITY_RAM_END: usize = 0x1000_0000; - -pub fn setup_bootinfo(vm: AxVMRef, crate_config: &AxVMCrateConfig) -> AxResult { - let bootargs = crate_config - .kernel - .cmdline - .clone() - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch Linux requires kernel.cmdline"))?; - if !has_cmdline_arg(&bootargs, "init") && !has_cmdline_arg(&bootargs, "rdinit") { - warn!("LoongArch Linux cmdline has no init= or rdinit= argument"); - } - if !has_cmdline_arg(&bootargs, "console") { - warn!("LoongArch Linux cmdline has no console= argument"); - } - - let mut cmdline = [0u8; 4096]; - let bytes = bootargs.as_bytes(); - let len = bytes.len().min(cmdline.len() - 1); - cmdline[..len].copy_from_slice(&bytes[..len]); - load_vm_image_from_memory(&cmdline, CMDLINE_GPA.into(), vm.clone())?; - - let mut vendor = [0u8; 64]; - let vendor_utf16 = [ - b'A' as u16, - b'x' as u16, - b'v' as u16, - b'i' as u16, - b's' as u16, - b'o' as u16, - b'r' as u16, - 0, - ]; - for (idx, ch) in vendor_utf16.iter().enumerate() { - vendor[idx * 2..idx * 2 + 2].copy_from_slice(&ch.to_le_bytes()); - } - load_vm_image_from_memory(&vendor, VENDOR_GPA.into(), vm.clone())?; - - let vm_regions = vm.memory_regions(); - let regions = efi_memory_regions(&vm_regions, crate_config); - let efi_region_count = regions - .iter() - .filter(|region| region.gpa.as_usize() < DMA_IDENTITY_RAM_END) - .count(); - let map_size = efi_region_count * EFI_MEMORY_DESC_SIZE; - let mut boot_memmap = Vec::new(); - write_u64(&mut boot_memmap, map_size as u64); - write_u64(&mut boot_memmap, EFI_MEMORY_DESC_SIZE as u64); - write_u32(&mut boot_memmap, EFI_MEMORY_DESCRIPTOR_VERSION); - write_u32(&mut boot_memmap, 0); - write_u64(&mut boot_memmap, 0); - write_u64(&mut boot_memmap, map_size as u64); - for region in ®ions { - let gpa = region.gpa.as_usize() as u64; - if region.gpa.as_usize() >= DMA_IDENTITY_RAM_END { - continue; - } - let pages = (region.size() as u64).div_ceil(4096); - let mem_type = if region.gpa.as_usize() == BOOTINFO_GPA || region.gpa.as_usize() == DTB_GPA - { - EFI_LOADER_DATA - } else { - EFI_CONVENTIONAL_MEMORY - }; - write_efi_memory_desc(&mut boot_memmap, gpa, pages, mem_type); - } - load_vm_image_from_memory(&boot_memmap, BOOT_MEMMAP_GPA.into(), vm.clone())?; - - let (dtb_addr, initrd_range) = vm.with_config(|config| { - let initrd_range = config.image_config.ramdisk.as_ref().and_then(|ramdisk| { - let size = ramdisk.size?; - let start = ramdisk.load_gpa.as_usize() as u64; - Some((start, size as u64)) - }); - (config.image_config.dtb_load_gpa, initrd_range) - }); - let mut config_table = Vec::new(); - write_guid( - &mut config_table, - 0x800f683f, - 0xd08b, - 0x423a, - &[0xa2, 0x93, 0x96, 0x5c, 0x3c, 0x6f, 0xe2, 0xb4], - ); - write_u64(&mut config_table, BOOT_MEMMAP_GPA as u64); - if let Some((base, size)) = initrd_range { - let mut initrd_table = Vec::new(); - write_u64(&mut initrd_table, base); - write_u64(&mut initrd_table, size); - load_vm_image_from_memory(&initrd_table, INITRD_TABLE_GPA.into(), vm.clone())?; - - write_guid( - &mut config_table, - 0x5568e427, - 0x68fc, - 0x4f3d, - &[0xac, 0x74, 0xca, 0x55, 0x52, 0x31, 0xcc, 0x68], - ); - write_u64(&mut config_table, INITRD_TABLE_GPA as u64); - } - if let Some(dtb_addr) = dtb_addr { - write_guid( - &mut config_table, - 0xb1b621d5, - 0xf19c, - 0x41a5, - &[0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0], - ); - write_u64(&mut config_table, dtb_addr.as_usize() as u64); - } - load_vm_image_from_memory(&config_table, CONFIG_TABLE_GPA.into(), vm.clone())?; - - let mut systab = Vec::new(); - write_u64(&mut systab, EFI_SYSTEM_TABLE_SIGNATURE); - write_u32(&mut systab, EFI_2_10_SYSTEM_TABLE_REVISION); - write_u32(&mut systab, 120); - write_u32(&mut systab, 0); - write_u32(&mut systab, 0); - write_u64(&mut systab, VENDOR_GPA as u64); - write_u32(&mut systab, 1); - write_u32(&mut systab, 0); - for _ in 0..8 { - write_u64(&mut systab, 0); - } - write_u64(&mut systab, (config_table.len() / 24) as u64); - write_u64(&mut systab, CONFIG_TABLE_GPA as u64); - load_vm_image_from_memory(&systab, SYSTAB_GPA.into(), vm.clone())?; - - let boot_stack = [0u8; BOOT_STACK_SIZE]; - load_vm_image_from_memory(&boot_stack, BOOT_STACK_GPA.into(), vm.clone())?; - - vm.with_config(|config| { - config.cpu_config.boot_args = [1, CMDLINE_GPA, SYSTAB_GPA]; - config.cpu_config.boot_stack_top = BOOT_STACK_GPA + BOOT_STACK_SIZE; - }); - info!( - "LoongArch Linux bootinfo: cmdline={:#x}, systab={:#x}, dtb={:?}, initrd={:?}, \ - boot_stack=[{:#x}, {:#x})", - CMDLINE_GPA, - SYSTAB_GPA, - dtb_addr, - initrd_range, - BOOT_STACK_GPA, - BOOT_STACK_GPA + BOOT_STACK_SIZE - ); - - Ok(()) -} - -fn efi_memory_regions<'a>( - regions: &'a [VMMemoryRegion], - crate_config: &AxVMCrateConfig, -) -> Vec<&'a VMMemoryRegion> { - let configured_region_count = if crate_config.kernel.configured_memory_region_count == 0 { - crate_config.kernel.memory_regions.len() - } else { - crate_config - .kernel - .configured_memory_region_count - .min(crate_config.kernel.memory_regions.len()) - }; - - crate_config - .kernel - .memory_regions - .iter() - .take(configured_region_count) - .filter_map(|cfg| { - let region = regions - .iter() - .find(|region| region.gpa.as_usize() == cfg.gpa && region.size() == cfg.size); - if region.is_none() { - warn!( - "Configured guest memory region [{:#x}, {:#x}) is not mapped; skipping EFI memmap entry", - cfg.gpa, - cfg.gpa + cfg.size - ); - } - region - }) - .collect() -} - -fn has_cmdline_arg(cmdline: &str, name: &str) -> bool { - cmdline - .split_ascii_whitespace() - .any(|arg| arg.split_once('=').is_some_and(|(key, _)| key == name)) -} - -fn write_efi_memory_desc(buf: &mut Vec, phys_addr: u64, num_pages: u64, mem_type: u32) { - write_u32(buf, mem_type); - write_u32(buf, 0); - write_u64(buf, phys_addr); - write_u64(buf, 0); - write_u64(buf, num_pages); - write_u64(buf, EFI_MEMORY_WB); -} - -fn write_guid(buf: &mut Vec, a: u32, b: u16, c: u16, d: &[u8; 8]) { - write_u32(buf, a); - write_u16(buf, b); - write_u16(buf, c); - buf.extend_from_slice(d); -} - -fn write_u16(buf: &mut Vec, value: u16) { - buf.extend_from_slice(&value.to_le_bytes()); -} - -fn write_u32(buf: &mut Vec, value: u32) { - buf.extend_from_slice(&value.to_le_bytes()); -} - -fn write_u64(buf: &mut Vec, value: u64) { - buf.extend_from_slice(&value.to_le_bytes()); -} diff --git a/os/axvisor/src/images/loongarch_zboot.rs b/os/axvisor/src/images/loongarch_zboot.rs deleted file mode 100644 index a1e25c4944..0000000000 --- a/os/axvisor/src/images/loongarch_zboot.rs +++ /dev/null @@ -1,185 +0,0 @@ -use alloc::vec::Vec; - -use ax_errno::{AxResult, ax_err_type}; -use axvm::{AxVMRef, GuestPhysAddr}; -use ruzstd::{decoding::StreamingDecoder, decoding::errors::FrameDecoderError, io::Read}; - -use super::{load_vm_image_from_memory, loongarch_image}; - -const ZBOOT_MAGIC: &[u8; 8] = b"MZ\0\0zimg"; -const HEADER_SIZE: usize = 0x40; -const PAYLOAD_INFO_OFFSET: usize = 0x8; -const PAYLOAD_OFFSET_BITS: u64 = 32; -const PAYLOAD_OFFSET_MASK: u64 = (1 << PAYLOAD_OFFSET_BITS) - 1; -const FORMAT_OFFSET: usize = 0x18; -const FORMAT_ZSTD: &[u8; 4] = b"zstd"; -const STREAM_CHUNK_SIZE: usize = 64 * 1024; - -#[derive(Debug)] -pub struct ZbootImage { - pub payload: Vec, -} - -pub fn decompress(image: &[u8]) -> AxResult> { - let Some(header) = Header::parse(image)? else { - return Ok(None); - }; - - let compressed = image - .get(header.payload_offset..header.payload_end()) - .ok_or_else(|| { - ax_err_type!( - InvalidInput, - format!( - "LoongArch zboot payload range [{:#x}, {:#x}) exceeds image size {:#x}", - header.payload_offset, - header.payload_end(), - image.len() - ) - ) - })?; - - let mut decoder = StreamingDecoder::new(compressed).map_err(decoder_error)?; - let mut payload = Vec::with_capacity(header.payload_size); - decoder.read_to_end(&mut payload).map_err(|err| { - ax_err_type!( - InvalidInput, - format!("failed to decompress LoongArch zboot zstd payload: {err}") - ) - })?; - - info!( - "Decompressed LoongArch zboot image: payload_offset={:#x}, compressed={:#x}, decompressed={:#x}", - header.payload_offset, - header.payload_size, - payload.len() - ); - - Ok(Some(ZbootImage { payload })) -} - -pub fn try_load_streamed_image( - image: &[u8], - vm: AxVMRef, -) -> AxResult> { - let Some(header) = Header::parse(image)? else { - return Ok(None); - }; - - let compressed = compressed_payload(image, &header)?; - let mut decoder = StreamingDecoder::new(compressed).map_err(decoder_error)?; - let mut image_header = [0u8; HEADER_SIZE]; - decoder.read_exact(&mut image_header).map_err(|err| { - ax_err_type!( - InvalidInput, - format!("failed to decompress LoongArch zboot image header: {err}") - ) - })?; - - let Some(info) = loongarch_image::parse_info(&image_header)? else { - return Ok(None); - }; - load_vm_image_from_memory(&image_header, info.load_offset, vm.clone())?; - - let mut chunk = [0u8; STREAM_CHUNK_SIZE]; - let mut written = image_header.len(); - while written < info.image_size { - let read_len = (info.image_size - written).min(chunk.len()); - decoder.read_exact(&mut chunk[..read_len]).map_err(|err| { - ax_err_type!( - InvalidInput, - format!("failed to stream LoongArch zboot payload: {err}") - ) - })?; - load_vm_image_from_memory( - &chunk[..read_len], - GuestPhysAddr::from(info.load_offset.as_usize() + written), - vm.clone(), - )?; - written += read_len; - } - - info!( - "Streamed LoongArch zboot Image: payload_offset={:#x}, compressed={:#x}, image_size={:#x}, load_offset={:#x}", - header.payload_offset, - header.payload_size, - info.image_size, - info.load_offset.as_usize() - ); - - Ok(Some(info)) -} - -fn compressed_payload<'a>(image: &'a [u8], header: &Header) -> AxResult<&'a [u8]> { - image - .get(header.payload_offset..header.payload_end()) - .ok_or_else(|| { - ax_err_type!( - InvalidInput, - format!( - "LoongArch zboot payload range [{:#x}, {:#x}) exceeds image size {:#x}", - header.payload_offset, - header.payload_end(), - image.len() - ) - ) - }) -} - -fn decoder_error(err: FrameDecoderError) -> ax_errno::AxError { - ax_err_type!( - InvalidInput, - format!("failed to initialize LoongArch zboot zstd decoder: {err:?}") - ) -} - -struct Header { - payload_offset: usize, - payload_size: usize, -} - -impl Header { - fn parse(image: &[u8]) -> AxResult> { - if image.len() < HEADER_SIZE || &image[..ZBOOT_MAGIC.len()] != ZBOOT_MAGIC { - return Ok(None); - } - if image - .get(FORMAT_OFFSET..FORMAT_OFFSET + FORMAT_ZSTD.len()) - .is_none_or(|format| format != FORMAT_ZSTD) - { - return Err(ax_err_type!( - InvalidInput, - "unsupported LoongArch zboot compression format" - )); - } - - let payload_info = read_u64(image, PAYLOAD_INFO_OFFSET)?; - let payload_offset = (payload_info & PAYLOAD_OFFSET_MASK) as usize; - let payload_size = (payload_info >> PAYLOAD_OFFSET_BITS) as usize; - if payload_offset < HEADER_SIZE || payload_size == 0 { - return Err(ax_err_type!( - InvalidInput, - format!( - "invalid LoongArch zboot payload metadata: offset={:#x}, size={:#x}", - payload_offset, payload_size - ) - )); - } - - Ok(Some(Self { - payload_offset, - payload_size, - })) - } - - fn payload_end(&self) -> usize { - self.payload_offset.saturating_add(self.payload_size) - } -} - -fn read_u64(image: &[u8], offset: usize) -> AxResult { - let bytes = image - .get(offset..offset + 8) - .ok_or_else(|| ax_err_type!(InvalidInput, "LoongArch zboot u64 read out of range"))?; - Ok(u64::from_le_bytes(bytes.try_into().unwrap())) -} diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index 31f105073f..b05a9d920a 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -34,14 +34,6 @@ struct LoongArchUefiRamRegion { } mod linux; -#[cfg(target_arch = "loongarch64")] -mod loongarch_elf; -#[cfg(target_arch = "loongarch64")] -mod loongarch_image; -#[cfg(target_arch = "loongarch64")] -mod loongarch_linux; -#[cfg(target_arch = "loongarch64")] -mod loongarch_zboot; #[cfg(target_arch = "x86_64")] mod x86; #[cfg(target_arch = "x86_64")] @@ -230,9 +222,6 @@ impl ImageLoader { } } - #[cfg(target_arch = "loongarch64")] - loongarch_linux::setup_bootinfo(self.vm.clone(), &self.config)?; - self.load_boot_image_from_memory(vm_imags.bios)?; Ok(()) @@ -448,50 +437,6 @@ impl ImageLoader { } fn load_kernel_from_memory(&self, kernel: &[u8]) -> AxResult { - #[cfg(target_arch = "loongarch64")] - if let Some(info) = loongarch_zboot::try_load_streamed_image(kernel, self.vm.clone())? { - self.vm.with_config(|config| { - config.cpu_config.bsp_entry = info.entry; - config.cpu_config.ap_entry = info.entry; - }); - info!( - "LoongArch zboot Image entry set to {:#x}", - info.entry.as_usize() - ); - return Ok(()); - } - - #[cfg(target_arch = "loongarch64")] - if let Some(image) = loongarch_zboot::decompress(kernel)? { - return self.load_kernel_from_memory(&image.payload); - } - - #[cfg(target_arch = "loongarch64")] - if let Some(info) = loongarch_elf::try_load(kernel, self.vm.clone())? { - self.vm.with_config(|config| { - config.cpu_config.bsp_entry = info.entry; - config.cpu_config.ap_entry = info.entry; - }); - info!( - "LoongArch ELF kernel entry set to {:#x}", - info.entry.as_usize() - ); - return Ok(()); - } - - #[cfg(target_arch = "loongarch64")] - if let Some(info) = loongarch_image::try_load(kernel, self.vm.clone())? { - self.vm.with_config(|config| { - config.cpu_config.bsp_entry = info.entry; - config.cpu_config.ap_entry = info.entry; - }); - info!( - "LoongArch Linux Image entry set to {:#x}", - info.entry.as_usize() - ); - return Ok(()); - } - load_vm_image_from_memory(kernel, self.kernel_load_gpa, self.vm.clone()) } @@ -808,29 +753,6 @@ pub fn load_vm_image_from_memory( } } -#[cfg(target_arch = "loongarch64")] -pub fn zero_vm_memory(load_addr: GuestPhysAddr, size: usize, vm: AxVMRef) -> AxResult { - let image_load_regions = vm.get_image_load_region(load_addr, size)?; - let mut zeroed_size = 0; - - for region in image_load_regions { - unsafe { - core::ptr::write_bytes(region.as_mut_ptr(), 0, region.len()); - } - axvm::clean_dcache_range((region.as_ptr() as usize).into(), region.len()); - zeroed_size += region.len(); - } - - if zeroed_size == size { - Ok(()) - } else { - ax_err!( - InvalidData, - format!("VM memory was only partially zeroed: {zeroed_size}/{size} bytes") - ) - } -} - fn fill_vm_region(load_addr: GuestPhysAddr, size: usize, byte: u8, vm: AxVMRef) -> AxResult { let image_load_regions = vm.get_image_load_region(load_addr, size)?; let mut filled_size = 0; @@ -1215,9 +1137,6 @@ pub mod fs { } } - #[cfg(target_arch = "loongarch64")] - loongarch_linux::setup_bootinfo(loader.vm.clone(), &loader.config)?; - Ok(()) } diff --git a/platforms/ax-plat-loongarch64-qemu-virt/axconfig.toml b/platforms/ax-plat-loongarch64-qemu-virt/axconfig.toml index 46ef803a2c..0894c4ddd6 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/axconfig.toml +++ b/platforms/ax-plat-loongarch64-qemu-virt/axconfig.toml @@ -34,9 +34,9 @@ phys-virt-offset = "0x9000_0000_0000_0000" # uint phys-bus-offset = 0 # uint # Base physical address of the kernel image. -kernel-base-paddr = 0x8000_0000 # uint +kernel-base-paddr = 0x0020_0000 # uint # Base virtual address of the kernel image. -kernel-base-vaddr = "0x9000_0000_8000_0000" # uint +kernel-base-vaddr = "0x9000_0000_0020_0000" # uint # Kernel page-table-backed address space. # # LoongArch64 uses the 0x9000_0000_0000_0000 DMW window for cached direct diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/console.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/console.rs index cac655416e..3347c717e2 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/console.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/console.rs @@ -12,7 +12,7 @@ use crate::config::{devices::UART_PADDR, plat::PHYS_VIRT_OFFSET}; static UART: LazyInit>> = LazyInit::new(); const CSR_GSTAT: u16 = 0x50; -const GSTAT_PVM: usize = 1 << 1; +const GSTAT_PGM: usize = 1 << 1; fn uart_config(input_irq_enabled: bool) -> Config { Config { @@ -31,7 +31,7 @@ fn in_guest_mode() -> bool { unsafe { core::arch::asm!("csrrd {}, {}", out(reg) gstat, const CSR_GSTAT); } - (gstat & GSTAT_PVM) != 0 + (gstat & GSTAT_PGM) != 0 } pub(crate) fn init_early() { diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs index 9ca6b7e2bd..a24172d892 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq.rs @@ -1,6 +1,3 @@ -#[cfg(feature = "hypervisor")] -use core::sync::atomic::{AtomicPtr, AtomicUsize, Ordering}; - use ax_plat::irq::{IpiTarget, IrqIf, dispatch_irq}; use loongArch64::{ iocsr::{iocsr_read_w, iocsr_write_w}, @@ -16,9 +13,6 @@ use crate::config::devices::{EIOINTC_IRQ, IPI_IRQ, TIMER_IRQ}; mod eiointc; mod pch_pic; -/// The maximum number of hypervisor-routed IRQs. -#[cfg(feature = "hypervisor")] -pub const MAX_IRQ_COUNT: usize = 256; const IOCSR_IPI_SEND_CPU_SHIFT: u32 = 16; const IOCSR_IPI_SEND_BLOCKING: u32 = 1 << 31; @@ -28,21 +22,6 @@ const IOCSR_IPI_STATUS: usize = 0x1000; const IOCSR_IPI_ENABLE: usize = 0x1004; const IOCSR_IPI_CLEAR: usize = 0x100c; const IOCSR_IPI_SEND: usize = 0x1040; -#[cfg(feature = "hypervisor")] -const IRQ_ROUTE_NONE: usize = 0; -#[cfg(feature = "hypervisor")] -const IRQ_TARGET_NONE: usize = usize::MAX; -#[cfg(feature = "hypervisor")] -const IRQ_TARGET_VM_SHIFT: usize = 32; - -#[cfg(feature = "hypervisor")] -static VIRTUAL_IRQ_INJECTOR: AtomicPtr<()> = AtomicPtr::new(core::ptr::null_mut()); -#[cfg(feature = "hypervisor")] -static GUEST_IRQ_ROUTES: [AtomicUsize; MAX_IRQ_COUNT] = - [const { AtomicUsize::new(IRQ_ROUTE_NONE) }; MAX_IRQ_COUNT]; -#[cfg(feature = "hypervisor")] -static GUEST_IRQ_TARGETS: [AtomicUsize; MAX_IRQ_COUNT] = - [const { AtomicUsize::new(IRQ_TARGET_NONE) }; MAX_IRQ_COUNT]; fn make_ipi_send_value(cpu_id: usize, vector: u32, blocking: bool) -> u32 { let mut value = (cpu_id as u32) << IOCSR_IPI_SEND_CPU_SHIFT | vector; @@ -52,70 +31,6 @@ fn make_ipi_send_value(cpu_id: usize, vector: u32, blocking: bool) -> u32 { value } -/// Registers the virtual interrupt injector used by hypervisor builds. -#[cfg(feature = "hypervisor")] -pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { - VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); - info!("LoongArch platform virtual IRQ injector registered"); -} - -#[cfg(feature = "hypervisor")] -fn encode_guest_vector(vector: usize) -> usize { - vector + 1 -} - -#[cfg(feature = "hypervisor")] -fn decode_guest_vector(encoded: usize) -> Option { - (encoded != IRQ_ROUTE_NONE).then_some(encoded - 1) -} - -#[cfg(feature = "hypervisor")] -fn encode_guest_target(vm_id: usize, vcpu_id: usize) -> usize { - (vm_id << IRQ_TARGET_VM_SHIFT) | vcpu_id -} - -#[cfg(feature = "hypervisor")] -fn decode_guest_target(encoded: usize) -> Option<(usize, usize)> { - (encoded != IRQ_TARGET_NONE).then_some(( - encoded >> IRQ_TARGET_VM_SHIFT, - encoded & ((1usize << IRQ_TARGET_VM_SHIFT) - 1), - )) -} - -#[cfg(feature = "hypervisor")] -fn guest_route(physical_irq: usize) -> Option<(usize, usize, usize)> { - if physical_irq >= MAX_IRQ_COUNT { - return None; - } - let guest_vector = decode_guest_vector(GUEST_IRQ_ROUTES[physical_irq].load(Ordering::Acquire))?; - let (vm_id, vcpu_id) = - decode_guest_target(GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire))?; - Some((vm_id, vcpu_id, guest_vector)) -} - -/// Routes one physical EIOINTC/PCH-PIC IRQ to a guest CPU interrupt vector. -#[cfg(feature = "hypervisor")] -pub fn register_guest_irq_route( - physical_irq: usize, - vm_id: usize, - vcpu_id: usize, - guest_vector: usize, -) { - if physical_irq >= MAX_IRQ_COUNT { - warn!("LoongArch guest IRQ route ignored: physical IRQ {physical_irq} out of range"); - return; - } - - GUEST_IRQ_ROUTES[physical_irq].store(encode_guest_vector(guest_vector), Ordering::Release); - GUEST_IRQ_TARGETS[physical_irq].store(encode_guest_target(vm_id, vcpu_id), Ordering::Release); - eiointc::enable_irq(physical_irq); - pch_pic::enable_irq(physical_irq); - debug!( - "LoongArch guest IRQ route: physical_irq={}, target=VM[{}] VCpu[{}], guest_vector={}", - physical_irq, vm_id, vcpu_id, guest_vector - ); -} - pub(crate) fn init() { eiointc::init(); pch_pic::init(); @@ -152,7 +67,6 @@ impl IrqType { match self { IrqType::Timer => Some(LineBasedInterrupt::TIMER), IrqType::Ipi => Some(LineBasedInterrupt::IPI), - IrqType::Io => LineBasedInterrupt::from_bits(1 << EIOINTC_IRQ), _ => None, } } @@ -209,31 +123,6 @@ impl IrqIf for IrqIfImpl { debug!("Spurious external IRQ"); return None; }; - - #[cfg(feature = "hypervisor")] - if let Some((vm_id, vcpu_id, guest_vector)) = guest_route(ex_irq) { - let injector = VIRTUAL_IRQ_INJECTOR.load(Ordering::Acquire); - if injector.is_null() { - warn!( - "LoongArch guest-owned IRQ {ex_irq} has no virtual IRQ injector; leaving \ - it pending for guest" - ); - return Some(ex_irq); - } - - // SAFETY: The injector is registered through - // register_virtual_irq_injector as a valid function pointer. - unsafe { - core::mem::transmute::<*mut (), fn(usize, usize, usize, usize)>(injector)( - vm_id, - vcpu_id, - guest_vector, - ex_irq, - ); - } - return Some(ex_irq); - } - irq = IrqType::Ex(ex_irq); } @@ -305,20 +194,3 @@ impl IrqIf for IrqIfImpl { } } } - -#[cfg(feature = "hypervisor")] -#[impl_plat_interface] -impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { - fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { - register_virtual_irq_injector(injector); - } - - fn register_guest_irq_route( - physical_irq: usize, - vm_id: usize, - vcpu_id: usize, - guest_vector: usize, - ) { - register_guest_irq_route(physical_irq, vm_id, vcpu_id, guest_vector); - } -} diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs index 3c0579ad29..26d2c9a11f 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/eiointc.rs @@ -63,7 +63,6 @@ pub fn enable_irq(irq: usize) { iocsr_write_d(addr, iocsr_read_d(addr) | bit); } } - pub fn disable_irq(irq: usize) { let (offset, bit) = split_bit(irq); let addr = EIOINTC_REG_ENABLE + offset; @@ -79,10 +78,6 @@ pub fn claim_irq() -> Option { } None } -/// Write back the ISR bit to acknowledge (clear) the interrupt. -/// Must be called after claim_irq() to allow the EIOINTC to deliver -/// subsequent interrupts. In hypervisor passthrough mode, the host must not -/// claim the IRQ first; the guest owns the claim/complete sequence. pub fn complete_irq(irq: usize) { let (offset, bit) = split_bit(irq); iocsr_write_d(EIOINTC_REG_ISR + offset, bit); diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/lib.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/lib.rs index dc058cf3f9..5487f3d547 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/lib.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/lib.rs @@ -28,10 +28,8 @@ mod boot; mod console; mod drivers; mod init; -#[cfg(all(feature = "irq", not(feature = "hypervisor")))] +#[cfg(feature = "irq")] mod irq; -#[cfg(feature = "hypervisor")] -pub mod irq; mod mem; #[cfg(feature = "smp")] mod mp; diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/mem.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/mem.rs index 76e96e89e4..abbaccc3ea 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/mem.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/mem.rs @@ -155,10 +155,7 @@ impl MemIf for MemIfImpl { /// Note that the ranges returned should not include the range where the /// kernel is loaded. fn reserved_phys_ram_ranges() -> &'static [RawRange] { - // AxVisor is loaded from high memory on LoongArch. Keep the low RAM - // bank out of the host allocator so passthrough devices can DMA to - // guest identity-mapped low memory. - &[(LOW_MEMORY_BASE, LOW_MEMORY_SIZE)] + &[(0, 0x200000)] // boot_info + fdt } /// Returns all device memory (MMIO) ranges on the platform. diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/time.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/time.rs index 1f86bb4f78..c5fb292e5c 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/time.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/time.rs @@ -123,13 +123,11 @@ impl TimeIf for TimeIfImpl { /// LoongArch64 TCFG CSR: #[cfg(feature = "irq")] fn set_oneshot_timer(deadline_ns: u64) { - use loongArch64::register::{tcfg, ticlr}; + use loongArch64::register::tcfg; let ticks_now = Self::current_ticks(); let ticks_deadline = Self::nanos_to_ticks(deadline_ns); let init_value = ticks_deadline.saturating_sub(ticks_now).max(1); - ticlr::clear_timer_interrupt(); - tcfg::set_periodic(false); tcfg::set_init_val(init_value as _); tcfg::set_en(true); } diff --git a/scripts/axbuild/src/axvisor/rootfs.rs b/scripts/axbuild/src/axvisor/rootfs.rs index 1168b1e6c5..b8963697fd 100644 --- a/scripts/axbuild/src/axvisor/rootfs.rs +++ b/scripts/axbuild/src/axvisor/rootfs.rs @@ -8,9 +8,7 @@ use std::{ fs, - io::Write, path::{Path, PathBuf}, - process::Command, }; use anyhow::{Context, anyhow}; @@ -87,7 +85,6 @@ pub(crate) fn prepare_loongarch_linux_memory_vmconfigs( continue; } - ensure_loongarch_busybox_serial_init(&rootfs_path, &out_dir)?; rootfs::inject::extract_file(&rootfs_path, "/guest/linux/linux-qemu", &kernel_path) .with_context(|| { format!( @@ -152,69 +149,6 @@ fn replace_toml_string_value(content: &str, key: &str, value: &str) -> String { + "\n" } -fn ensure_loongarch_busybox_serial_init(rootfs_path: &Path, out_dir: &Path) -> anyhow::Result<()> { - let Some(inittab) = rootfs::inject::read_text_file(rootfs_path, "/etc/inittab")? else { - return Ok(()); - }; - let replacement_content = loongarch_busybox_inittab(); - if inittab == replacement_content || rootfs_file_exists(rootfs_path, "/sbin/openrc")? { - return Ok(()); - } - - fs::create_dir_all(out_dir) - .with_context(|| format!("failed to create {}", out_dir.display()))?; - let replacement = out_dir.join("inittab.busybox"); - write_text_file(&replacement, replacement_content)?; - rootfs::inject::replace_file(rootfs_path, "/etc/inittab", &replacement) - .with_context(|| format!("failed to patch /etc/inittab in {}", rootfs_path.display()))?; - Ok(()) -} - -fn loongarch_busybox_inittab() -> &'static str { - concat!( - "# /etc/inittab - BusyBox init for LoongArch AxVisor rootfs\n", - "::sysinit:/bin/mount -t proc proc /proc\n", - "::sysinit:/bin/mount -t sysfs sysfs /sys\n", - "::sysinit:/bin/mount -t devtmpfs devtmpfs /dev\n", - "ttyS0::respawn:/bin/sh\n", - "::ctrlaltdel:/sbin/reboot\n", - "::shutdown:/bin/umount -a -r\n", - ) -} - -fn rootfs_file_exists(rootfs_path: &Path, guest_path: &str) -> anyhow::Result { - let output = Command::new("debugfs") - .arg("-R") - .arg(format!("stat {guest_path}")) - .arg(rootfs_path) - .output() - .with_context(|| format!("failed to spawn debugfs for {}", rootfs_path.display()))?; - let stdout = String::from_utf8_lossy(&output.stdout); - let stderr = String::from_utf8_lossy(&output.stderr); - if stdout.contains("File not found") - || stdout.contains("File not found by ext2_lookup") - || stderr.contains("File not found") - || stderr.contains("File not found by ext2_lookup") - { - return Ok(false); - } - if output.status.success() { - return Ok(true); - } - Err(anyhow!( - "failed to stat {guest_path} in {}: {}", - rootfs_path.display(), - stderr.trim() - )) -} - -fn write_text_file(path: &Path, content: &str) -> anyhow::Result<()> { - let mut file = - fs::File::create(path).with_context(|| format!("failed to create {}", path.display()))?; - file.write_all(content.as_bytes()) - .with_context(|| format!("failed to write {}", path.display())) -} - pub(super) async fn load_patched_qemu_config( axvisor: &mut Axvisor, request: &ResolvedAxvisorRequest, From 70bf6931e85870f5b7ed04db9441714917e1f1fd Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 15 Jun 2026 10:46:41 +0800 Subject: [PATCH 22/50] opt log --- .../configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml | 4 ++-- virtualization/loongarch_vcpu/src/exception.rs | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml index 2f82d0360d..7652173e61 100644 --- a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml +++ b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml @@ -22,7 +22,7 @@ entry_point = 0x1c00_0000 image_location = "fs" # The file path of the kernel image. kernel_path = "/guest/linux/linux-qemu" -# The ELF LOAD paddr is used by the LoongArch loader; this is a fallback for flat images. +# Fallback load address for non-firmware boot paths. kernel_load_addr = 0x0020_0000 # Boot Linux through guest UEFI/ACPI, matching the LoongArch QEMU virt platform. enable_bios = true @@ -30,7 +30,7 @@ boot_protocol = "uefi" uefi_firmware_path = "/tmp/ostool/ovmf/loongarch64/code.fd" bios_load_addr = 0x1c00_0000 # Kernel command line. Rootfs mode intentionally uses virtio-blk /dev/vda. -cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw console=ttyS0,115200 earlycon=uart8250,mmio,0x1fe001e0,115200 nokaslr loglevel=8 ignore_loglevel swiotlb=1024 pci=nomsi initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" +cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw console=ttyS0,115200 quiet loglevel=3 nokaslr swiotlb=1024 pci=nomsi initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" # Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`). # For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`, 2 means `MAP_RESERVED`. diff --git a/virtualization/loongarch_vcpu/src/exception.rs b/virtualization/loongarch_vcpu/src/exception.rs index 6668347df3..944f739be5 100644 --- a/virtualization/loongarch_vcpu/src/exception.rs +++ b/virtualization/loongarch_vcpu/src/exception.rs @@ -1615,7 +1615,7 @@ pub fn handle_exception_sync( let ecode = get_exception_code(ctx); let esubcode = get_exception_subcode(ctx); if SYNC_EXIT_LOGS.fetch_add(1, Ordering::Relaxed) < 32 { - log::warn!( + log::trace!( "LoongArch guest sync exit: ecode={:#x}, esubcode={:#x}, guest_pc={:#x}, \ host_era={:#x}, gera={:#x}, badv={:#x}, badi={:#x}, guest_is={:#x}, \ host_estat={:#x}, tlbrbadv={:#x}, tlbrera={:#x}", @@ -1633,7 +1633,7 @@ pub fn handle_exception_sync( ); } - log::debug!( + log::trace!( "LoongArch guest sync exit: ecode={:#x}, esubcode={:#x}, guest_pc={:#x}, host_era={:#x}, \ gera={:#x}, badv={:#x}, badi={:#x}, host_estat={:#x}, tlbrera={:#x}", ecode, @@ -1655,7 +1655,7 @@ pub fn handle_exception_sync( } ctx.sepc = get_guest_pc(ctx); if NESTED_FAULT_LOGS.fetch_add(1, Ordering::Relaxed) < 8 { - log::warn!( + log::trace!( "LoongArch nested fault from host refill: badv={:#x}, gpa={:#x}, pc={:#x}, \ crmd={:#x}, eentry={:#x}, tlbrentry={:#x}, tlbrera={:#x}, host_estat={:#x}", badv, @@ -1708,7 +1708,7 @@ pub fn handle_exception_sync( access_flags |= MappingFlags::READ; } if NESTED_FAULT_LOGS.fetch_add(1, Ordering::Relaxed) < 8 { - log::warn!( + log::trace!( "LoongArch nested fault from regular exception: ecode={:#x}, badv={:#x}, \ gpa={:#x}, pc={:#x}, crmd={:#x}, eentry={:#x}, tlbrentry={:#x}, \ host_estat={:#x}", From 84aeaf725c9630293dc91563067a21609531afae Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 15 Jun 2026 13:29:17 +0800 Subject: [PATCH 23/50] optimize --- components/axcpu/src/loongarch64/asm.rs | 42 +----- .../someboot/src/arch/loongarch64/mod.rs | 1 - .../someboot/src/arch/loongarch64/trap.rs | 39 +++-- components/someboot/src/efi_stub/mod.rs | 1 - drivers/rdrive/src/probe/acpi.rs | 16 +-- .../page_table_entry/src/arch/loongarch64.rs | 3 +- os/arceos/api/arceos_posix_api/src/imp/io.rs | 5 +- .../api/arceos_posix_api/src/imp/task.rs | 1 - os/arceos/modules/axruntime/src/lang_items.rs | 3 - os/arceos/modules/axtask/src/run_queue.rs | 2 - .../qemu/loongarch64/linux-rootfs-smp1.toml | 2 +- platforms/axplat-dyn/src/power.rs | 1 - .../somehal/src/arch/loongarch64/eiointc.rs | 8 -- platforms/somehal/src/arch/loongarch64/mod.rs | 8 -- .../somehal/src/arch/loongarch64/pch_pic.rs | 46 ------ test-suit/arceos/c/qemu-loongarch64.toml | 2 - test-suit/arceos/rust/qemu-loongarch64.toml | 2 +- .../qemu-smp1/system/qemu-loongarch64.toml | 4 +- .../qemu-smp4/system/qemu-loongarch64.toml | 4 +- virtualization/axvm/src/vm.rs | 33 ++++- virtualization/loongarch_vcpu/src/vcpu.rs | 135 +----------------- 21 files changed, 78 insertions(+), 280 deletions(-) diff --git a/components/axcpu/src/loongarch64/asm.rs b/components/axcpu/src/loongarch64/asm.rs index 3c79599a90..7cb78e98d5 100644 --- a/components/axcpu/src/loongarch64/asm.rs +++ b/components/axcpu/src/loongarch64/asm.rs @@ -6,30 +6,9 @@ use ax_memory_addr::{PhysAddr, VirtAddr}; use loongArch64::register::{ crmd, ecfg::{self, LineBasedInterrupt}, - eentry, estat, pgdh, pgdl, tcfg, tlbrentry, tval, + eentry, pgdh, pgdl, }; -#[derive(Debug, Clone, Copy)] -/// A raw snapshot of LoongArch interrupt and timer CSRs. -pub struct IrqDebugSnapshot { - /// Current mode information CSR. - pub crmd: usize, - /// Exception configuration CSR. - pub ecfg: usize, - /// Exception status CSR. - pub estat: usize, - /// General exception entry base CSR. - pub eentry: usize, - /// TLB refill exception entry base CSR. - pub tlbrentry: usize, - /// Timer configuration CSR. - pub tcfg: usize, - /// Timer value CSR. - pub tval: usize, - /// Kernel scratch CSR used by the host trap entry to save the kernel stack. - pub ksave_ksp: usize, -} - /// Allows the current CPU to respond to interrupts. #[inline] pub fn enable_irqs() { @@ -66,25 +45,6 @@ fn set_local_irq_line_enabled(line: LineBasedInterrupt, enabled: bool) { ecfg::set_lie(new_value); } -/// Captures the local interrupt and timer CSRs for LoongArch debugging. -#[inline] -pub fn irq_debug_snapshot() -> IrqDebugSnapshot { - let ksave_ksp: usize; - unsafe { - asm!("csrrd {}, 0x30", out(reg) ksave_ksp); - } - IrqDebugSnapshot { - crmd: crmd::read().raw(), - ecfg: ecfg::read().raw(), - estat: estat::read().raw(), - eentry: eentry::read().raw(), - tlbrentry: tlbrentry::read().raw(), - tcfg: tcfg::read().raw(), - tval: tval::read().raw(), - ksave_ksp, - } -} - /// Relaxes the current CPU and waits for interrupts. /// /// It must be called with interrupts enabled, otherwise it will never return. diff --git a/components/someboot/src/arch/loongarch64/mod.rs b/components/someboot/src/arch/loongarch64/mod.rs index 9ec2e5fdae..e385b6bc95 100644 --- a/components/someboot/src/arch/loongarch64/mod.rs +++ b/components/someboot/src/arch/loongarch64/mod.rs @@ -141,7 +141,6 @@ impl ArchTrait for Arch { } fn shutdown() -> ! { - crate::console::_write_str("[someboot loongarch64] shutdown entered\n"); if efi_stub::is_uefi_available() { efi_stub::reset( efi_stub::ResetType::SHUTDOWN, diff --git a/components/someboot/src/arch/loongarch64/trap.rs b/components/someboot/src/arch/loongarch64/trap.rs index e1f0de1851..9f6371b0d4 100644 --- a/components/someboot/src/arch/loongarch64/trap.rs +++ b/components/someboot/src/arch/loongarch64/trap.rs @@ -149,9 +149,9 @@ fn tlbrentry_addr() -> usize { virt_to_phys((eentry_addr() + 80 * VECSIZE) as *const u8) } -pub fn per_cpu_trap_init(_is_primary: bool) { +pub fn per_cpu_trap_init(is_primary: bool) { setup_vint_size(); - configure_exception_vector(); + configure_exception_vector(is_primary); } pub(crate) fn init_entries_for_secondary() { @@ -166,11 +166,21 @@ fn setup_vint_size() { } /// 配置异常向量 -fn configure_exception_vector() { +fn configure_exception_vector(verbose: bool) { let eentry_addr = eentry_addr(); + if verbose { + println!("Setting EENTRY to {:#x}", eentry_addr); + } eentry::set_eentry(eentry_addr); + let val = eentry::read().eentry(); + if verbose { + println!("EENTRY set to {:#x}", val); + } let tlbrentry_addr = tlbrentry_addr(); + if verbose { + println!("Setting TLBRENTRY to {:#x}", tlbrentry_addr); + } tlbrentry::set_tlbrentry(tlbrentry_addr); } @@ -185,7 +195,7 @@ fn do_vint(_tf: &mut TrapFrame) { /// Page Fault 处理函数 (普通 TLB 异常: TLBL, TLBS, TLBI, TLBM, TLBNR, TLBNX, TLBPE) #[unsafe(no_mangle)] extern "C" fn do_page_fault(tf: &TrapFrame, write: usize, address: usize) -> ! { - crate::console::_write_str("[someboot trap] do_page_fault\n"); + println!("do_page_fault called"); let estat = estat::read(); let ecode = estat.ecode(); @@ -219,7 +229,7 @@ extern "C" fn do_page_fault(tf: &TrapFrame, write: usize, address: usize) -> ! { /// TLB Refill 使用独立的 CSR: TLBRERA, TLBRPRMD, TLBRBADV #[unsafe(no_mangle)] extern "C" fn do_tlb_refill(tf: &TrapFrame, address: usize) -> ! { - crate::console::_write_str("[someboot trap] do_tlb_refill\n"); + println!("do_tlb_refill called"); panic_on_exception( "TLB REFILL", @@ -653,7 +663,7 @@ global_asm!( /// 保留异常处理函数 #[unsafe(no_mangle)] extern "C" fn do_reserved_exception(tf: &TrapFrame) -> ! { - crate::console::_write_str("[someboot trap] do_reserved_exception\n"); + println!("*** do_reserved_exception 被调用 ***"); let estat = estat::read(); let ecode = estat.ecode(); let esubcode = estat.esubcode(); @@ -676,13 +686,24 @@ extern "C" fn do_reserved_exception(tf: &TrapFrame) -> ! { /// ADE: Address Error - Memory access (内存访问时地址错误) #[unsafe(no_mangle)] extern "C" fn do_address_error(tf: &TrapFrame, badv: usize) -> ! { - crate::console::_write_str("[someboot trap] do_address_error\n"); + println!("\n*** do_address_error 被调用 ***"); + println!("BADV (错误地址): {:#x}", badv); let estat = estat::read(); let ecode = estat.ecode(); let esubcode = estat.esubcode(); + println!("ESTAT.ECODE: {:#x}", ecode); + println!("ESTAT.ESUBCODE: {:#x}", esubcode); + println!("ERA (PC): {:#x}", tf.era); + + // ADF 和 ADE 都使用 Ecode 0x8，这里统一处理 + // 根据子码或其他信息区分具体类型（如果需要） let fault_type = "Address Error"; + let _ = ecode; // 避免未使用警告 + + println!("异常类型: {}", fault_type); + println!("*** 开始 panic ***\n"); panic_on_exception( "ADDRESS ERROR", @@ -698,10 +719,6 @@ extern "C" fn do_address_error(tf: &TrapFrame, badv: usize) -> ! { } fn panic_on_exception(name: &str, tf: &TrapFrame, fmt: Arguments<'_>) -> ! { - crate::console::_print(format_args!( - "[someboot trap] panic_on_exception name={name} era={:#x} prmd={:#x} sp={:#x}\n", - tf.era, tf.prmd, tf.regs.sp - )); println!( " ============================================================\n{name} \ diff --git a/components/someboot/src/efi_stub/mod.rs b/components/someboot/src/efi_stub/mod.rs index f88ec85463..1041b0d389 100644 --- a/components/someboot/src/efi_stub/mod.rs +++ b/components/someboot/src/efi_stub/mod.rs @@ -389,7 +389,6 @@ pub fn is_uefi_available() -> bool { #[cfg(target_arch = "loongarch64")] pub fn reset(reset_type: ResetType, status: Status, data: Option<&[u8]>) -> ! { - crate::console::_write_str("[someboot efi_stub] reset via UEFI\n"); info!("Resetting system via UEFI..."); uefi::runtime::reset(reset_type, status, data) } diff --git a/drivers/rdrive/src/probe/acpi.rs b/drivers/rdrive/src/probe/acpi.rs index 6d77034897..fa0aae4d6a 100644 --- a/drivers/rdrive/src/probe/acpi.rs +++ b/drivers/rdrive/src/probe/acpi.rs @@ -1546,21 +1546,13 @@ fn read_loongarch_bio_pic_entry( } let entry = unsafe { (base.add(offset) as *const RawMadtBioPic).read_unaligned() }; - let id = entry.id; - let address = entry.address; - let size = entry.size; - let gsi_base = entry.gsi_base; - info!( - "LoongArch MADT BIO_PIC: id={}, address={:#x}, size={:#x}, gsi_base={}", - id, address, size, gsi_base - ); routing.add_pch_pic(AcpiPchPic { - id, - address, - mmio_size: size, + id: entry.id, + address: entry.address, + mmio_size: entry.size, gsi_count: LOONGARCH_PCH_PIC_GSI_COUNT, - gsi_base: u32::from(gsi_base), + gsi_base: u32::from(entry.gsi_base), }); } diff --git a/memory/page_table_entry/src/arch/loongarch64.rs b/memory/page_table_entry/src/arch/loongarch64.rs index 22475c54dd..3e80cf359d 100644 --- a/memory/page_table_entry/src/arch/loongarch64.rs +++ b/memory/page_table_entry/src/arch/loongarch64.rs @@ -157,8 +157,7 @@ impl GenericPTE for LA64PTE { } fn set_paddr(&mut self, paddr: PhysAddr) { - self.0 = - (self.0 & !Self::PHYS_ADDR_MASK) | (paddr.as_usize() as u64 & Self::PHYS_ADDR_MASK); + self.0 = (self.0 & !Self::PHYS_ADDR_MASK) | (paddr.as_usize() as u64 & Self::PHYS_ADDR_MASK) } fn set_flags(&mut self, flags: MappingFlags, is_huge: bool) { diff --git a/os/arceos/api/arceos_posix_api/src/imp/io.rs b/os/arceos/api/arceos_posix_api/src/imp/io.rs index 9ffba42d6e..2147a4ff3d 100644 --- a/os/arceos/api/arceos_posix_api/src/imp/io.rs +++ b/os/arceos/api/arceos_posix_api/src/imp/io.rs @@ -6,7 +6,7 @@ use ax_io::prelude::*; use crate::ctypes; #[cfg(feature = "fd")] -use crate::imp::fd_ops::{FileLike, get_file_like}; +use crate::imp::fd_ops::get_file_like; /// Read data from the file indicated by `fd`. /// @@ -38,9 +38,6 @@ fn write_impl(fd: c_int, buf: *const c_void, count: usize) -> LinuxResult c_int { /// Exit current task #[track_caller] pub fn sys_exit(exit_code: c_int) -> ! { - ax_hal::console::write_text_bytes(b"[ax-posix-api] sys_exit\n"); debug!("sys_exit <= {exit_code}"); #[cfg(feature = "multitask")] ax_task::exit(exit_code); diff --git a/os/arceos/modules/axruntime/src/lang_items.rs b/os/arceos/modules/axruntime/src/lang_items.rs index 782c114b43..b2b28c666e 100644 --- a/os/arceos/modules/axruntime/src/lang_items.rs +++ b/os/arceos/modules/axruntime/src/lang_items.rs @@ -35,9 +35,7 @@ fn panic_primary(info: &PanicInfo) -> ! { } fn panic_message(info: &PanicInfo) { - ax_hal::console::write_text_bytes(b"[axruntime panic] entering panic_message\n"); ax_println!("{}", info); - ax_hal::console::write_text_bytes(b"[axruntime panic] leaving panic_message\n"); } fn panic_backtrace() { @@ -51,7 +49,6 @@ fn should_print_panic_backtrace() -> bool { } fn panic_shutdown() -> ! { - ax_hal::console::write_text_bytes(b"[axruntime panic] system_off from panic_shutdown\n"); ax_hal::power::system_off() } diff --git a/os/arceos/modules/axtask/src/run_queue.rs b/os/arceos/modules/axtask/src/run_queue.rs index b62c61ce75..acb80c1db0 100644 --- a/os/arceos/modules/axtask/src/run_queue.rs +++ b/os/arceos/modules/axtask/src/run_queue.rs @@ -615,11 +615,9 @@ impl CurrentRunQueueRef<'_, G> { pub fn exit_current(&mut self, exit_code: i32) -> ! { let curr = &self.current_task; debug!("task exit: {}, exit_code={}", curr.id_name(), exit_code); - ax_hal::console::write_text_bytes(b"[axtask] exit_current\n"); assert!(curr.is_running(), "task is not running: {:?}", curr.state()); assert!(!curr.is_idle()); if curr.is_init() { - ax_hal::console::write_text_bytes(b"[axtask] init task exiting, calling system_off\n"); // Safety: it is called from `current_run_queue::().exit_current(exit_code)`, // which disabled IRQs and preemption. unsafe { diff --git a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml index 7652173e61..bea1d17383 100644 --- a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml +++ b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml @@ -30,7 +30,7 @@ boot_protocol = "uefi" uefi_firmware_path = "/tmp/ostool/ovmf/loongarch64/code.fd" bios_load_addr = 0x1c00_0000 # Kernel command line. Rootfs mode intentionally uses virtio-blk /dev/vda. -cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw console=ttyS0,115200 quiet loglevel=3 nokaslr swiotlb=1024 pci=nomsi initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" +cmdline = "root=/dev/vda rootfstype=ext4 rootwait rw console=ttyS0,115200 earlycon=uart8250,mmio,0x1fe001e0,115200 nokaslr loglevel=8 ignore_loglevel swiotlb=1024 pci=nomsi initcall_blacklist=raid6_select_algo,ixgbe_init_module,i8042_init,inet6_init" # Memory regions with format (`base_paddr`, `size`, `flags`, `map_type`). # For `map_type`, 0 means `MAP_ALLOC`, 1 means `MAP_IDENTICAL`, 2 means `MAP_RESERVED`. diff --git a/platforms/axplat-dyn/src/power.rs b/platforms/axplat-dyn/src/power.rs index 1c17de08e5..fb16c8b01a 100644 --- a/platforms/axplat-dyn/src/power.rs +++ b/platforms/axplat-dyn/src/power.rs @@ -16,7 +16,6 @@ impl PowerIf for PowerImpl { /// Shutdown the whole system. fn system_off() -> ! { - ax_plat::console::write_text_bytes(b"[axplat-dyn] system_off\n"); somehal::power::shutdown() } diff --git a/platforms/somehal/src/arch/loongarch64/eiointc.rs b/platforms/somehal/src/arch/loongarch64/eiointc.rs index f81935c65d..37a3301173 100644 --- a/platforms/somehal/src/arch/loongarch64/eiointc.rs +++ b/platforms/somehal/src/arch/loongarch64/eiointc.rs @@ -58,14 +58,6 @@ pub fn complete_irq(irq: usize) { complete_irq_for(irq, EIOINTC_VECTOR_COUNT); } -pub fn debug_pending_summary() -> [u64; 4] { - let mut pending = [0; 4]; - for (reg, slot) in pending.iter_mut().enumerate() { - *slot = iocsr_read_d(EIOINTC_REG_ISR + reg * 8); - } - pending -} - fn probe_eiointc_fdt(probe: ProbeFdt<'_>) -> Result<(), OnProbeError> { register_eiointc(probe.into_platform_device()) } diff --git a/platforms/somehal/src/arch/loongarch64/mod.rs b/platforms/somehal/src/arch/loongarch64/mod.rs index 312109fa76..f6940c6104 100644 --- a/platforms/somehal/src/arch/loongarch64/mod.rs +++ b/platforms/somehal/src/arch/loongarch64/mod.rs @@ -8,14 +8,6 @@ mod pch_pic; pub struct Plat; -pub fn debug_external_irq_snapshot(inputs: &[usize]) { - info!( - "LoongArch EIOINTC pending summary: {:?}", - eiointc::debug_pending_summary() - ); - pch_pic::debug_summary(inputs); -} - const IOCSR_IPI_SEND_CPU_SHIFT: u32 = 16; const IOCSR_IPI_SEND_BLOCKING: u32 = 1 << 31; diff --git a/platforms/somehal/src/arch/loongarch64/pch_pic.rs b/platforms/somehal/src/arch/loongarch64/pch_pic.rs index 14e11d95e2..012f3b9c61 100644 --- a/platforms/somehal/src/arch/loongarch64/pch_pic.rs +++ b/platforms/somehal/src/arch/loongarch64/pch_pic.rs @@ -15,10 +15,7 @@ const DEFAULT_PCH_PIC_SIZE: usize = 0x400; const PCH_PIC_ID: usize = 0x00; const PCH_PIC_MASK: usize = 0x20; -const PCH_PIC_HTMSI_EN: usize = 0x40; const PCH_PIC_EDGE: usize = 0x60; -const PCH_PIC_CLR: usize = 0x80; -const PCH_INT_ROUTE: usize = 0x100; const PCH_PIC_POL: usize = 0x3e0; const PCH_INT_HTVEC: usize = 0x200; @@ -52,45 +49,6 @@ pub fn set_irq_enable(irq: usize, enable: bool) { }); } -pub fn debug_summary(inputs: &[usize]) { - with_pch_pic("debugging PCH-PIC state", |pic| { - let mask0 = pic.read_w(PCH_PIC_MASK); - let mask1 = pic.read_w(PCH_PIC_MASK + 4); - let htmsi0 = pic.read_w(PCH_PIC_HTMSI_EN); - let htmsi1 = pic.read_w(PCH_PIC_HTMSI_EN + 4); - let edge0 = pic.read_w(PCH_PIC_EDGE); - let edge1 = pic.read_w(PCH_PIC_EDGE + 4); - let pol0 = pic.read_w(PCH_PIC_POL); - let pol1 = pic.read_w(PCH_PIC_POL + 4); - let clr0 = pic.read_w(PCH_PIC_CLR); - let clr1 = pic.read_w(PCH_PIC_CLR + 4); - debug!( - "LoongArch PCH-PIC summary: base_vector={}, vector_count={}, mask=[{:#x},{:#x}], \ - htmsi=[{:#x},{:#x}], edge=[{:#x},{:#x}], pol=[{:#x},{:#x}], clr=[{:#x},{:#x}]", - pic.base_vector, - pic.vector_count, - mask0, - mask1, - htmsi0, - htmsi1, - edge0, - edge1, - pol0, - pol1, - clr0, - clr1 - ); - for &input in inputs { - if input >= pic.vector_count { - continue; - } - let route = pic.read_b(PCH_INT_ROUTE + input); - let htvec = pic.read_b(PCH_INT_HTVEC + input); - debug!("LoongArch PCH-PIC input {input}: route={route:#x}, htvec={htvec:#x}"); - } - }); -} - fn probe_pch_pic_fdt(probe: ProbeFdt<'_>) -> Result<(), OnProbeError> { let (info, dev) = probe.into_parts(); let reg = info @@ -292,10 +250,6 @@ impl PchPic { self.mmio.read(offset) } - fn read_b(&self, offset: usize) -> u8 { - self.mmio.read(offset) - } - fn write_w(&self, offset: usize, value: u32) { self.mmio.write(offset, value); } diff --git a/test-suit/arceos/c/qemu-loongarch64.toml b/test-suit/arceos/c/qemu-loongarch64.toml index d1f64409a6..6c17a43491 100644 --- a/test-suit/arceos/c/qemu-loongarch64.toml +++ b/test-suit/arceos/c/qemu-loongarch64.toml @@ -1,6 +1,4 @@ args = [ - "-m", - "2G", "-smp", "4", "-device", diff --git a/test-suit/arceos/rust/qemu-loongarch64.toml b/test-suit/arceos/rust/qemu-loongarch64.toml index 710ff27427..6a7d02ae5b 100644 --- a/test-suit/arceos/rust/qemu-loongarch64.toml +++ b/test-suit/arceos/rust/qemu-loongarch64.toml @@ -1,6 +1,6 @@ args = [ "-m", - "2G", + "256M", "-smp", "4", "-device", diff --git a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml index 309c40be41..f437c9e98f 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml @@ -5,7 +5,7 @@ args = [ "la464", "-nographic", "-m", - "2G", + "512M", "-device", "nvme,serial=deadbeef,drive=nvm", "-drive", @@ -22,7 +22,7 @@ args = [ "virtio-tablet-pci", ] uefi = false -to_bin = false +to_bin = true shell_prefix = "root@starry:" test_commands = [ ''' diff --git a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml index 1d35f03160..8017c7c2c4 100644 --- a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml @@ -5,7 +5,7 @@ args = [ "la464", "-nographic", "-m", - "2G", + "512M", "-smp", "4", "-device", @@ -18,7 +18,7 @@ args = [ "user,id=net0", ] uefi = false -to_bin = false +to_bin = true shell_prefix = "root@starry:" test_commands = [ ''' diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index 6a5eecabf8..d72b28d573 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -29,7 +29,7 @@ use axdevice::{ use axdevice_base::AccessWidth; #[cfg(target_arch = "aarch64")] use axdevice_base::DeviceRegistry as _; -use axvcpu::{AxVCpu, AxVCpuExitReason, VCpuState}; +use axvcpu::{AxArchVCpu, AxVCpu, AxVCpuExitReason, VCpuState}; #[cfg(target_arch = "x86_64")] use axvm_types::EmulatedDeviceType; use axvm_types::{GuestPhysAddr, HostPhysAddr, HostVirtAddr}; @@ -814,7 +814,36 @@ impl AxVM { )?; } AxVCpuExitReason::NestedPageFault { addr, access_flags } => { - if !self.handle_nested_page_fault(addr, access_flags) { + if self.get_devices().find_mmio_dev(addr).is_some() { + if let Some(mmio_exit) = + vcpu.get_arch_vcpu().decode_mmio_fault(addr, access_flags) + { + match mmio_exit { + AxVCpuExitReason::MmioRead { + addr, + width, + reg, + reg_width, + signed_ext, + } => { + let raw = self.get_devices().handle_mmio_read(addr, width)?; + let masked = raw & width_mask(width); + let val = if signed_ext { + sign_extend_value(masked, width) + } else { + masked & width_mask(reg_width) + }; + vcpu.set_gpr(reg, val); + } + AxVCpuExitReason::MmioWrite { addr, width, data } => { + self.handle_mmio_write(addr, width, data as usize)?; + } + exit_reason => break Ok(exit_reason), + } + } else { + break Ok(AxVCpuExitReason::NestedPageFault { addr, access_flags }); + } + } else if !self.handle_nested_page_fault(addr, access_flags) { break Ok(AxVCpuExitReason::NestedPageFault { addr, access_flags }); } } diff --git a/virtualization/loongarch_vcpu/src/vcpu.rs b/virtualization/loongarch_vcpu/src/vcpu.rs index 2e94d49f8f..85e543eed4 100644 --- a/virtualization/loongarch_vcpu/src/vcpu.rs +++ b/virtualization/loongarch_vcpu/src/vcpu.rs @@ -15,12 +15,12 @@ use crate::{ context_frame::LoongArchContextFrame, host, registers::{ - CSR_ASID, CSR_CRMD, CSR_ECFG, CSR_GCTL, CSR_GINTC, CSR_GSTAT, CSR_GTLBC, CSR_KSAVE_KSP, - CSR_PGDH, CSR_PGDL, CSR_PRMD, CSR_PWCH, CSR_PWCL, CSR_STLBPS, CSR_TLBRENTRY, INT_HWI0, - INT_HWI7, INT_IPI, INT_TIMER, csr_read, csr_write, gcfg_set_gpm_num, gcfg_set_matc, - gcfg_set_toci, gcfg_set_toe, gcfg_set_tohu, gcfg_set_top, gcfg_set_topi, gcfg_set_toti, - get_ecfg_vs, gintc_set_hwi_passthrough, gstat_set_gid, gstat_set_pgm, gtlbc_set_tgid, - gtlbc_set_use_tgid, set_ecfg_line_enabled, set_ecfg_vs, + CSR_ASID, CSR_CRMD, CSR_ECFG, CSR_KSAVE_KSP, CSR_PGDH, CSR_PGDL, CSR_PRMD, CSR_PWCH, + CSR_PWCL, CSR_STLBPS, CSR_TLBRENTRY, INT_HWI0, INT_HWI7, INT_IPI, INT_TIMER, csr_read, + csr_write, gcfg_set_gpm_num, gcfg_set_matc, gcfg_set_toci, gcfg_set_toe, gcfg_set_tohu, + gcfg_set_top, gcfg_set_topi, gcfg_set_toti, get_ecfg_vs, gintc_set_hwi_passthrough, + gstat_set_gid, gstat_set_pgm, gtlbc_set_tgid, gtlbc_set_use_tgid, set_ecfg_line_enabled, + set_ecfg_vs, }, }; @@ -134,29 +134,6 @@ pub struct LoongArchVCpuSetupConfig { pub firmware_boot: bool, } -#[cfg(target_arch = "loongarch64")] -#[derive(Clone, Copy, Debug)] -pub struct LoongArchVCpuDebugState { - pub sepc: usize, - pub gcsr_crmd: usize, - pub gcsr_ectl: usize, - pub gcsr_estat: usize, - pub gcsr_era: usize, - pub gcsr_badv: usize, - pub gcsr_eentry: usize, - pub gcsr_tcfg: usize, - pub gcsr_tval: usize, - pub gcsr_tlbrentry: usize, - pub gcsr_tlbrbadv: usize, - pub gcsr_tlbrera: usize, - pub host_estat: usize, - pub host_era: usize, - pub host_badv: usize, - pub host_tlbrbadv: usize, - pub host_tlbrera: usize, - pub last_badi: usize, -} - impl AxArchVCpu for LoongArchVCpu { type CreateConfig = LoongArchVCpuCreateConfig; type SetupConfig = LoongArchVCpuSetupConfig; @@ -238,77 +215,6 @@ impl AxArchVCpu for LoongArchVCpu { self.ctx.gcsr_ectl ); } - if !self.entry_logged - || self.ctx.gcsr_estat & self.ctx.gcsr_ectl & (1usize << INT_HWI0) != 0 - { - let gintc = unsafe { csr_read::() }; - log::debug!( - "LoongArch guest first entry: VM[{}] VCpu[{}] sepc={:#x}, gera={:#x}, \ - a0={:#x}, a1={:#x}, a2={:#x}, sp={:#x}, stage2_root={:#x}, estat={:#x}, \ - ecfg={:#x}, gintc={:#x}", - self.vm_id, - self.vcpu_id, - self.ctx.sepc, - self.ctx.gcsr_era, - self.ctx.get_a0(), - self.ctx.get_a1(), - self.ctx.get_a2(), - self.ctx.x[3], - self.stage2_root.as_usize(), - self.ctx.gcsr_estat, - self.ctx.gcsr_ectl, - gintc, - ); - let ( - gstat, - gcfg, - gtlbc, - gintc, - host_crmd, - host_ecfg, - host_pgdl, - host_pgdh, - host_pwcl, - host_pwch, - host_stlbps, - host_tlbrentry, - ) = unsafe { - ( - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - csr_read::(), - ) - }; - log::debug!( - "LoongArch guest entry CSR: gstat={:#x}, gcfg={:#x}, gtlbc={:#x}, \ - gintc={:#x}, host_crmd={:#x}, host_ecfg={:#x}, host_pgdl={:#x}, \ - host_pgdh={:#x}, host_pwcl={:#x}, host_pwch={:#x}, host_stlbps={:#x}, \ - host_tlbrentry={:#x}", - gstat, - gcfg, - gtlbc, - gintc, - host_crmd, - host_ecfg, - host_pgdl, - host_pgdh, - host_pwcl, - host_pwch, - host_stlbps, - host_tlbrentry, - ); - self.entry_logged = true; - } - log::debug!("LoongArch guest entry context:\n{}", self.ctx); let exit_reason = unsafe { save_host_sp(); self.run_guest() @@ -339,12 +245,7 @@ impl AxArchVCpu for LoongArchVCpu { let _ = self.cpu_id; #[cfg(target_arch = "loongarch64")] unsafe { - log::debug!( - "LoongArch VCpu[{}] bind: save host translation", - self.vcpu_id - ); self.save_host_translation_state(); - log::debug!("LoongArch VCpu[{}] bind: done", self.vcpu_id); } Ok(()) } @@ -425,30 +326,6 @@ impl AxArchVCpu for LoongArchVCpu { } impl LoongArchVCpu { - #[cfg(target_arch = "loongarch64")] - pub fn debug_state(&self) -> LoongArchVCpuDebugState { - LoongArchVCpuDebugState { - sepc: self.ctx.sepc, - gcsr_crmd: self.ctx.gcsr_crmd, - gcsr_ectl: self.ctx.gcsr_ectl, - gcsr_estat: self.ctx.gcsr_estat, - gcsr_era: self.ctx.gcsr_era, - gcsr_badv: self.ctx.gcsr_badv, - gcsr_eentry: self.ctx.gcsr_eentry, - gcsr_tcfg: self.ctx.gcsr_tcfg, - gcsr_tval: self.ctx.gcsr_tval, - gcsr_tlbrentry: self.ctx.gcsr_tlbrentry, - gcsr_tlbrbadv: self.ctx.gcsr_tlbrbadv, - gcsr_tlbrera: self.ctx.gcsr_tlbrera, - host_estat: self.ctx.host_estat, - host_era: self.ctx.host_era, - host_badv: self.ctx.host_badv, - host_tlbrbadv: self.ctx.host_tlbrbadv, - host_tlbrera: self.ctx.host_tlbrera, - last_badi: self.last_badi, - } - } - #[cfg(target_arch = "loongarch64")] pub fn inject_external_interrupt(&mut self, vector: usize, physical_irq: usize) -> AxResult { if let Some(hwi) = From 243512299ff074a48a58ff7dc7c7b4c7e2f6a5f7 Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 15 Jun 2026 13:36:44 +0800 Subject: [PATCH 24/50] chore(config): omit default dynamic platform flag --- os/axvisor/configs/board/qemu-loongarch64.toml | 1 - test-suit/arceos/c/qemu-loongarch64.toml | 2 ++ test-suit/arceos/rust/qemu-loongarch64.toml | 2 +- .../normal/qemu/build-loongarch64-unknown-none-softfloat.toml | 1 - 4 files changed, 3 insertions(+), 3 deletions(-) diff --git a/os/axvisor/configs/board/qemu-loongarch64.toml b/os/axvisor/configs/board/qemu-loongarch64.toml index cccff7f8cc..1b17cc1389 100644 --- a/os/axvisor/configs/board/qemu-loongarch64.toml +++ b/os/axvisor/configs/board/qemu-loongarch64.toml @@ -5,6 +5,5 @@ features = [ ] log = "Info" max_cpu_num = 1 -plat_dyn = true target = "loongarch64-unknown-none-softfloat" vm_configs = [] diff --git a/test-suit/arceos/c/qemu-loongarch64.toml b/test-suit/arceos/c/qemu-loongarch64.toml index 6c17a43491..d1f64409a6 100644 --- a/test-suit/arceos/c/qemu-loongarch64.toml +++ b/test-suit/arceos/c/qemu-loongarch64.toml @@ -1,4 +1,6 @@ args = [ + "-m", + "2G", "-smp", "4", "-device", diff --git a/test-suit/arceos/rust/qemu-loongarch64.toml b/test-suit/arceos/rust/qemu-loongarch64.toml index 6a7d02ae5b..710ff27427 100644 --- a/test-suit/arceos/rust/qemu-loongarch64.toml +++ b/test-suit/arceos/rust/qemu-loongarch64.toml @@ -1,6 +1,6 @@ args = [ "-m", - "256M", + "2G", "-smp", "4", "-device", diff --git a/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml b/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml index cccff7f8cc..1b17cc1389 100644 --- a/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml +++ b/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml @@ -5,6 +5,5 @@ features = [ ] log = "Info" max_cpu_num = 1 -plat_dyn = true target = "loongarch64-unknown-none-softfloat" vm_configs = [] From 4907242df5eba43ddd966960da88c84c97ed5db5 Mon Sep 17 00:00:00 2001 From: szy Date: Tue, 16 Jun 2026 14:26:06 +0800 Subject: [PATCH 25/50] fix(starryos): restore LoongArch qemu memory size --- test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml | 2 +- test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml index f437c9e98f..59851ea694 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml @@ -5,7 +5,7 @@ args = [ "la464", "-nographic", "-m", - "512M", + "2G", "-device", "nvme,serial=deadbeef,drive=nvm", "-drive", diff --git a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml index 8017c7c2c4..6d8635bf07 100644 --- a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml @@ -5,7 +5,7 @@ args = [ "la464", "-nographic", "-m", - "512M", + "2G", "-smp", "4", "-device", From 5b187181fe9e4e804a8262696c1af11363e0888d Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 18 Jun 2026 13:14:45 +0800 Subject: [PATCH 26/50] use dyn addr --- components/someboot/src/acpi/earlycon.rs | 12 +- .../someboot/src/arch/loongarch64/console.rs | 37 +--- drivers/rdrive/src/probe/acpi.rs | 83 ++++++++ .../qemu/loongarch64/linux-rootfs-smp1.toml | 9 +- os/axvisor/src/fdt/mod.rs | 196 +++++++++++++++++- scripts/axbuild/src/build/std_build.rs | 57 +++++ .../axbuild/src/build/tests/target_specs.rs | 26 +++ 7 files changed, 372 insertions(+), 48 deletions(-) diff --git a/components/someboot/src/acpi/earlycon.rs b/components/someboot/src/acpi/earlycon.rs index fffa22af2d..ea5a096654 100644 --- a/components/someboot/src/acpi/earlycon.rs +++ b/components/someboot/src/acpi/earlycon.rs @@ -8,17 +8,21 @@ use crate::{ mem::_fixmap_io, }; -pub(crate) fn acpi_setup_earlycon() -> Result<(), AcpiError> { +pub(crate) fn acpi_setup_earlycon() -> Result { + setup_earlycon_from_spcr() +} + +pub(crate) fn setup_earlycon_from_spcr() -> Result { let tb = crate::acpi::tables()?; for spsr in tb.find_tables::() { if deal_with_spsr(&spsr).is_some() { println!("Early console setup complete."); - break; + return Ok(true); } } - Ok(()) + Ok(false) } fn deal_with_spsr(spsr: &PhysicalMapping) -> Option<()> { @@ -42,6 +46,8 @@ fn deal_with_spsr(spsr: &PhysicalMapping) -> Option<()> { let (vaddr, is_mmio) = match spsr.interface_type() { acpi::sdt::spcr::SpcrInterfaceType::Full16550 + | acpi::sdt::spcr::SpcrInterfaceType::Full16450 + | acpi::sdt::spcr::SpcrInterfaceType::Nvidia16550 | acpi::sdt::spcr::SpcrInterfaceType::Generic16550 => match base_address.address_space { AddressSpace::SystemIo => { #[cfg(target_arch = "x86_64")] diff --git a/components/someboot/src/arch/loongarch64/console.rs b/components/someboot/src/arch/loongarch64/console.rs index 97e077a9b4..a43237d26e 100644 --- a/components/someboot/src/arch/loongarch64/console.rs +++ b/components/someboot/src/arch/loongarch64/console.rs @@ -1,38 +1,3 @@ pub struct Console; -const QEMU_VIRT_UART_PADDR: usize = 0x1fe0_01e0; -const QEMU_VIRT_UART_CLOCK_HZ: u32 = 100_000_000; -const QEMU_VIRT_UART_REG_WIDTH: usize = 1; - -impl crate::console::ArchConsoleOps for Console { - fn init() -> bool { - use core::ptr::NonNull; - - use some_serial::InterfaceRaw; - - let Some(base) = NonNull::new(crate::mem::_fixmap_io(QEMU_VIRT_UART_PADDR)) else { - return false; - }; - let mut uart = some_serial::ns16550::Ns16550::new_mmio( - base, - QEMU_VIRT_UART_CLOCK_HZ, - QEMU_VIRT_UART_REG_WIDTH, - ); - uart.open(); - - let Some(tx) = uart.take_tx() else { - return false; - }; - let Some(rx) = uart.take_rx() else { - return false; - }; - - crate::console::set_earlycon_sender(tx); - crate::console::set_earlycon_receiver(rx); - unsafe { - crate::console::DEBUG_BASE = QEMU_VIRT_UART_PADDR; - crate::console::DEBUG_IS_MMIO = true; - } - true - } -} +impl crate::console::ArchConsoleOps for Console {} diff --git a/drivers/rdrive/src/probe/acpi.rs b/drivers/rdrive/src/probe/acpi.rs index fa0aae4d6a..777a8b4bf1 100644 --- a/drivers/rdrive/src/probe/acpi.rs +++ b/drivers/rdrive/src/probe/acpi.rs @@ -739,6 +739,16 @@ pub struct AcpiResourceRange { pub size: u64, } +#[derive(Debug, Clone, PartialEq, Eq)] +pub struct AcpiResourceDevice { + pub path: String, + pub hid: Option, + pub cids: Vec, + pub memory_ranges: Vec, + pub io_ranges: Vec, + pub irq_routes: Vec, +} + #[derive(Debug, Clone)] struct AcpiDeviceInfo { path: String, @@ -832,6 +842,19 @@ impl AcpiInfo<'_> { } } +impl From for AcpiResourceDevice { + fn from(value: AcpiDeviceInfo) -> Self { + Self { + path: value.path, + hid: value.hid, + cids: value.cids, + memory_ranges: value.memory_ranges, + io_ranges: value.io_ranges, + irq_routes: value.irq_routes, + } + } +} + pub struct ProbeAcpi<'a> { info: AcpiInfo<'a>, platform: PlatformDevice, @@ -1194,6 +1217,29 @@ impl System { }) } + pub fn resource_devices(&self) -> Result, ProbeError> { + self.device_infos().map(|devices| { + devices + .into_iter() + .map(AcpiResourceDevice::from) + .collect::>() + }) + } + + pub fn serial_console_memory_range(&self) -> Option { + let tables = self.handler.root.tables().ok()?; + let spcr = tables.find_table::()?; + let address = spcr.base_address()?.ok()?; + if address.address_space != acpi::address::AddressSpace::SystemMemory { + return None; + } + + Some(AcpiResourceRange { + base: address.address, + size: spcr_uart_register_size(address.access_size), + }) + } + pub fn pci_irq_for_endpoint( &self, info: PciInfo, @@ -1336,6 +1382,32 @@ impl System { Ok(devices) } + fn device_infos(&self) -> Result, ProbeError> { + let mut devices = Vec::new(); + let mut namespace = self.interpreter.namespace.lock().clone(); + namespace + .traverse(|path, level| { + if level.kind != NamespaceLevelKind::Device { + return Ok(true); + } + let Some((hid, cids)) = acpi_device_ids(&self.interpreter, path)? else { + return Ok(true); + }; + let resources = read_device_resources(&self.interpreter, path, &self.routing)?; + devices.push(AcpiDeviceInfo { + path: path.as_string(), + hid: Some(hid), + cids, + memory_ranges: resources.memory_ranges, + io_ranges: resources.io_ranges, + irq_routes: resources.irq_routes, + }); + Ok(true) + }) + .map_err(|err| ProbeError::OnProbe(OnProbeError::other(format!("{err:?}"))))?; + Ok(devices) + } + fn probe_register( &self, register: &DriverRegister, @@ -1556,6 +1628,17 @@ fn read_loongarch_bio_pic_entry( }); } +fn spcr_uart_register_size(access_size: u8) -> u64 { + let access_bytes = match access_size { + 1 => 1, + 2 => 2, + 3 => 4, + 4 => 8, + _ => 1, + }; + access_bytes * 8 +} + #[derive(Default)] struct AcpiDeviceResources { memory_ranges: Vec, diff --git a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml index bea1d17383..c2c86ed236 100644 --- a/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml +++ b/os/axvisor/configs/vms/qemu/loongarch64/linux-rootfs-smp1.toml @@ -49,19 +49,12 @@ interrupt_mode = "passthrough" # Pass-through devices. passthrough_devices = [ + ["/"], ] # Passthrough addresses. # Base-GPA Length. passthrough_addresses = [ - [0x100d_0100, 0x100], - [0x100e_0000, 0x1_0000], - [0x1d00_0000, 0x0100_0000], - [0x1fe0_01e0, 0x100], - [0x1800_4000, 0xc000], - [0x2000_0000, 0x0800_0000], - [0x2ff0_0000, 0x8], - [0x4000_0000, 0x4000_0000], ] # Devices that are not desired to be passed through to the guest diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index f973a05170..c7debbbe88 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -23,11 +23,13 @@ mod parser; mod print; pub(crate) mod vm_fdt; -use alloc::{collections::BTreeMap, format, vec::Vec}; +use alloc::{collections::BTreeMap, format, string::String, vec::Vec}; use ax_errno::{AxResult, ax_err_type}; use ax_kspin::SpinNoIrq as Mutex; use ax_lazyinit::LazyInit; +#[cfg(target_arch = "loongarch64")] +use axvm::config::PassThroughDeviceConfig; // pub use print::print_fdt; #[cfg(any( target_arch = "aarch64", @@ -108,12 +110,204 @@ fn handle_uefi_fdt_operations( vm_config.id(), LOONGARCH_UEFI_FDT_BASE ); + expand_loongarch_uefi_root_passthrough(vm_config, vm_create_config)?; vm_config.set_dtb_load_gpa(LOONGARCH_UEFI_FDT_BASE.into()); vm_create_config.kernel.dtb_load_addr = Some(LOONGARCH_UEFI_FDT_BASE); store_loongarch_guest_irq_routes(vm_config.id(), loongarch_qemu_uefi_irq_routes()); Ok(()) } +#[cfg(target_arch = "loongarch64")] +fn expand_loongarch_uefi_root_passthrough( + vm_config: &mut AxVMConfig, + vm_create_config: &AxVMCrateConfig, +) -> AxResult { + let has_root_passthrough = vm_config + .pass_through_devices() + .iter() + .any(|device| device.name == "/" && device.length == 0); + if !has_root_passthrough { + return Ok(()); + } + + let ranges = ax_driver::probe::acpi::with_acpi(loongarch_acpi_passthrough_ranges) + .ok_or_else(|| ax_err_type!(NotFound, "LoongArch UEFI root passthrough requires ACPI"))??; + + vm_config.clear_pass_through_devices(); + let mut added = 0; + for range in ranges + .into_iter() + .filter(|range| !loongarch_acpi_passthrough_range_is_occupied(range, vm_create_config)) + { + vm_config.add_pass_through_device(PassThroughDeviceConfig { + name: range.name, + base_gpa: range.base, + base_hpa: range.base, + length: range.size, + irq_id: 0, + }); + added += 1; + } + + if added == 0 { + return Err(ax_err_type!( + NotFound, + "LoongArch UEFI root passthrough resources are all occupied by VM config" + )); + } + + Ok(()) +} + +#[cfg(target_arch = "loongarch64")] +fn loongarch_acpi_passthrough_range_is_occupied( + range: &LoongArchAcpiPassthroughRange, + vm_create_config: &AxVMCrateConfig, +) -> bool { + vm_create_config + .kernel + .memory_regions + .iter() + .any(|memory| loongarch_ranges_overlap(range.base, range.size, memory.gpa, memory.size)) + || vm_create_config.devices.emu_devices.iter().any(|device| { + loongarch_ranges_overlap(range.base, range.size, device.base_gpa, device.length) + }) +} + +#[cfg(target_arch = "loongarch64")] +fn loongarch_ranges_overlap( + base: usize, + size: usize, + other_base: usize, + other_size: usize, +) -> bool { + const PAGE_SIZE: usize = 4096; + + if size == 0 || other_size == 0 { + return false; + } + + let start = base & !(PAGE_SIZE - 1); + let end = base.saturating_add(size).div_ceil(PAGE_SIZE) * PAGE_SIZE; + let other_start = other_base & !(PAGE_SIZE - 1); + let other_end = other_base.saturating_add(other_size).div_ceil(PAGE_SIZE) * PAGE_SIZE; + + start < other_end && other_start < end +} + +#[cfg(target_arch = "loongarch64")] +#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord)] +struct LoongArchAcpiPassthroughRange { + name: String, + base: usize, + size: usize, +} + +#[cfg(target_arch = "loongarch64")] +fn loongarch_acpi_passthrough_ranges( + acpi: &ax_driver::probe::acpi::System, +) -> AxResult> { + let mut ranges = Vec::new(); + + for device in acpi.resource_devices().map_err(|err| { + ax_err_type!( + InvalidData, + format!("failed to collect ACPI resource devices: {err:?}") + ) + })? { + for (index, range) in device.memory_ranges.iter().enumerate() { + add_loongarch_acpi_passthrough_range( + &mut ranges, + format!("{}:mem{index}", device.path), + range.base, + range.size, + )?; + } + } + + if let Some(range) = acpi.serial_console_memory_range() { + add_loongarch_acpi_passthrough_range( + &mut ranges, + "acpi-spcr-uart".into(), + range.base, + range.size, + )?; + } + + for (index, region) in acpi.pci_ecam_regions().iter().enumerate() { + add_loongarch_acpi_passthrough_range( + &mut ranges, + format!("acpi-mcfg{index}"), + region.base_address, + region.size() as u64, + )?; + } + + for (index, pch_pic) in acpi.routing().pch_pics().iter().enumerate() { + add_loongarch_acpi_passthrough_range( + &mut ranges, + format!("acpi-pch-pic{index}"), + pch_pic.address, + u64::from(pch_pic.mmio_size), + )?; + } + + for (index, region) in ax_hal::mem::memory_regions() + .filter(|region| region.flags.contains(ax_hal::mem::MemRegionFlags::DEVICE)) + .enumerate() + { + add_loongarch_acpi_passthrough_range( + &mut ranges, + format!("host-mmio{index}"), + region.paddr.as_usize() as u64, + region.size as u64, + )?; + } + + ranges.sort_by_key(|range| range.base); + let mut merged = Vec::::new(); + for range in ranges { + if let Some(last) = merged.last_mut() { + let last_end = last.base.saturating_add(last.size); + let range_end = range.base.saturating_add(range.size); + if last_end >= range.base { + last.size = last_end.max(range_end) - last.base; + last.name.push('+'); + last.name.push_str(&range.name); + continue; + } + } + merged.push(range); + } + + if merged.is_empty() { + return Err(ax_err_type!( + NotFound, + "LoongArch UEFI root passthrough did not find ACPI MMIO resources" + )); + } + + Ok(merged) +} + +#[cfg(target_arch = "loongarch64")] +fn add_loongarch_acpi_passthrough_range( + ranges: &mut Vec, + name: String, + base: u64, + size: u64, +) -> AxResult { + if size == 0 { + return Ok(()); + } + let base = usize::try_from(base) + .map_err(|_| ax_err_type!(InvalidData, "ACPI passthrough base does not fit usize"))?; + let size = usize::try_from(size) + .map_err(|_| ax_err_type!(InvalidData, "ACPI passthrough size does not fit usize"))?; + ranges.push(LoongArchAcpiPassthroughRange { name, base, size }); + Ok(()) +} + #[cfg(target_arch = "loongarch64")] fn loongarch_qemu_uefi_irq_routes() -> Vec { const HOST_UART_IRQ: usize = 2; diff --git a/scripts/axbuild/src/build/std_build.rs b/scripts/axbuild/src/build/std_build.rs index 9e61fee07d..ce0ffebd82 100644 --- a/scripts/axbuild/src/build/std_build.rs +++ b/scripts/axbuild/src/build/std_build.rs @@ -55,6 +55,7 @@ pub(super) fn std_c_toolchain_env(target_name: &str, tool_prefix: &str) -> HashM format!("--target={tool_prefix}"), format!("--sysroot={sysroot}"), ]; + bindgen_args.extend(musl_toolchain_bindgen_args(&cc, &sysroot, tool_prefix)); bindgen_args.extend( std_c_target_flags(target_name) .into_iter() @@ -107,6 +108,62 @@ pub(super) fn musl_toolchain_sysroot(cc: &str) -> Option { (!sysroot.is_empty()).then(|| sysroot.to_string()) } +fn musl_toolchain_bindgen_args(cc: &str, sysroot: &str, tool_prefix: &str) -> Vec { + let Some(toolchain_root) = musl_toolchain_root(cc, sysroot) else { + return Vec::new(); + }; + + let mut args = vec![format!("--gcc-toolchain={}", toolchain_root.display())]; + + let include = Path::new(sysroot).join("include"); + if include.is_dir() { + args.push("-isystem".to_string()); + args.push(include.display().to_string()); + } + + if let Some(gcc_include) = musl_gcc_include_dir(&toolchain_root, tool_prefix) { + args.push("-isystem".to_string()); + args.push(gcc_include.display().to_string()); + } + + args +} + +fn musl_toolchain_root(cc: &str, sysroot: &str) -> Option { + let cc_path = command_path(cc)?; + let bin_dir = cc_path.parent()?; + let root = bin_dir.parent()?; + let sysroot_path = fs::canonicalize(sysroot).ok()?; + let root_path = fs::canonicalize(root).ok()?; + + sysroot_path + .starts_with(&root_path) + .then(|| root.to_path_buf()) +} + +fn command_path(command: &str) -> Option { + let path = Path::new(command); + if path.components().count() > 1 { + return path.exists().then(|| path.to_path_buf()); + } + + std::env::var_os("PATH")? + .to_string_lossy() + .split(':') + .map(Path::new) + .map(|dir| dir.join(command)) + .find(|path| path.exists()) +} + +fn musl_gcc_include_dir(toolchain_root: &Path, tool_prefix: &str) -> Option { + let gcc_dir = toolchain_root.join("lib/gcc").join(tool_prefix); + fs::read_dir(gcc_dir) + .ok()? + .filter_map(Result::ok) + .map(|entry| entry.path().join("include")) + .find(|path| path.is_dir()) +} + pub(super) fn std_target_json_path(target: &str, plat_dyn: bool) -> PathBuf { let path = Path::new(TARGET_JSON_ROOT).join(STD_TARGET_DIR); if plat_dyn { diff --git a/scripts/axbuild/src/build/tests/target_specs.rs b/scripts/axbuild/src/build/tests/target_specs.rs index ac741bbf2f..0dbf0d0407 100644 --- a/scripts/axbuild/src/build/tests/target_specs.rs +++ b/scripts/axbuild/src/build/tests/target_specs.rs @@ -42,6 +42,32 @@ fn std_c_toolchain_env_exports_loongarch_softfloat_abi_flags() { } } +#[test] +fn musl_toolchain_bindgen_args_pin_clang_to_musl_toolchain() -> anyhow::Result<()> { + let dir = tempdir()?; + let root = dir.path(); + let cc = root.join("bin/loongarch64-linux-musl-cc"); + let sysroot = root.join("loongarch64-linux-musl"); + let libc_include = sysroot.join("include"); + let gcc_include = root.join("lib/gcc/loongarch64-linux-musl/13.2.0/include"); + fs::create_dir_all(cc.parent().unwrap())?; + fs::create_dir_all(&libc_include)?; + fs::create_dir_all(&gcc_include)?; + fs::write(&cc, "")?; + + let args = musl_toolchain_bindgen_args( + cc.to_str().unwrap(), + sysroot.to_str().unwrap(), + "loongarch64-linux-musl", + ); + let joined = args.join(" "); + + assert!(joined.contains(&format!("--gcc-toolchain={}", root.display()))); + assert!(joined.contains(&libc_include.display().to_string())); + assert!(joined.contains(&gcc_include.display().to_string())); + Ok(()) +} + #[test] fn std_target_specs_keep_kernel_fields_with_std_identity() { for (std_target, plat_dyn, llvm_target, arch, pointer_width) in [ From 7fd667d2c1c88b7aa324cc240393380a091b9f01 Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 18 Jun 2026 15:11:07 +0800 Subject: [PATCH 27/50] feat(axvisor): refine LoongArch UEFI guest platform --- Cargo.lock | 1 + os/axvisor/Cargo.toml | 1 + os/axvisor/src/fdt/mod.rs | 256 +------------ os/axvisor/src/fdt/parser.rs | 4 +- .../loongarch64/firmware_fdt.rs | 337 +++++++++++++++++ .../src/guest_platform/loongarch64/mod.rs | 230 ++++++++++++ .../src/guest_platform/loongarch64/probe.rs | 352 ++++++++++++++++++ .../guest_platform/loongarch64/resources.rs | 234 ++++++++++++ os/axvisor/src/guest_platform/mod.rs | 2 + os/axvisor/src/images/mod.rs | 329 +--------------- os/axvisor/src/main.rs | 2 + os/axvisor/src/manager.rs | 2 +- virtualization/axdevice/src/fw_cfg.rs | 270 ++++++++++---- virtualization/axdevice/src/lib.rs | 5 +- virtualization/axvm/src/lib.rs | 2 +- 15 files changed, 1392 insertions(+), 635 deletions(-) create mode 100644 os/axvisor/src/guest_platform/loongarch64/firmware_fdt.rs create mode 100644 os/axvisor/src/guest_platform/loongarch64/mod.rs create mode 100644 os/axvisor/src/guest_platform/loongarch64/probe.rs create mode 100644 os/axvisor/src/guest_platform/loongarch64/resources.rs create mode 100644 os/axvisor/src/guest_platform/mod.rs diff --git a/Cargo.lock b/Cargo.lock index 2bf3488575..e980681588 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1531,6 +1531,7 @@ dependencies = [ "ax-memory-addr", "ax-std", "axbuild", + "axdevice", "axvm", "axvmconfig", "byte-unit", diff --git a/os/axvisor/Cargo.toml b/os/axvisor/Cargo.toml index bd56011b3d..8e7cdedb51 100644 --- a/os/axvisor/Cargo.toml +++ b/os/axvisor/Cargo.toml @@ -70,6 +70,7 @@ ax-hal = { workspace = true, features = ["paging", "irq", "smp", "hv", "axvisor- # ax-runtime = { version = "=0.3.0-preview.1", features = ["alloc", "irq", "paging", "smp", "multitask"] } axvm = { workspace = true, default-features = false } axvmconfig = { workspace = true, default-features = false } +axdevice = { workspace = true } # System independent crates provided by ArceOS ax-errno = { workspace = true } ax-memory-addr = { workspace = true } diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index c7debbbe88..5238d4a00d 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -23,13 +23,11 @@ mod parser; mod print; pub(crate) mod vm_fdt; -use alloc::{collections::BTreeMap, format, string::String, vec::Vec}; +use alloc::{collections::BTreeMap, format, vec::Vec}; use ax_errno::{AxResult, ax_err_type}; use ax_kspin::SpinNoIrq as Mutex; use ax_lazyinit::LazyInit; -#[cfg(target_arch = "loongarch64")] -use axvm::config::PassThroughDeviceConfig; // pub use print::print_fdt; #[cfg(any( target_arch = "aarch64", @@ -48,22 +46,12 @@ use crate::config::{get_vm_dtb_arc, vmcfg}; // DTB cache for generated device trees static GENERATED_DTB_CACHE: LazyInit>>> = LazyInit::new(); -#[cfg(target_arch = "loongarch64")] -static LOONGARCH_GUEST_IRQ_ROUTES: LazyInit>>> = - LazyInit::new(); - -#[cfg(target_arch = "loongarch64")] -#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] -pub struct LoongArchGuestIrqRoute { - pub physical_irq: usize, - pub guest_vector: usize, -} /// Initialize the DTB cache pub fn init_dtb_cache() { GENERATED_DTB_CACHE.init_once(Mutex::new(BTreeMap::new())); #[cfg(target_arch = "loongarch64")] - LOONGARCH_GUEST_IRQ_ROUTES.init_once(Mutex::new(BTreeMap::new())); + crate::guest_platform::loongarch64::init(); } /// Get reference to the DTB cache @@ -80,250 +68,12 @@ pub fn crate_guest_fdt_with_cache(dtb_data: Vec, crate_config: &AxVMCrateCon cache_lock.insert(crate_config.base.id, dtb_data); } -#[cfg(target_arch = "loongarch64")] -pub fn store_loongarch_guest_irq_routes(vm_id: usize, routes: Vec) { - let mut cache_lock = LOONGARCH_GUEST_IRQ_ROUTES - .get_or_init(|| Mutex::new(BTreeMap::new())) - .lock(); - cache_lock.insert(vm_id, routes); -} - -#[cfg(target_arch = "loongarch64")] -pub fn get_loongarch_guest_irq_routes(vm_id: usize) -> Vec { - LOONGARCH_GUEST_IRQ_ROUTES - .get_or_init(|| Mutex::new(BTreeMap::new())) - .lock() - .get(&vm_id) - .cloned() - .unwrap_or_default() -} - #[cfg(target_arch = "loongarch64")] fn handle_uefi_fdt_operations( vm_config: &mut AxVMConfig, vm_create_config: &mut AxVMCrateConfig, ) -> AxResult { - const LOONGARCH_UEFI_FDT_BASE: usize = 0x0010_0000; - - info!( - "VM[{}] uses LoongArch UEFI boot protocol, keeping firmware DTB at {:#x}", - vm_config.id(), - LOONGARCH_UEFI_FDT_BASE - ); - expand_loongarch_uefi_root_passthrough(vm_config, vm_create_config)?; - vm_config.set_dtb_load_gpa(LOONGARCH_UEFI_FDT_BASE.into()); - vm_create_config.kernel.dtb_load_addr = Some(LOONGARCH_UEFI_FDT_BASE); - store_loongarch_guest_irq_routes(vm_config.id(), loongarch_qemu_uefi_irq_routes()); - Ok(()) -} - -#[cfg(target_arch = "loongarch64")] -fn expand_loongarch_uefi_root_passthrough( - vm_config: &mut AxVMConfig, - vm_create_config: &AxVMCrateConfig, -) -> AxResult { - let has_root_passthrough = vm_config - .pass_through_devices() - .iter() - .any(|device| device.name == "/" && device.length == 0); - if !has_root_passthrough { - return Ok(()); - } - - let ranges = ax_driver::probe::acpi::with_acpi(loongarch_acpi_passthrough_ranges) - .ok_or_else(|| ax_err_type!(NotFound, "LoongArch UEFI root passthrough requires ACPI"))??; - - vm_config.clear_pass_through_devices(); - let mut added = 0; - for range in ranges - .into_iter() - .filter(|range| !loongarch_acpi_passthrough_range_is_occupied(range, vm_create_config)) - { - vm_config.add_pass_through_device(PassThroughDeviceConfig { - name: range.name, - base_gpa: range.base, - base_hpa: range.base, - length: range.size, - irq_id: 0, - }); - added += 1; - } - - if added == 0 { - return Err(ax_err_type!( - NotFound, - "LoongArch UEFI root passthrough resources are all occupied by VM config" - )); - } - - Ok(()) -} - -#[cfg(target_arch = "loongarch64")] -fn loongarch_acpi_passthrough_range_is_occupied( - range: &LoongArchAcpiPassthroughRange, - vm_create_config: &AxVMCrateConfig, -) -> bool { - vm_create_config - .kernel - .memory_regions - .iter() - .any(|memory| loongarch_ranges_overlap(range.base, range.size, memory.gpa, memory.size)) - || vm_create_config.devices.emu_devices.iter().any(|device| { - loongarch_ranges_overlap(range.base, range.size, device.base_gpa, device.length) - }) -} - -#[cfg(target_arch = "loongarch64")] -fn loongarch_ranges_overlap( - base: usize, - size: usize, - other_base: usize, - other_size: usize, -) -> bool { - const PAGE_SIZE: usize = 4096; - - if size == 0 || other_size == 0 { - return false; - } - - let start = base & !(PAGE_SIZE - 1); - let end = base.saturating_add(size).div_ceil(PAGE_SIZE) * PAGE_SIZE; - let other_start = other_base & !(PAGE_SIZE - 1); - let other_end = other_base.saturating_add(other_size).div_ceil(PAGE_SIZE) * PAGE_SIZE; - - start < other_end && other_start < end -} - -#[cfg(target_arch = "loongarch64")] -#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord)] -struct LoongArchAcpiPassthroughRange { - name: String, - base: usize, - size: usize, -} - -#[cfg(target_arch = "loongarch64")] -fn loongarch_acpi_passthrough_ranges( - acpi: &ax_driver::probe::acpi::System, -) -> AxResult> { - let mut ranges = Vec::new(); - - for device in acpi.resource_devices().map_err(|err| { - ax_err_type!( - InvalidData, - format!("failed to collect ACPI resource devices: {err:?}") - ) - })? { - for (index, range) in device.memory_ranges.iter().enumerate() { - add_loongarch_acpi_passthrough_range( - &mut ranges, - format!("{}:mem{index}", device.path), - range.base, - range.size, - )?; - } - } - - if let Some(range) = acpi.serial_console_memory_range() { - add_loongarch_acpi_passthrough_range( - &mut ranges, - "acpi-spcr-uart".into(), - range.base, - range.size, - )?; - } - - for (index, region) in acpi.pci_ecam_regions().iter().enumerate() { - add_loongarch_acpi_passthrough_range( - &mut ranges, - format!("acpi-mcfg{index}"), - region.base_address, - region.size() as u64, - )?; - } - - for (index, pch_pic) in acpi.routing().pch_pics().iter().enumerate() { - add_loongarch_acpi_passthrough_range( - &mut ranges, - format!("acpi-pch-pic{index}"), - pch_pic.address, - u64::from(pch_pic.mmio_size), - )?; - } - - for (index, region) in ax_hal::mem::memory_regions() - .filter(|region| region.flags.contains(ax_hal::mem::MemRegionFlags::DEVICE)) - .enumerate() - { - add_loongarch_acpi_passthrough_range( - &mut ranges, - format!("host-mmio{index}"), - region.paddr.as_usize() as u64, - region.size as u64, - )?; - } - - ranges.sort_by_key(|range| range.base); - let mut merged = Vec::::new(); - for range in ranges { - if let Some(last) = merged.last_mut() { - let last_end = last.base.saturating_add(last.size); - let range_end = range.base.saturating_add(range.size); - if last_end >= range.base { - last.size = last_end.max(range_end) - last.base; - last.name.push('+'); - last.name.push_str(&range.name); - continue; - } - } - merged.push(range); - } - - if merged.is_empty() { - return Err(ax_err_type!( - NotFound, - "LoongArch UEFI root passthrough did not find ACPI MMIO resources" - )); - } - - Ok(merged) -} - -#[cfg(target_arch = "loongarch64")] -fn add_loongarch_acpi_passthrough_range( - ranges: &mut Vec, - name: String, - base: u64, - size: u64, -) -> AxResult { - if size == 0 { - return Ok(()); - } - let base = usize::try_from(base) - .map_err(|_| ax_err_type!(InvalidData, "ACPI passthrough base does not fit usize"))?; - let size = usize::try_from(size) - .map_err(|_| ax_err_type!(InvalidData, "ACPI passthrough size does not fit usize"))?; - ranges.push(LoongArchAcpiPassthroughRange { name, base, size }); - Ok(()) -} - -#[cfg(target_arch = "loongarch64")] -fn loongarch_qemu_uefi_irq_routes() -> Vec { - const HOST_UART_IRQ: usize = 2; - const HOST_PCI_INTX_BASE: usize = 16; - const GUEST_UART_PCH_INPUT: usize = 2; - const GUEST_PCH_INTX_BASE: usize = 16; - - let mut routes = Vec::from([LoongArchGuestIrqRoute { - physical_irq: HOST_UART_IRQ, - guest_vector: GUEST_UART_PCH_INPUT, - }]); - routes.extend((0..4).map(|idx| LoongArchGuestIrqRoute { - physical_irq: HOST_PCI_INTX_BASE + idx, - guest_vector: GUEST_PCH_INTX_BASE + idx, - })); - routes + crate::guest_platform::loongarch64::prepare_uefi_fdt_config(vm_config, vm_create_config) } #[cfg(not(target_arch = "loongarch64"))] diff --git a/os/axvisor/src/fdt/parser.rs b/os/axvisor/src/fdt/parser.rs index 7dd69be0a2..e26495e165 100644 --- a/os/axvisor/src/fdt/parser.rs +++ b/os/axvisor/src/fdt/parser.rs @@ -26,7 +26,9 @@ use fdt_parser::{Node, Status}; #[cfg(target_arch = "aarch64")] use crate::fdt::create::update_cpu_node; #[cfg(target_arch = "loongarch64")] -use crate::fdt::{LoongArchGuestIrqRoute, store_loongarch_guest_irq_routes}; +use crate::guest_platform::loongarch64::{ + LoongArchGuestIrqRoute, store_guest_irq_routes as store_loongarch_guest_irq_routes, +}; use axvm::{MappingFlags, config::AxVMConfig}; use axvmconfig::{AxVMCrateConfig, PassThroughDeviceConfig, VmMemConfig, VmMemMappingType}; diff --git a/os/axvisor/src/guest_platform/loongarch64/firmware_fdt.rs b/os/axvisor/src/guest_platform/loongarch64/firmware_fdt.rs new file mode 100644 index 0000000000..c3569348df --- /dev/null +++ b/os/axvisor/src/guest_platform/loongarch64/firmware_fdt.rs @@ -0,0 +1,337 @@ +use alloc::{format, vec}; + +use ax_errno::{AxError, AxResult, ax_err_type}; + +use super::GuestPlatform; +use crate::fdt::vm_fdt::FdtWriter; + +const PHANDLE_CPU0: u32 = 0x8000; +const PHANDLE_CPUIC: u32 = 0x8001; +const PHANDLE_EIOINTC: u32 = 0x8002; +const PHANDLE_PCH_PIC: u32 = 0x8003; +const PHANDLE_PCH_MSI: u32 = 0x8004; +const PHANDLE_GED_SYSCON: u32 = 0x8005; + +pub fn build(platform: &GuestPlatform) -> AxResult> { + let mut fdt = FdtWriter::new().map_err(fdt_err)?; + let root = fdt.begin_node("").map_err(fdt_err)?; + fdt.property_u32("#address-cells", 2).map_err(fdt_err)?; + fdt.property_u32("#size-cells", 2).map_err(fdt_err)?; + fdt.property_string("compatible", "linux,dummy-loongson3") + .map_err(fdt_err)?; + + add_chosen(&mut fdt, platform)?; + add_cpus(&mut fdt)?; + add_memory(&mut fdt, platform)?; + add_interrupt_controllers(&mut fdt, platform)?; + add_platform_bus(&mut fdt, platform)?; + add_power(&mut fdt, platform)?; + add_rtc(&mut fdt, platform)?; + add_serial(&mut fdt, platform)?; + add_flash(&mut fdt, platform)?; + add_fw_cfg(&mut fdt, platform)?; + + fdt.end_node(root).map_err(fdt_err)?; + fdt.finish().map_err(fdt_err) +} + +fn fdt_err(err: impl core::fmt::Debug) -> AxError { + ax_err_type!( + InvalidData, + format!("failed to build LoongArch UEFI firmware FDT: {err:?}") + ) +} + +fn add_platform_bus(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + let (bus_base, bus_size) = platform_bus_range(platform); + let platform_bus = fdt + .begin_node(&format!("platform-bus@{bus_base:x}")) + .map_err(fdt_err)?; + fdt.property_string_list( + "compatible", + vec!["qemu,platform".into(), "simple-bus".into()], + ) + .map_err(fdt_err)?; + fdt.property_u32("#address-cells", 1).map_err(fdt_err)?; + fdt.property_u32("#size-cells", 1).map_err(fdt_err)?; + fdt.property_array_u32("ranges", &[0, 0, bus_base as u32, bus_size as u32]) + .map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", PHANDLE_PCH_PIC) + .map_err(fdt_err)?; + fdt.end_node(platform_bus).map_err(fdt_err)?; + Ok(()) +} + +fn platform_bus_range(platform: &GuestPlatform) -> (u64, u64) { + const PAGE_SIZE: u64 = 0x1000; + + let base = platform + .firmware_devices + .ged + .mmio + .base + .min(platform.firmware_devices.rtc.mmio.base) + & !(PAGE_SIZE - 1); + let end = platform + .firmware_devices + .ged + .mmio + .base + .saturating_add(platform.firmware_devices.ged.mmio.size) + .max( + platform + .firmware_devices + .rtc + .mmio + .base + .saturating_add(platform.firmware_devices.rtc.mmio.size), + ) + .div_ceil(PAGE_SIZE) + * PAGE_SIZE; + + (base, end.saturating_sub(base).max(PAGE_SIZE)) +} + +fn add_chosen(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + let chosen = fdt.begin_node("chosen").map_err(fdt_err)?; + fdt.property_string( + "stdout-path", + &format!("/serial@{:x}", platform.serial.mmio.base), + ) + .map_err(fdt_err)?; + fdt.end_node(chosen).map_err(fdt_err)?; + Ok(()) +} + +fn add_cpus(fdt: &mut FdtWriter) -> AxResult { + let cpus = fdt.begin_node("cpus").map_err(fdt_err)?; + fdt.property_u32("#address-cells", 1).map_err(fdt_err)?; + fdt.property_u32("#size-cells", 0).map_err(fdt_err)?; + let cpu_map = fdt.begin_node("cpu-map").map_err(fdt_err)?; + let socket0 = fdt.begin_node("socket0").map_err(fdt_err)?; + let core0 = fdt.begin_node("core0").map_err(fdt_err)?; + fdt.property_u32("cpu", PHANDLE_CPU0).map_err(fdt_err)?; + fdt.end_node(core0).map_err(fdt_err)?; + fdt.end_node(socket0).map_err(fdt_err)?; + fdt.end_node(cpu_map).map_err(fdt_err)?; + let cpu = fdt.begin_node("cpu@0").map_err(fdt_err)?; + fdt.property_string("device_type", "cpu").map_err(fdt_err)?; + fdt.property_string("compatible", "loongarch,Loongson-3A5000") + .map_err(fdt_err)?; + fdt.property_u32("reg", 0).map_err(fdt_err)?; + fdt.property_phandle(PHANDLE_CPU0).map_err(fdt_err)?; + fdt.end_node(cpu).map_err(fdt_err)?; + fdt.end_node(cpus).map_err(fdt_err)?; + Ok(()) +} + +fn add_memory(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + for region in &platform.ram_regions { + let memory = fdt + .begin_node(&format!("memory@{:x}", region.base)) + .map_err(fdt_err)?; + fdt.property_string("device_type", "memory") + .map_err(fdt_err)?; + fdt.property_array_u32( + "reg", + &[ + (region.base >> 32) as u32, + region.base as u32, + (region.size >> 32) as u32, + region.size as u32, + ], + ) + .map_err(fdt_err)?; + fdt.end_node(memory).map_err(fdt_err)?; + } + Ok(()) +} + +fn add_interrupt_controllers(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + let cpuic = fdt.begin_node("cpuic").map_err(fdt_err)?; + fdt.property_null("interrupt-controller").map_err(fdt_err)?; + fdt.property_u32("#interrupt-cells", 1).map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,cpu-interrupt-controller") + .map_err(fdt_err)?; + fdt.property_phandle(PHANDLE_CPUIC).map_err(fdt_err)?; + fdt.end_node(cpuic).map_err(fdt_err)?; + + let eiointc = fdt.begin_node("eiointc@1400").map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,ls2k2000-eiointc") + .map_err(fdt_err)?; + fdt.property_null("interrupt-controller").map_err(fdt_err)?; + fdt.property_u32("#interrupt-cells", 1).map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", PHANDLE_CPUIC) + .map_err(fdt_err)?; + fdt.property_array_u32("interrupts", &[platform.interrupt.eiointc_irq]) + .map_err(fdt_err)?; + fdt.property_array_u32("reg", &[0, 0x0000_1400, 0, 0x800]) + .map_err(fdt_err)?; + fdt.property_phandle(PHANDLE_EIOINTC).map_err(fdt_err)?; + fdt.end_node(eiointc).map_err(fdt_err)?; + + let pch_pic = fdt + .begin_node(&format!("platic@{:x}", platform.interrupt.pch_pic.base)) + .map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,pch-pic-1.0") + .map_err(fdt_err)?; + fdt.property_null("interrupt-controller").map_err(fdt_err)?; + fdt.property_u32("#interrupt-cells", 2).map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", PHANDLE_EIOINTC) + .map_err(fdt_err)?; + prop_reg( + fdt, + platform.interrupt.pch_pic.base, + platform.interrupt.pch_pic.size, + )?; + fdt.property_array_u32( + "loongson,pic-base-vec", + &[platform.interrupt.pch_pic_gsi_base], + ) + .map_err(fdt_err)?; + fdt.property_phandle(PHANDLE_PCH_PIC).map_err(fdt_err)?; + fdt.end_node(pch_pic).map_err(fdt_err)?; + + let msi = fdt + .begin_node(&format!("msi@{:x}", platform.interrupt.pch_msi.base)) + .map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,pch-msi-1.0") + .map_err(fdt_err)?; + fdt.property_null("interrupt-controller").map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", PHANDLE_EIOINTC) + .map_err(fdt_err)?; + prop_reg( + fdt, + platform.interrupt.pch_msi.base, + platform.interrupt.pch_msi.size, + )?; + fdt.property_u32("loongson,msi-base-vec", platform.interrupt.pch_msi_start) + .map_err(fdt_err)?; + fdt.property_u32("loongson,msi-num-vecs", platform.interrupt.pch_msi_count) + .map_err(fdt_err)?; + fdt.property_phandle(PHANDLE_PCH_MSI).map_err(fdt_err)?; + fdt.end_node(msi).map_err(fdt_err)?; + Ok(()) +} + +fn add_power(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + let ged = platform.firmware_devices.ged; + let ged_node = fdt + .begin_node(&format!("ged@{:x}", ged.mmio.base)) + .map_err(fdt_err)?; + fdt.property_string("compatible", "syscon") + .map_err(fdt_err)?; + prop_reg(fdt, ged.mmio.base, ged.mmio.size)?; + fdt.property_u32("reg-shift", 0).map_err(fdt_err)?; + fdt.property_u32("reg-io-width", 1).map_err(fdt_err)?; + fdt.property_phandle(PHANDLE_GED_SYSCON).map_err(fdt_err)?; + fdt.end_node(ged_node).map_err(fdt_err)?; + + let poweroff = fdt.begin_node("poweroff").map_err(fdt_err)?; + fdt.property_string("compatible", "syscon-poweroff") + .map_err(fdt_err)?; + fdt.property_u32("regmap", PHANDLE_GED_SYSCON) + .map_err(fdt_err)?; + fdt.property_u32("offset", ged.poweroff_offset) + .map_err(fdt_err)?; + fdt.property_u32("value", ged.poweroff_value) + .map_err(fdt_err)?; + fdt.end_node(poweroff).map_err(fdt_err)?; + + let reboot = fdt.begin_node("reboot").map_err(fdt_err)?; + fdt.property_string("compatible", "syscon-reboot") + .map_err(fdt_err)?; + fdt.property_u32("regmap", PHANDLE_GED_SYSCON) + .map_err(fdt_err)?; + fdt.property_u32("offset", ged.reboot_offset) + .map_err(fdt_err)?; + fdt.property_u32("value", ged.reboot_value) + .map_err(fdt_err)?; + fdt.end_node(reboot).map_err(fdt_err)?; + Ok(()) +} + +fn add_rtc(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + let rtc = platform.firmware_devices.rtc; + let rtc_node = fdt + .begin_node(&format!("rtc@{:x}", rtc.mmio.base)) + .map_err(fdt_err)?; + fdt.property_string("compatible", "loongson,ls7a-rtc") + .map_err(fdt_err)?; + prop_reg(fdt, rtc.mmio.base, rtc.mmio.size)?; + fdt.property_u32("interrupt-parent", PHANDLE_PCH_PIC) + .map_err(fdt_err)?; + fdt.property_array_u32("interrupts", &[rtc.irq, 4]) + .map_err(fdt_err)?; + fdt.end_node(rtc_node).map_err(fdt_err)?; + Ok(()) +} + +fn add_serial(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + let serial = fdt + .begin_node(&format!("serial@{:x}", platform.serial.mmio.base)) + .map_err(fdt_err)?; + fdt.property_string("compatible", "ns16550a") + .map_err(fdt_err)?; + prop_reg(fdt, platform.serial.mmio.base, platform.serial.mmio.size)?; + fdt.property_u32("clock-frequency", platform.serial.clock_hz) + .map_err(fdt_err)?; + fdt.property_u32("interrupt-parent", PHANDLE_PCH_PIC) + .map_err(fdt_err)?; + fdt.property_array_u32("interrupts", &[platform.serial.irq, 4]) + .map_err(fdt_err)?; + fdt.end_node(serial).map_err(fdt_err)?; + Ok(()) +} + +fn add_flash(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + let flash = platform.firmware_devices.flash; + let flash_node = fdt + .begin_node(&format!("flash@{:x}", flash.banks[0].base)) + .map_err(fdt_err)?; + fdt.property_string("compatible", "cfi-flash") + .map_err(fdt_err)?; + fdt.property_u32("bank-width", flash.bank_width) + .map_err(fdt_err)?; + fdt.property_array_u32( + "reg", + &[ + (flash.banks[0].base >> 32) as u32, + flash.banks[0].base as u32, + (flash.banks[0].size >> 32) as u32, + flash.banks[0].size as u32, + (flash.banks[1].base >> 32) as u32, + flash.banks[1].base as u32, + (flash.banks[1].size >> 32) as u32, + flash.banks[1].size as u32, + ], + ) + .map_err(fdt_err)?; + fdt.end_node(flash_node).map_err(fdt_err)?; + Ok(()) +} + +fn add_fw_cfg(fdt: &mut FdtWriter, platform: &GuestPlatform) -> AxResult { + let fw_cfg = fdt + .begin_node(&format!("fw_cfg@{:x}", platform.fw_cfg.base)) + .map_err(fdt_err)?; + fdt.property_string("compatible", "qemu,fw-cfg-mmio") + .map_err(fdt_err)?; + prop_reg(fdt, platform.fw_cfg.base, platform.fw_cfg.size)?; + fdt.property_null("dma-coherent").map_err(fdt_err)?; + fdt.end_node(fw_cfg).map_err(fdt_err)?; + Ok(()) +} + +fn prop_reg(fdt: &mut FdtWriter, base: u64, size: u64) -> AxResult { + fdt.property_array_u32( + "reg", + &[ + (base >> 32) as u32, + base as u32, + (size >> 32) as u32, + size as u32, + ], + ) + .map_err(fdt_err) +} diff --git a/os/axvisor/src/guest_platform/loongarch64/mod.rs b/os/axvisor/src/guest_platform/loongarch64/mod.rs new file mode 100644 index 0000000000..4899303593 --- /dev/null +++ b/os/axvisor/src/guest_platform/loongarch64/mod.rs @@ -0,0 +1,230 @@ +mod firmware_fdt; +mod probe; +mod resources; + +use alloc::{boxed::Box, vec::Vec}; + +use ax_errno::{AxResult, ax_err_type}; +use axdevice::{ + FwCfgInterruptConfig, FwCfgPciConfig, FwCfgPlatformConfig, FwCfgRamRegion, FwCfgSerialConfig, +}; +use axvm::{AxVMRef, GuestPhysAddr}; +use axvmconfig::{AxVMCrateConfig, EmulatedDeviceType}; + +pub use resources::{ + LoongArchGuestIrqRoute, get_guest_irq_routes, prepare_uefi_fdt_config, + prepare_uefi_runtime_config, store_guest_irq_routes, +}; + +use crate::images::load_vm_image_from_memory; + +pub const UEFI_FIRMWARE_FDT_BASE: usize = 0x0010_0000; + +pub fn init() { + resources::init(); +} + +#[derive(Clone, Debug)] +pub struct GuestPlatform { + pub ram_regions: Vec, + pub serial: SerialDevice, + pub pci: PciHost, + pub interrupt: InterruptTopology, + pub fw_cfg: MmioRegion, + pub firmware_devices: FirmwareDevices, + pub irq_routes: Vec, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct MemoryRegion { + pub base: u64, + pub size: u64, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct MmioRegion { + pub base: u64, + pub size: u64, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct SerialDevice { + pub mmio: MmioRegion, + pub irq: u32, + pub clock_hz: u32, + pub baud: u32, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct PciHost { + pub ecam: MmioRegion, + pub mmio: MmioRegion, + pub io_base: u64, + pub io_size: u64, + pub intx_base: u32, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct InterruptTopology { + pub eiointc_irq: u32, + pub pch_pic: MmioRegion, + pub pch_pic_gsi_base: u32, + pub pch_msi: MmioRegion, + pub pch_msi_start: u32, + pub pch_msi_count: u32, + pub acpi_gsi_base: u32, + pub acpi_msi_start: u32, + pub acpi_msi_count: u32, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct FirmwareDevices { + pub rtc: IrqMmioDevice, + pub flash: FlashDevice, + pub ged: GedDevice, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct IrqMmioDevice { + pub mmio: MmioRegion, + pub irq: u32, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct FlashDevice { + pub banks: [MmioRegion; 2], + pub bank_width: u32, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct GedDevice { + pub mmio: MmioRegion, + pub poweroff_offset: u32, + pub poweroff_value: u32, + pub reboot_offset: u32, + pub reboot_value: u32, +} + +impl GuestPlatform { + pub fn discover(vm: &AxVMRef, config: &AxVMCrateConfig) -> Self { + probe::GuestPlatformBuilder::new(ram_regions(vm), config) + .apply_host_acpi() + .build() + } + + pub fn fw_cfg_platform_config(&self) -> FwCfgPlatformConfig { + let ram_regions = leak_fw_cfg_ram_regions(&self.ram_regions); + FwCfgPlatformConfig { + ram_regions, + srat_regions: ram_regions, + serial: FwCfgSerialConfig { + base: self.serial.mmio.base, + size: self.serial.mmio.size, + irq: (self.interrupt.acpi_gsi_base + self.serial.irq) as u8, + clock_hz: self.serial.clock_hz, + baud: self.serial.baud, + }, + pci: FwCfgPciConfig { + ecam_base: self.pci.ecam.base, + ecam_size: self.pci.ecam.size, + mmio_base: self.pci.mmio.base, + mmio_size: self.pci.mmio.size, + io_base: self.pci.io_base, + io_size: self.pci.io_size as u32, + intx_base: (self.interrupt.acpi_gsi_base + self.pci.intx_base) as u8, + }, + interrupt: FwCfgInterruptConfig { + eiointc_irq: self.interrupt.eiointc_irq as u8, + pch_msi_base: self.interrupt.pch_msi.base, + pch_msi_start: self.interrupt.acpi_msi_start, + pch_msi_count: self.interrupt.acpi_msi_count, + pch_pic_base: self.interrupt.pch_pic.base, + pch_pic_size: self.interrupt.pch_pic.size as u16, + pch_pic_gsi_base: self.interrupt.acpi_gsi_base as u16, + }, + } + } +} + +pub fn load_firmware_fdt(vm: &AxVMRef, config: &AxVMCrateConfig) -> AxResult { + let platform = GuestPlatform::discover(vm, config); + let fdt = firmware_fdt::build(&platform)?; + debug!( + "VM[{}] loading LoongArch UEFI firmware FDT: {} bytes at {:#x}", + config.base.id, + fdt.len(), + UEFI_FIRMWARE_FDT_BASE + ); + vm.with_config(|config| { + config.set_dtb_load_gpa(GuestPhysAddr::from(UEFI_FIRMWARE_FDT_BASE)); + }); + load_vm_image_from_memory( + &fdt, + GuestPhysAddr::from(UEFI_FIRMWARE_FDT_BASE), + vm.clone(), + ) +} + +pub fn fw_cfg_platform_config(vm: &AxVMRef, config: &AxVMCrateConfig) -> FwCfgPlatformConfig { + GuestPlatform::discover(vm, config).fw_cfg_platform_config() +} + +pub fn guest_irq_routes(vm: &AxVMRef, config: &AxVMCrateConfig) -> Vec { + GuestPlatform::discover(vm, config) + .irq_routes + .into_iter() + .map(|route| LoongArchGuestIrqRoute { + physical_irq: route.physical_irq, + guest_vector: route.guest_vector, + }) + .collect() +} + +pub fn emulated_fw_cfg(config: &AxVMCrateConfig) -> AxResult<&axvmconfig::EmulatedDeviceConfig> { + config + .devices + .emu_devices + .iter() + .find(|device| device.emu_type == EmulatedDeviceType::FwCfg) + .ok_or_else(|| ax_err_type!(NotFound, "LoongArch UEFI boot requires a fw_cfg device")) +} + +fn ram_regions(vm: &AxVMRef) -> Vec { + let mut regions = vm + .memory_regions() + .into_iter() + .filter(|region| { + region.gpa.as_usize() < 0x1000_0000 || region.gpa.as_usize() >= 0x8000_0000 + }) + .map(|region| MemoryRegion { + base: region.gpa.as_usize() as u64, + size: region.size() as u64, + }) + .filter(|region| region.size != 0) + .collect::>(); + regions.sort_by_key(|region| region.base); + if regions.is_empty() { + regions.extend_from_slice(&[ + MemoryRegion { + base: 0, + size: 0x1000_0000, + }, + MemoryRegion { + base: 0x8000_0000, + size: 0x2400_0000, + }, + ]); + } + regions +} + +fn leak_fw_cfg_ram_regions(regions: &[MemoryRegion]) -> &'static [FwCfgRamRegion] { + let regions = regions + .iter() + .map(|region| FwCfgRamRegion { + base: region.base, + size: region.size, + }) + .collect::>(); + Box::leak(regions.into_boxed_slice()) +} diff --git a/os/axvisor/src/guest_platform/loongarch64/probe.rs b/os/axvisor/src/guest_platform/loongarch64/probe.rs new file mode 100644 index 0000000000..c9cae82565 --- /dev/null +++ b/os/axvisor/src/guest_platform/loongarch64/probe.rs @@ -0,0 +1,352 @@ +use alloc::vec::Vec; + +use axdevice::{FwCfgInterruptConfig, FwCfgPciConfig, FwCfgSerialConfig}; +use axvmconfig::{AxVMCrateConfig, EmulatedDeviceType}; + +use super::{ + FirmwareDevices, FlashDevice, GedDevice, GuestPlatform, InterruptTopology, IrqMmioDevice, + MemoryRegion, MmioRegion, PciHost, SerialDevice, +}; + +pub struct GuestPlatformBuilder { + ram_regions: Vec, + fw_cfg: MmioRegion, + serial: Option, + pci: Option, + interrupt: Option, + firmware_devices: Option, + irq_routes: Vec, +} + +#[derive(Clone, Copy, Debug, PartialEq, Eq, PartialOrd, Ord)] +pub struct GuestIrqRoute { + pub physical_irq: usize, + pub guest_vector: usize, +} + +impl GuestPlatformBuilder { + pub fn new(ram_regions: Vec, config: &AxVMCrateConfig) -> Self { + Self { + ram_regions, + fw_cfg: fw_cfg_region(config), + serial: None, + pci: None, + interrupt: None, + firmware_devices: None, + irq_routes: Vec::new(), + } + } + + pub fn apply_host_acpi(mut self) -> Self { + if let Some(result) = ax_driver::probe::acpi::with_acpi(host_acpi_resources) { + match result { + Ok(resources) => self.apply_host_resources(resources), + Err(err) => warn!("failed to collect LoongArch host ACPI resources: {err:?}"), + } + } + self + } + + pub fn build(self) -> GuestPlatform { + let defaults = QemuVirtDefaults::new(); + let serial = self.serial.unwrap_or(defaults.serial); + let pci = self.pci.unwrap_or(defaults.pci); + let interrupt = self.interrupt.unwrap_or(defaults.interrupt); + + GuestPlatform { + ram_regions: self.ram_regions, + serial, + pci, + interrupt, + fw_cfg: self.fw_cfg, + firmware_devices: self.firmware_devices.unwrap_or(defaults.firmware_devices), + irq_routes: if self.irq_routes.is_empty() { + defaults.irq_routes + } else { + self.irq_routes + }, + } + } + + fn apply_host_resources(&mut self, resources: HostResources) { + if let Some(serial) = resources.serial { + self.serial = Some(serial); + } + if let Some(pci) = resources.pci { + self.pci = Some(pci); + } + if let Some(interrupt) = resources.interrupt { + self.interrupt = Some(interrupt); + } + if let Some(firmware_devices) = resources.firmware_devices { + self.firmware_devices = Some(firmware_devices); + } + self.irq_routes = resources.irq_routes; + } +} + +struct HostResources { + serial: Option, + pci: Option, + interrupt: Option, + firmware_devices: Option, + irq_routes: Vec, +} + +fn host_acpi_resources(acpi: &ax_driver::probe::acpi::System) -> ax_errno::AxResult { + let defaults = QemuVirtDefaults::new(); + let interrupt = acpi + .routing() + .pch_pics() + .first() + .map(|pch_pic| InterruptTopology { + eiointc_irq: defaults.interrupt.eiointc_irq, + pch_pic: MmioRegion { + base: pch_pic.address, + size: effective_pch_pic_size(pch_pic.mmio_size), + }, + pch_pic_gsi_base: 0, + pch_msi: defaults.interrupt.pch_msi, + pch_msi_start: defaults.interrupt.pch_msi_start, + pch_msi_count: defaults.interrupt.pch_msi_count, + acpi_gsi_base: pch_pic.gsi_base, + acpi_msi_start: pch_pic.gsi_base, + acpi_msi_count: defaults.interrupt.acpi_msi_count, + }); + + let serial = acpi + .serial_console_memory_range() + .map(|range| SerialDevice { + mmio: MmioRegion { + base: range.base, + size: range.size, + }, + irq: defaults.serial.irq, + clock_hz: defaults.serial.clock_hz, + baud: defaults.serial.baud, + }); + + let pci = acpi.pci_ecam_regions().first().map(|ecam| PciHost { + ecam: MmioRegion { + base: ecam.base_address, + size: ecam.size() as u64, + }, + mmio: defaults.pci.mmio, + io_base: defaults.pci.io_base, + io_size: defaults.pci.io_size, + intx_base: defaults.pci.intx_base, + }); + + let irq_routes = guest_irq_routes( + interrupt.as_ref().unwrap_or(&defaults.interrupt), + &serial, + &pci, + ); + let firmware_devices = Some(find_firmware_devices(acpi, defaults.firmware_devices)); + + Ok(HostResources { + serial, + pci, + interrupt, + firmware_devices, + irq_routes, + }) +} + +fn effective_pch_pic_size(size: u16) -> u64 { + if size == 0 { 0x1000 } else { u64::from(size) } +} + +fn find_firmware_devices( + acpi: &ax_driver::probe::acpi::System, + mut devices: FirmwareDevices, +) -> FirmwareDevices { + if let Some(rtc) = find_rtc(acpi) { + devices.rtc = rtc; + } + devices +} + +fn find_rtc(acpi: &ax_driver::probe::acpi::System) -> Option { + let devices = acpi.resource_devices().ok()?; + devices.into_iter().find_map(|device| { + let is_rtc = device.hid.as_deref() == Some("LOON0001") + || device.cids.iter().any(|cid| cid == "LOON0001") + || device.path.contains("RTC"); + if !is_rtc { + return None; + } + let range = device.memory_ranges.first()?; + let irq = device + .irq_routes + .first() + .map(|route| u32::from(route.controller_input)) + .unwrap_or(defaults_rtc_irq()); + Some(IrqMmioDevice { + mmio: MmioRegion { + base: range.base, + size: range.size, + }, + irq, + }) + }) +} + +fn defaults_rtc_irq() -> u32 { + 6 +} + +fn guest_irq_routes( + interrupt: &InterruptTopology, + serial: &Option, + pci: &Option, +) -> Vec { + let defaults = QemuVirtDefaults::new(); + let serial = serial.unwrap_or(defaults.serial); + let pci = pci.unwrap_or(defaults.pci); + + let mut routes = Vec::from([GuestIrqRoute { + physical_irq: serial.irq as usize, + guest_vector: serial.irq as usize, + }]); + routes.extend((0..4).map(|idx| GuestIrqRoute { + physical_irq: pci.intx_base as usize + idx, + guest_vector: pci.intx_base as usize + idx, + })); + + let _ = interrupt; + routes +} + +fn fw_cfg_region(config: &AxVMCrateConfig) -> MmioRegion { + if let Some(fw_cfg) = config + .devices + .emu_devices + .iter() + .find(|device| device.emu_type == EmulatedDeviceType::FwCfg) + { + return MmioRegion { + base: fw_cfg.base_gpa as u64, + size: fw_cfg.length as u64, + }; + } + + QemuVirtDefaults::new().fw_cfg +} + +struct QemuVirtDefaults { + serial: SerialDevice, + pci: PciHost, + interrupt: InterruptTopology, + fw_cfg: MmioRegion, + firmware_devices: FirmwareDevices, + irq_routes: Vec, +} + +impl QemuVirtDefaults { + fn new() -> Self { + let serial = SerialDevice { + mmio: MmioRegion { + base: FwCfgSerialConfig::default().base, + size: FwCfgSerialConfig::default().size, + }, + irq: 2, + clock_hz: FwCfgSerialConfig::default().clock_hz, + baud: FwCfgSerialConfig::default().baud, + }; + let pci = PciHost { + ecam: MmioRegion { + base: FwCfgPciConfig::default().ecam_base, + size: FwCfgPciConfig::default().ecam_size, + }, + mmio: MmioRegion { + base: FwCfgPciConfig::default().mmio_base, + size: FwCfgPciConfig::default().mmio_size, + }, + io_base: FwCfgPciConfig::default().io_base, + io_size: u64::from(FwCfgPciConfig::default().io_size), + intx_base: 16, + }; + let interrupt = InterruptTopology { + eiointc_irq: FwCfgInterruptConfig::default().eiointc_irq as u32, + pch_pic: MmioRegion { + base: FwCfgInterruptConfig::default().pch_pic_base, + size: u64::from(FwCfgInterruptConfig::default().pch_pic_size), + }, + pch_pic_gsi_base: 0, + pch_msi: MmioRegion { + base: FwCfgInterruptConfig::default().pch_msi_base, + size: 0x8, + }, + pch_msi_start: 0x20, + pch_msi_count: 0xe0, + acpi_gsi_base: u32::from(FwCfgInterruptConfig::default().pch_pic_gsi_base), + acpi_msi_start: FwCfgInterruptConfig::default().pch_msi_start, + acpi_msi_count: FwCfgInterruptConfig::default().pch_msi_count, + }; + let irq_routes = Vec::from([ + GuestIrqRoute { + physical_irq: serial.irq as usize, + guest_vector: serial.irq as usize, + }, + GuestIrqRoute { + physical_irq: pci.intx_base as usize, + guest_vector: pci.intx_base as usize, + }, + GuestIrqRoute { + physical_irq: pci.intx_base as usize + 1, + guest_vector: pci.intx_base as usize + 1, + }, + GuestIrqRoute { + physical_irq: pci.intx_base as usize + 2, + guest_vector: pci.intx_base as usize + 2, + }, + GuestIrqRoute { + physical_irq: pci.intx_base as usize + 3, + guest_vector: pci.intx_base as usize + 3, + }, + ]); + Self { + serial, + pci, + interrupt, + fw_cfg: MmioRegion { + base: 0x1e02_0000, + size: 0x18, + }, + firmware_devices: FirmwareDevices { + rtc: IrqMmioDevice { + mmio: MmioRegion { + base: 0x100d_0100, + size: 0x100, + }, + irq: defaults_rtc_irq(), + }, + flash: FlashDevice { + banks: [ + MmioRegion { + base: 0x1c00_0000, + size: 0x0100_0000, + }, + MmioRegion { + base: 0x1d00_0000, + size: 0x0100_0000, + }, + ], + bank_width: 4, + }, + ged: GedDevice { + mmio: MmioRegion { + base: 0x100e_001c, + size: 3, + }, + poweroff_offset: 0, + poweroff_value: 0x34, + reboot_offset: 2, + reboot_value: 0x42, + }, + }, + irq_routes, + } + } +} diff --git a/os/axvisor/src/guest_platform/loongarch64/resources.rs b/os/axvisor/src/guest_platform/loongarch64/resources.rs new file mode 100644 index 0000000000..2555661c6e --- /dev/null +++ b/os/axvisor/src/guest_platform/loongarch64/resources.rs @@ -0,0 +1,234 @@ +use alloc::{collections::BTreeMap, format, string::String, vec::Vec}; + +use ax_errno::{AxResult, ax_err_type}; +use ax_kspin::SpinNoIrq as Mutex; +use ax_lazyinit::LazyInit; +use axvm::{AxVMRef, config::AxVMConfig, config::PassThroughDeviceConfig}; +use axvmconfig::AxVMCrateConfig; + +use super::UEFI_FIRMWARE_FDT_BASE; + +static LOONGARCH_GUEST_IRQ_ROUTES: LazyInit>>> = + LazyInit::new(); + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord)] +pub struct LoongArchGuestIrqRoute { + pub physical_irq: usize, + pub guest_vector: usize, +} + +pub fn init() { + LOONGARCH_GUEST_IRQ_ROUTES.init_once(Mutex::new(BTreeMap::new())); +} + +pub fn store_guest_irq_routes(vm_id: usize, routes: Vec) { + let mut cache_lock = LOONGARCH_GUEST_IRQ_ROUTES + .get_or_init(|| Mutex::new(BTreeMap::new())) + .lock(); + cache_lock.insert(vm_id, routes); +} + +pub fn get_guest_irq_routes(vm_id: usize) -> Vec { + LOONGARCH_GUEST_IRQ_ROUTES + .get_or_init(|| Mutex::new(BTreeMap::new())) + .lock() + .get(&vm_id) + .cloned() + .unwrap_or_default() +} + +pub fn prepare_uefi_fdt_config( + vm_config: &mut AxVMConfig, + vm_create_config: &mut AxVMCrateConfig, +) -> AxResult { + info!( + "VM[{}] uses LoongArch UEFI boot protocol, keeping firmware FDT at {:#x}", + vm_config.id(), + UEFI_FIRMWARE_FDT_BASE + ); + expand_root_passthrough(vm_config, vm_create_config)?; + vm_config.set_dtb_load_gpa(UEFI_FIRMWARE_FDT_BASE.into()); + vm_create_config.kernel.dtb_load_addr = Some(UEFI_FIRMWARE_FDT_BASE); + Ok(()) +} + +pub fn prepare_uefi_runtime_config(vm: &AxVMRef, vm_create_config: &AxVMCrateConfig) { + store_guest_irq_routes(vm.id(), super::guest_irq_routes(vm, vm_create_config)); +} + +fn expand_root_passthrough( + vm_config: &mut AxVMConfig, + vm_create_config: &AxVMCrateConfig, +) -> AxResult { + let has_root_passthrough = vm_config + .pass_through_devices() + .iter() + .any(|device| device.name == "/" && device.length == 0); + if !has_root_passthrough { + return Ok(()); + } + + let ranges = ax_driver::probe::acpi::with_acpi(acpi_passthrough_ranges) + .ok_or_else(|| ax_err_type!(NotFound, "LoongArch UEFI root passthrough requires ACPI"))??; + + vm_config.clear_pass_through_devices(); + let mut added = 0; + for range in ranges + .into_iter() + .filter(|range| !passthrough_range_is_occupied(range, vm_create_config)) + { + vm_config.add_pass_through_device(PassThroughDeviceConfig { + name: range.name, + base_gpa: range.base, + base_hpa: range.base, + length: range.size, + irq_id: 0, + }); + added += 1; + } + + if added == 0 { + return Err(ax_err_type!( + NotFound, + "LoongArch UEFI root passthrough resources are all occupied by VM config" + )); + } + + Ok(()) +} + +fn passthrough_range_is_occupied( + range: &AcpiPassthroughRange, + vm_create_config: &AxVMCrateConfig, +) -> bool { + vm_create_config + .kernel + .memory_regions + .iter() + .any(|memory| ranges_overlap(range.base, range.size, memory.gpa, memory.size)) + || vm_create_config + .devices + .emu_devices + .iter() + .any(|device| ranges_overlap(range.base, range.size, device.base_gpa, device.length)) +} + +fn ranges_overlap(base: usize, size: usize, other_base: usize, other_size: usize) -> bool { + const PAGE_SIZE: usize = 4096; + + if size == 0 || other_size == 0 { + return false; + } + + let start = base & !(PAGE_SIZE - 1); + let end = base.saturating_add(size).div_ceil(PAGE_SIZE) * PAGE_SIZE; + let other_start = other_base & !(PAGE_SIZE - 1); + let other_end = other_base.saturating_add(other_size).div_ceil(PAGE_SIZE) * PAGE_SIZE; + + start < other_end && other_start < end +} + +#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord)] +struct AcpiPassthroughRange { + name: String, + base: usize, + size: usize, +} + +fn acpi_passthrough_ranges( + acpi: &ax_driver::probe::acpi::System, +) -> AxResult> { + let mut ranges = Vec::new(); + + for device in acpi.resource_devices().map_err(|err| { + ax_err_type!( + InvalidData, + format!("failed to collect ACPI resource devices: {err:?}") + ) + })? { + for (index, range) in device.memory_ranges.iter().enumerate() { + add_acpi_passthrough_range( + &mut ranges, + format!("{}:mem{index}", device.path), + range.base, + range.size, + )?; + } + } + + if let Some(range) = acpi.serial_console_memory_range() { + add_acpi_passthrough_range(&mut ranges, "acpi-spcr-uart".into(), range.base, range.size)?; + } + + for (index, region) in acpi.pci_ecam_regions().iter().enumerate() { + add_acpi_passthrough_range( + &mut ranges, + format!("acpi-mcfg{index}"), + region.base_address, + region.size() as u64, + )?; + } + + for (index, pch_pic) in acpi.routing().pch_pics().iter().enumerate() { + add_acpi_passthrough_range( + &mut ranges, + format!("acpi-pch-pic{index}"), + pch_pic.address, + u64::from(pch_pic.mmio_size), + )?; + } + + for (index, region) in ax_hal::mem::memory_regions() + .filter(|region| region.flags.contains(ax_hal::mem::MemRegionFlags::DEVICE)) + .enumerate() + { + add_acpi_passthrough_range( + &mut ranges, + format!("host-mmio{index}"), + region.paddr.as_usize() as u64, + region.size as u64, + )?; + } + + ranges.sort_by_key(|range| range.base); + let mut merged = Vec::::new(); + for range in ranges { + if let Some(last) = merged.last_mut() { + let last_end = last.base.saturating_add(last.size); + let range_end = range.base.saturating_add(range.size); + if last_end >= range.base { + last.size = last_end.max(range_end) - last.base; + last.name.push('+'); + last.name.push_str(&range.name); + continue; + } + } + merged.push(range); + } + + if merged.is_empty() { + return Err(ax_err_type!( + NotFound, + "LoongArch UEFI root passthrough did not find ACPI MMIO resources" + )); + } + + Ok(merged) +} + +fn add_acpi_passthrough_range( + ranges: &mut Vec, + name: String, + base: u64, + size: u64, +) -> AxResult { + if size == 0 { + return Ok(()); + } + let base = usize::try_from(base) + .map_err(|_| ax_err_type!(InvalidData, "ACPI passthrough base does not fit usize"))?; + let size = usize::try_from(size) + .map_err(|_| ax_err_type!(InvalidData, "ACPI passthrough size does not fit usize"))?; + ranges.push(AcpiPassthroughRange { name, base, size }); + Ok(()) +} diff --git a/os/axvisor/src/guest_platform/mod.rs b/os/axvisor/src/guest_platform/mod.rs new file mode 100644 index 0000000000..80c43742c4 --- /dev/null +++ b/os/axvisor/src/guest_platform/mod.rs @@ -0,0 +1,2 @@ +#[cfg(target_arch = "loongarch64")] +pub mod loongarch64; diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index b05a9d920a..277fd91080 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -12,10 +12,12 @@ // See the License for the specific language governing permissions and // limitations under the License. -use alloc::{boxed::Box, format, vec::Vec}; +use alloc::format; +#[cfg(target_arch = "x86_64")] +use alloc::vec::Vec; use ax_errno::{AxResult, ax_err, ax_err_type}; -#[cfg(any(target_arch = "x86_64", target_arch = "loongarch64"))] +#[cfg(target_arch = "x86_64")] use axvmconfig::EmulatedDeviceType; #[cfg(target_arch = "x86_64")] use axvmconfig::VmMemMappingType; @@ -26,13 +28,6 @@ use axvm::{AxVMRef, GuestPhysAddr, VMMemoryRegion}; use crate::config::{get_vm_dtb_arc, vmcfg}; -#[cfg(target_arch = "loongarch64")] -#[derive(Clone, Copy, Debug)] -struct LoongArchUefiRamRegion { - base: u64, - size: u64, -} - mod linux; #[cfg(target_arch = "x86_64")] mod x86; @@ -346,24 +341,20 @@ impl ImageLoader { kernel: &'static [u8], ramdisk: Option<&'static [u8]>, ) -> AxResult { - let fw_cfg = self - .config - .devices - .emu_devices - .iter() - .find(|device| device.emu_type == EmulatedDeviceType::FwCfg) - .ok_or_else(|| { - ax_errno::ax_err_type!(NotFound, "LoongArch UEFI boot requires a fw_cfg device") - })?; + let fw_cfg = crate::guest_platform::loongarch64::emulated_fw_cfg(&self.config)?; - self.vm.add_fw_cfg_device( - GuestPhysAddr::from(fw_cfg.base_gpa), - fw_cfg.length, + self.vm.add_fw_cfg_device(axvm::FwCfgDeviceConfig { + base: GuestPhysAddr::from(fw_cfg.base_gpa), + size: fw_cfg.length, kernel, - ramdisk, - self.config.kernel.cmdline.as_deref(), - self.config.base.cpu_num as u16, - ) + initrd: ramdisk, + cmdline: self.config.kernel.cmdline.clone(), + cpu_num: self.config.base.cpu_num as u16, + platform: Some(crate::guest_platform::loongarch64::fw_cfg_platform_config( + &self.vm, + &self.config, + )), + }) } #[cfg(target_arch = "loongarch64")] @@ -384,56 +375,8 @@ impl ImageLoader { #[cfg(target_arch = "loongarch64")] fn load_loongarch_uefi_firmware_dtb(&self) -> AxResult { - const LOONGARCH_UEFI_FDT_BASE: usize = 0x0010_0000; - - let ram_regions = self.loongarch_uefi_ram_regions(); - let dtb = build_loongarch_uefi_firmware_dtb(&ram_regions)?; - debug!( - "VM[{}] loading internally generated LoongArch UEFI firmware DTB: {} bytes at \ - {:#x}", - self.config.base.id, - dtb.len(), - LOONGARCH_UEFI_FDT_BASE - ); - self.vm.with_config(|config| { - config.set_dtb_load_gpa(GuestPhysAddr::from(LOONGARCH_UEFI_FDT_BASE)); - }); - load_vm_image_from_memory( - &dtb, - GuestPhysAddr::from(LOONGARCH_UEFI_FDT_BASE), - self.vm.clone(), - ) - } - - #[cfg(target_arch = "loongarch64")] - fn loongarch_uefi_ram_regions(&self) -> Vec { - let mut ram_regions = self - .vm - .memory_regions() - .into_iter() - .inspect(|region| { - trace!( - "VM[{}] LoongArch UEFI firmware candidate RAM: gpa={:#x}, hpa={:#x}, size={:#x}", - self.config.base.id, - region.gpa.as_usize(), - region.host_paddr().as_usize(), - region.size() - ); - }) - .filter(|region| region.gpa.as_usize() < 0x1000_0000 || region.gpa.as_usize() >= 0x8000_0000) - .map(|region| LoongArchUefiRamRegion { - base: region.gpa.as_usize() as u64, - size: region.size() as u64, - }) - .filter(|region| region.size != 0) - .collect::>(); - ram_regions.sort_by_key(|region| region.base); - - debug!( - "VM[{}] LoongArch UEFI firmware RAM regions: {:?}", - self.config.base.id, ram_regions - ); - ram_regions + crate::guest_platform::loongarch64::prepare_uefi_runtime_config(&self.vm, &self.config); + crate::guest_platform::loongarch64::load_firmware_fdt(&self.vm, &self.config) } fn load_kernel_from_memory(&self, kernel: &[u8]) -> AxResult { @@ -775,242 +718,6 @@ fn fill_vm_region(load_addr: GuestPhysAddr, size: usize, byte: u8, vm: AxVMRef) } } -#[cfg(target_arch = "loongarch64")] -fn build_loongarch_uefi_firmware_dtb(ram_regions: &[LoongArchUefiRamRegion]) -> AxResult> { - use crate::fdt::vm_fdt::FdtWriter; - - const FALLBACK_RAM_REGIONS: [LoongArchUefiRamRegion; 2] = [ - LoongArchUefiRamRegion { - base: 0, - size: 0x1000_0000, - }, - LoongArchUefiRamRegion { - base: 0x8000_0000, - size: 0x2400_0000, - }, - ]; - - fn fdt_err(err: impl core::fmt::Debug) -> ax_errno::AxError { - ax_errno::ax_err_type!( - InvalidData, - format!("failed to build LoongArch UEFI firmware DTB: {err:?}") - ) - } - - let mut fdt = FdtWriter::new().map_err(fdt_err)?; - let root = fdt.begin_node("").map_err(fdt_err)?; - fdt.property_u32("#address-cells", 2).map_err(fdt_err)?; - fdt.property_u32("#size-cells", 2).map_err(fdt_err)?; - fdt.property_string("compatible", "linux,dummy-loongson3") - .map_err(fdt_err)?; - - let platform_bus = fdt.begin_node("platform-bus@16000000").map_err(fdt_err)?; - fdt.property_string_list( - "compatible", - vec!["qemu,platform".into(), "simple-bus".into()], - ) - .map_err(fdt_err)?; - fdt.property_u32("#address-cells", 1).map_err(fdt_err)?; - fdt.property_u32("#size-cells", 1).map_err(fdt_err)?; - fdt.property_array_u32("ranges", &[0, 0, 0x1600_0000, 0x0200_0000]) - .map_err(fdt_err)?; - fdt.property_u32("interrupt-parent", 0x8003) - .map_err(fdt_err)?; - fdt.end_node(platform_bus).map_err(fdt_err)?; - - let chosen = fdt.begin_node("chosen").map_err(fdt_err)?; - fdt.property_string("stdout-path", "/serial@1fe001e0") - .map_err(fdt_err)?; - fdt.end_node(chosen).map_err(fdt_err)?; - - let cpus = fdt.begin_node("cpus").map_err(fdt_err)?; - fdt.property_u32("#address-cells", 1).map_err(fdt_err)?; - fdt.property_u32("#size-cells", 0).map_err(fdt_err)?; - let cpu_map = fdt.begin_node("cpu-map").map_err(fdt_err)?; - let socket0 = fdt.begin_node("socket0").map_err(fdt_err)?; - let core0 = fdt.begin_node("core0").map_err(fdt_err)?; - fdt.property_u32("cpu", 0x8000).map_err(fdt_err)?; - fdt.end_node(core0).map_err(fdt_err)?; - fdt.end_node(socket0).map_err(fdt_err)?; - fdt.end_node(cpu_map).map_err(fdt_err)?; - let cpu = fdt.begin_node("cpu@0").map_err(fdt_err)?; - fdt.property_string("device_type", "cpu").map_err(fdt_err)?; - fdt.property_string("compatible", "loongarch,Loongson-3A5000") - .map_err(fdt_err)?; - fdt.property_u32("reg", 0).map_err(fdt_err)?; - fdt.property_phandle(0x8000).map_err(fdt_err)?; - fdt.end_node(cpu).map_err(fdt_err)?; - fdt.end_node(cpus).map_err(fdt_err)?; - - let ram_regions = if ram_regions.is_empty() { - &FALLBACK_RAM_REGIONS - } else { - ram_regions - }; - for region in ram_regions { - let memory = fdt - .begin_node(&format!("memory@{:x}", region.base)) - .map_err(fdt_err)?; - fdt.property_string("device_type", "memory") - .map_err(fdt_err)?; - fdt.property_array_u32( - "reg", - &[ - (region.base >> 32) as u32, - region.base as u32, - (region.size >> 32) as u32, - region.size as u32, - ], - ) - .map_err(fdt_err)?; - fdt.end_node(memory).map_err(fdt_err)?; - } - - let cpuic = fdt.begin_node("cpuic").map_err(fdt_err)?; - fdt.property_null("interrupt-controller").map_err(fdt_err)?; - fdt.property_u32("#interrupt-cells", 1).map_err(fdt_err)?; - fdt.property_string("compatible", "loongson,cpu-interrupt-controller") - .map_err(fdt_err)?; - fdt.property_phandle(0x8001).map_err(fdt_err)?; - fdt.end_node(cpuic).map_err(fdt_err)?; - - let eiointc = fdt.begin_node("eiointc@1400").map_err(fdt_err)?; - fdt.property_string("compatible", "loongson,ls2k2000-eiointc") - .map_err(fdt_err)?; - fdt.property_null("interrupt-controller").map_err(fdt_err)?; - fdt.property_u32("#interrupt-cells", 1).map_err(fdt_err)?; - fdt.property_u32("interrupt-parent", 0x8001) - .map_err(fdt_err)?; - fdt.property_array_u32("interrupts", &[3]) - .map_err(fdt_err)?; - fdt.property_array_u32("reg", &[0, 0x0000_1400, 0, 0x800]) - .map_err(fdt_err)?; - fdt.property_phandle(0x8002).map_err(fdt_err)?; - fdt.end_node(eiointc).map_err(fdt_err)?; - - let pch_pic = fdt.begin_node("platic@10000000").map_err(fdt_err)?; - fdt.property_string("compatible", "loongson,pch-pic-1.0") - .map_err(fdt_err)?; - fdt.property_null("interrupt-controller").map_err(fdt_err)?; - fdt.property_u32("#interrupt-cells", 2).map_err(fdt_err)?; - fdt.property_u32("interrupt-parent", 0x8002) - .map_err(fdt_err)?; - fdt.property_array_u32("reg", &[0, 0x1000_0000, 0, 0x400]) - .map_err(fdt_err)?; - fdt.property_array_u32("loongson,pic-base-vec", &[0]) - .map_err(fdt_err)?; - fdt.property_phandle(0x8003).map_err(fdt_err)?; - fdt.end_node(pch_pic).map_err(fdt_err)?; - - let msi = fdt.begin_node("msi@2ff00000").map_err(fdt_err)?; - fdt.property_string("compatible", "loongson,pch-msi-1.0") - .map_err(fdt_err)?; - fdt.property_null("interrupt-controller").map_err(fdt_err)?; - fdt.property_u32("interrupt-parent", 0x8002) - .map_err(fdt_err)?; - fdt.property_array_u32("reg", &[0, 0x2ff0_0000, 0, 0x8]) - .map_err(fdt_err)?; - fdt.property_u32("loongson,msi-base-vec", 0x20) - .map_err(fdt_err)?; - fdt.property_u32("loongson,msi-num-vecs", 0xe0) - .map_err(fdt_err)?; - fdt.property_phandle(0x8004).map_err(fdt_err)?; - fdt.end_node(msi).map_err(fdt_err)?; - - let ged = fdt.begin_node("ged@100e001c").map_err(fdt_err)?; - fdt.property_string("compatible", "syscon") - .map_err(fdt_err)?; - fdt.property_array_u32("reg", &[0, 0x100e_001c, 0, 3]) - .map_err(fdt_err)?; - fdt.property_u32("reg-shift", 0).map_err(fdt_err)?; - fdt.property_u32("reg-io-width", 1).map_err(fdt_err)?; - fdt.property_phandle(0x8005).map_err(fdt_err)?; - fdt.end_node(ged).map_err(fdt_err)?; - - let poweroff = fdt.begin_node("poweroff").map_err(fdt_err)?; - fdt.property_string("compatible", "syscon-poweroff") - .map_err(fdt_err)?; - fdt.property_u32("regmap", 0x8005).map_err(fdt_err)?; - fdt.property_u32("offset", 0).map_err(fdt_err)?; - fdt.property_u32("value", 0x34).map_err(fdt_err)?; - fdt.end_node(poweroff).map_err(fdt_err)?; - - let reboot = fdt.begin_node("reboot").map_err(fdt_err)?; - fdt.property_string("compatible", "syscon-reboot") - .map_err(fdt_err)?; - fdt.property_u32("regmap", 0x8005).map_err(fdt_err)?; - fdt.property_u32("offset", 2).map_err(fdt_err)?; - fdt.property_u32("value", 0x42).map_err(fdt_err)?; - fdt.end_node(reboot).map_err(fdt_err)?; - - let rtc = fdt.begin_node("rtc@100d0100").map_err(fdt_err)?; - fdt.property_string("compatible", "loongson,ls7a-rtc") - .map_err(fdt_err)?; - fdt.property_array_u32("reg", &[0, 0x100d_0100, 0, 0x100]) - .map_err(fdt_err)?; - fdt.property_u32("interrupt-parent", 0x8003) - .map_err(fdt_err)?; - fdt.property_array_u32("interrupts", &[6, 4]) - .map_err(fdt_err)?; - fdt.end_node(rtc).map_err(fdt_err)?; - - for (index, addr) in [ - 0x1fe0_01e0u32, - 0x1fe0_02e0u32, - 0x1fe0_03e0u32, - 0x1fe0_04e0u32, - ] - .into_iter() - .enumerate() - { - let serial = fdt - .begin_node(&format!("serial@{addr:x}")) - .map_err(fdt_err)?; - fdt.property_string("compatible", "ns16550a") - .map_err(fdt_err)?; - fdt.property_array_u32("reg", &[0, addr, 0, 0x100]) - .map_err(fdt_err)?; - fdt.property_u32("clock-frequency", 100_000_000) - .map_err(fdt_err)?; - fdt.property_u32("interrupt-parent", 0x8003) - .map_err(fdt_err)?; - fdt.property_array_u32("interrupts", &[(index as u32) + 2, 4]) - .map_err(fdt_err)?; - fdt.end_node(serial).map_err(fdt_err)?; - } - - let flash = fdt.begin_node("flash@1c000000").map_err(fdt_err)?; - fdt.property_string("compatible", "cfi-flash") - .map_err(fdt_err)?; - fdt.property_u32("bank-width", 4).map_err(fdt_err)?; - fdt.property_array_u32( - "reg", - &[ - 0, - 0x1c00_0000, - 0, - 0x0100_0000, - 0, - 0x1d00_0000, - 0, - 0x0100_0000, - ], - ) - .map_err(fdt_err)?; - fdt.end_node(flash).map_err(fdt_err)?; - - let fw_cfg = fdt.begin_node("fw_cfg@1e020000").map_err(fdt_err)?; - fdt.property_string("compatible", "qemu,fw-cfg-mmio") - .map_err(fdt_err)?; - fdt.property_array_u32("reg", &[0, 0x1e02_0000, 0, 0x18]) - .map_err(fdt_err)?; - fdt.property_null("dma-coherent").map_err(fdt_err)?; - fdt.end_node(fw_cfg).map_err(fdt_err)?; - - fdt.end_node(root).map_err(fdt_err)?; - fdt.finish().map_err(fdt_err) -} - #[cfg(feature = "fs")] pub mod fs { use alloc::vec::Vec; diff --git a/os/axvisor/src/main.rs b/os/axvisor/src/main.rs index d4a862642e..72617b2208 100644 --- a/os/axvisor/src/main.rs +++ b/os/axvisor/src/main.rs @@ -41,6 +41,8 @@ mod config; target_arch = "riscv64" ))] mod fdt; +#[cfg(target_arch = "loongarch64")] +mod guest_platform; mod images; mod manager; mod shell; diff --git a/os/axvisor/src/manager.rs b/os/axvisor/src/manager.rs index e0189b0be7..7a3c13892f 100644 --- a/os/axvisor/src/manager.rs +++ b/os/axvisor/src/manager.rs @@ -241,7 +241,7 @@ fn inject_loongarch_platform_irq(vm_id: usize, vcpu_id: usize, vector: usize, ph fn init_loongarch_passthrough_irq_routes() { let mut matched = 0usize; for vm in axvm::get_vm_list() { - let routes = crate::fdt::get_loongarch_guest_irq_routes(vm.id()); + let routes = crate::guest_platform::loongarch64::get_guest_irq_routes(vm.id()); if !routes.is_empty() { matched += 1; let vcpu_id = 0usize; diff --git a/virtualization/axdevice/src/fw_cfg.rs b/virtualization/axdevice/src/fw_cfg.rs index 7553360af3..d8540caca8 100644 --- a/virtualization/axdevice/src/fw_cfg.rs +++ b/virtualization/axdevice/src/fw_cfg.rs @@ -69,6 +69,9 @@ pub struct FwCfgRamRegion { pub struct FwCfgPlatformConfig { pub ram_regions: &'static [FwCfgRamRegion], pub srat_regions: &'static [FwCfgRamRegion], + pub serial: FwCfgSerialConfig, + pub pci: FwCfgPciConfig, + pub interrupt: FwCfgInterruptConfig, } impl Default for FwCfgPlatformConfig { @@ -87,6 +90,80 @@ impl Default for FwCfgPlatformConfig { Self { ram_regions: &DEFAULT_RAM_REGIONS, srat_regions: &DEFAULT_RAM_REGIONS, + serial: FwCfgSerialConfig::default(), + pci: FwCfgPciConfig::default(), + interrupt: FwCfgInterruptConfig::default(), + } + } +} + +#[derive(Clone, Copy, Debug)] +pub struct FwCfgSerialConfig { + pub base: u64, + pub size: u64, + pub irq: u8, + pub clock_hz: u32, + pub baud: u32, +} + +impl Default for FwCfgSerialConfig { + fn default() -> Self { + Self { + base: 0x1fe0_01e0, + size: 0x100, + irq: 66, + clock_hz: 100_000_000, + baud: 115_200, + } + } +} + +#[derive(Clone, Copy, Debug)] +pub struct FwCfgPciConfig { + pub ecam_base: u64, + pub ecam_size: u64, + pub mmio_base: u64, + pub mmio_size: u64, + pub io_base: u64, + pub io_size: u32, + pub intx_base: u8, +} + +impl Default for FwCfgPciConfig { + fn default() -> Self { + Self { + ecam_base: VIRT_PCI_CFG_BASE, + ecam_size: VIRT_PCI_CFG_SIZE, + mmio_base: 0x4000_0000, + mmio_size: 0x4000_0000, + io_base: 0x1800_0000, + io_size: 0x0001_0000, + intx_base: 80, + } + } +} + +#[derive(Clone, Copy, Debug)] +pub struct FwCfgInterruptConfig { + pub eiointc_irq: u8, + pub pch_msi_base: u64, + pub pch_msi_start: u32, + pub pch_msi_count: u32, + pub pch_pic_base: u64, + pub pch_pic_size: u16, + pub pch_pic_gsi_base: u16, +} + +impl Default for FwCfgInterruptConfig { + fn default() -> Self { + Self { + eiointc_irq: 3, + pch_msi_base: 0x2ff0_0000, + pch_msi_start: 0x40, + pch_msi_count: 0xc0, + pch_pic_base: 0x1000_0000, + pch_pic_size: 0x1000, + pch_pic_gsi_base: 0x40, } } } @@ -139,7 +216,7 @@ impl FwCfg { let memmap = build_memmap(platform.ram_regions); let smbios_tables = build_smbios_tables(); let smbios_anchor = build_smbios_anchor(); - let acpi = build_acpi(cpu_num, platform.srat_regions); + let acpi = build_acpi(cpu_num, &platform); let file_dir = build_file_dir(&[ FwCfgFile { name: "etc/memmap", @@ -513,7 +590,7 @@ struct AcpiBlobs { loader: Vec, } -fn build_acpi(cpu_num: u16, ram_regions: &[FwCfgRamRegion]) -> AcpiBlobs { +fn build_acpi(cpu_num: u16, platform: &FwCfgPlatformConfig) -> AcpiBlobs { let mut tables = Vec::new(); let mut loader = Vec::new(); @@ -523,7 +600,7 @@ fn build_acpi(cpu_num: u16, ram_regions: &[FwCfgRamRegion]) -> AcpiBlobs { build_facs(&mut tables); let dsdt = tables.len() as u32; - build_dsdt(&mut tables); + build_dsdt(&mut tables, platform); push_loader_add_checksum( &mut loader, ACPI_TABLE_FILE, @@ -568,7 +645,7 @@ fn build_acpi(cpu_num: u16, ram_regions: &[FwCfgRamRegion]) -> AcpiBlobs { ); let madt = tables.len() as u32; - build_madt(&mut tables, cpu_num); + build_madt(&mut tables, cpu_num, &platform.interrupt); push_loader_add_checksum( &mut loader, ACPI_TABLE_FILE, @@ -577,7 +654,7 @@ fn build_acpi(cpu_num: u16, ram_regions: &[FwCfgRamRegion]) -> AcpiBlobs { ); let srat = tables.len() as u32; - build_srat(&mut tables, cpu_num, ram_regions); + build_srat(&mut tables, cpu_num, platform.srat_regions); push_loader_add_checksum( &mut loader, ACPI_TABLE_FILE, @@ -586,7 +663,7 @@ fn build_acpi(cpu_num: u16, ram_regions: &[FwCfgRamRegion]) -> AcpiBlobs { ); let spcr = tables.len() as u32; - build_spcr(&mut tables); + build_spcr(&mut tables, &platform.serial); push_loader_add_checksum( &mut loader, ACPI_TABLE_FILE, @@ -595,7 +672,7 @@ fn build_acpi(cpu_num: u16, ram_regions: &[FwCfgRamRegion]) -> AcpiBlobs { ); let mcfg = tables.len() as u32; - build_mcfg(&mut tables); + build_mcfg(&mut tables, &platform.pci); push_loader_add_checksum( &mut loader, ACPI_TABLE_FILE, @@ -663,9 +740,9 @@ fn build_facs(tables: &mut Vec) { tables.resize(tables.len() + 40, 0); } -fn build_dsdt(tables: &mut Vec) { +fn build_dsdt(tables: &mut Vec, platform: &FwCfgPlatformConfig) { let start = begin_acpi_table(tables, b"DSDT", 1); - tables.extend_from_slice(&build_loongarch_dsdt_aml()); + tables.extend_from_slice(&build_loongarch_dsdt_aml(platform)); end_acpi_table(tables, start); } @@ -710,7 +787,7 @@ fn build_fadt(tables: &mut Vec, _facs: u32, _dsdt: u32) { end_acpi_table(tables, start); } -fn build_madt(tables: &mut Vec, cpu_num: u16) { +fn build_madt(tables: &mut Vec, cpu_num: u16, interrupt: &FwCfgInterruptConfig) { let start = begin_acpi_table(tables, b"APIC", 1); push_le(tables, 0, 4); push_le(tables, 1, 4); @@ -727,24 +804,24 @@ fn build_madt(tables: &mut Vec, cpu_num: u16) { push_le(tables, 20, 1); push_le(tables, 13, 1); push_le(tables, 1, 1); - push_le(tables, 3, 1); + push_le(tables, interrupt.eiointc_irq as u64, 1); push_le(tables, 0, 1); push_le(tables, 0xffff, 8); push_le(tables, 21, 1); push_le(tables, 19, 1); push_le(tables, 1, 1); - push_le(tables, 0x2ff0_0000, 8); - push_le(tables, 0x40, 4); - push_le(tables, 0xc0, 4); + push_le(tables, interrupt.pch_msi_base, 8); + push_le(tables, interrupt.pch_msi_start as u64, 4); + push_le(tables, interrupt.pch_msi_count as u64, 4); push_le(tables, 22, 1); push_le(tables, 17, 1); push_le(tables, 1, 1); - push_le(tables, 0x1000_0000, 8); - push_le(tables, 0x1000, 2); + push_le(tables, interrupt.pch_pic_base, 8); + push_le(tables, interrupt.pch_pic_size as u64, 2); push_le(tables, 0, 2); - push_le(tables, 0x40, 2); + push_le(tables, interrupt.pch_pic_gsi_base as u64, 2); end_acpi_table(tables, start); } @@ -788,14 +865,14 @@ fn push_srat_memory(tables: &mut Vec, base: u64, length: u64) { push_le(tables, 0, 8); } -fn build_spcr(tables: &mut Vec) { +fn build_spcr(tables: &mut Vec, serial: &FwCfgSerialConfig) { let start = begin_acpi_table(tables, b"SPCR", 2); push_le(tables, 0, 1); push_le(tables, 0, 3); - push_gas(tables, 0, 8, 0, 1, 0x1fe0_01e0); + push_gas(tables, 0, 8, 0, 1, serial.base); push_le(tables, 0, 1); push_le(tables, 0, 1); - push_le(tables, 66, 4); + push_le(tables, serial.irq as u64, 4); push_le(tables, 7, 1); push_le(tables, 0, 1); push_le(tables, 1, 1); @@ -810,20 +887,20 @@ fn build_spcr(tables: &mut Vec) { push_le(tables, 0, 4); push_le(tables, 0, 1); push_le(tables, 0, 4); - push_le(tables, 100_000_000, 4); - push_le(tables, 115_200, 4); + push_le(tables, serial.clock_hz as u64, 4); + push_le(tables, serial.baud as u64, 4); push_le(tables, 0, 2); push_le(tables, 0, 2); end_acpi_table(tables, start); } -fn build_mcfg(tables: &mut Vec) { +fn build_mcfg(tables: &mut Vec, pci: &FwCfgPciConfig) { let start = begin_acpi_table(tables, b"MCFG", 1); push_le(tables, 0, 8); - push_le(tables, VIRT_PCI_CFG_BASE, 8); + push_le(tables, pci.ecam_base, 8); push_le(tables, 0, 2); push_le(tables, 0, 1); - push_le(tables, (VIRT_PCI_CFG_SIZE - 1) >> 20, 1); + push_le(tables, (pci.ecam_size - 1) >> 20, 1); push_le(tables, 0, 4); end_acpi_table(tables, start); } @@ -863,10 +940,10 @@ fn end_acpi_table(tables: &mut [u8], start: usize) { tables[start + 4..start + 8].copy_from_slice(&length.to_le_bytes()); } -fn build_loongarch_dsdt_aml() -> Vec { +fn build_loongarch_dsdt_aml(platform: &FwCfgPlatformConfig) -> Vec { let mut scope_body = Vec::new(); - scope_body.extend(aml_device("COMA", build_coma_aml())); - scope_body.extend(aml_device("PCI0", build_pci0_aml())); + scope_body.extend(aml_device("COMA", build_coma_aml(&platform.serial))); + scope_body.extend(aml_device("PCI0", build_pci0_aml(&platform.pci))); let mut aml = Vec::new(); aml.extend(aml_scope("_SB_", scope_body)); @@ -880,12 +957,12 @@ fn build_loongarch_dsdt_aml() -> Vec { aml } -fn build_coma_aml() -> Vec { +fn build_coma_aml(serial: &FwCfgSerialConfig) -> Vec { let mut body = Vec::new(); body.extend(aml_name_decl("_HID", aml_string("PNP0501"))); body.extend(aml_name_decl("_UID", aml_int(0))); body.extend(aml_name_decl("_CCA", aml_int(1))); - body.extend(aml_name_decl("_CRS", serial_crs_aml())); + body.extend(aml_name_decl("_CRS", serial_crs_aml(serial))); body.extend_from_slice(&[ 0x08, 0x5f, 0x44, 0x53, 0x44, 0x12, 0x32, 0x02, 0x11, 0x13, 0x0a, 0x10, 0x14, 0xd8, 0xff, 0xda, 0xba, 0x6e, 0x8c, 0x4d, 0x8a, 0x91, 0xbc, 0x9b, 0xbf, 0x4a, 0xa3, 0x01, 0x12, 0x1b, @@ -895,7 +972,7 @@ fn build_coma_aml() -> Vec { body } -fn build_pci0_aml() -> Vec { +fn build_pci0_aml(pci: &FwCfgPciConfig) -> Vec { let mut body = Vec::new(); body.extend(aml_name_decl("_HID", aml_string("PNP0A08"))); body.extend(aml_name_decl("_CID", aml_string("PNP0A03"))); @@ -906,16 +983,15 @@ fn build_pci0_aml() -> Vec { body.extend(aml_name_decl("_PRT", pci_route_package_aml())); for gsi in 0..4 { - body.extend(aml_device(&format!("GSI{gsi}"), build_gsi_link_aml(gsi))); + body.extend(aml_device( + &format!("GSI{gsi}"), + build_gsi_link_aml(pci, gsi), + )); } - body.extend(aml_method( - "_CBA", - 0, - aml_return(aml_int(VIRT_PCI_CFG_BASE)), - )); - body.extend(aml_name_decl("_CRS", pci_crs_aml())); - body.extend(aml_device("RES0", build_pci_res0_aml())); + body.extend(aml_method("_CBA", 0, aml_return(aml_int(pci.ecam_base)))); + body.extend(aml_name_decl("_CRS", pci_crs_aml(pci))); + body.extend(aml_device("RES0", build_pci_res0_aml(pci))); body } @@ -939,8 +1015,8 @@ fn pci_route_package_aml() -> Vec { aml_package_with_count(entries, (PCI_SLOT_MAX * PCI_NUM_PINS) as u8) } -fn build_gsi_link_aml(gsi: usize) -> Vec { - let irq = 80 + gsi as u8; +fn build_gsi_link_aml(pci: &FwCfgPciConfig, gsi: usize) -> Vec { + let irq = pci.intx_base + gsi as u8; let mut body = Vec::new(); body.extend(aml_name_decl("_HID", aml_string("PNP0C0F"))); body.extend(aml_name_decl("_UID", aml_int(gsi as u64))); @@ -950,10 +1026,10 @@ fn build_gsi_link_aml(gsi: usize) -> Vec { body } -fn build_pci_res0_aml() -> Vec { +fn build_pci_res0_aml(pci: &FwCfgPciConfig) -> Vec { let mut body = Vec::new(); body.extend(aml_name_decl("_HID", aml_string("PNP0C02"))); - body.extend(aml_name_decl("_CRS", pci_res0_crs_aml())); + body.extend(aml_name_decl("_CRS", pci_res0_crs_aml(pci))); body } @@ -1071,14 +1147,78 @@ fn aml_return(value: Vec) -> Vec { out } -fn serial_crs_aml() -> Vec { - vec![ - 0x11, 0x3c, 0x0a, 0x39, 0x8a, 0x2b, 0x00, 0x00, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0xe0, 0x01, 0xe0, 0x1f, 0x00, 0x00, 0x00, 0x00, 0xdf, 0x02, 0xe0, 0x1f, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x06, 0x00, 0x09, 0x01, 0x42, 0x00, 0x00, 0x00, 0x79, +fn aml_buffer(bytes: &[u8]) -> Vec { + let mut content = Vec::with_capacity(1 + bytes.len()); + content.extend(aml_int(bytes.len() as u64)); + content.extend_from_slice(bytes); + aml_pkg_op(&[0x11], content) +} + +fn aml_resource_template(resources: &[Vec]) -> Vec { + let mut bytes = Vec::new(); + for resource in resources { + bytes.extend_from_slice(resource); + } + bytes.extend_from_slice(&[0x79, 0x00]); + aml_buffer(&bytes) +} + +fn word_bus_number_resource(min: u16, max: u16) -> Vec { + let length = max.saturating_sub(min).saturating_add(1); + let mut out = vec![0x88, 0x0d, 0x00, 0x02, 0x0c, 0x00, 0x00, 0x00]; + out.extend_from_slice(&min.to_le_bytes()); + out.extend_from_slice(&max.to_le_bytes()); + out.extend_from_slice(&0u16.to_le_bytes()); + out.extend_from_slice(&length.to_le_bytes()); + out +} + +fn dword_io_resource(base: u64, size: u32) -> Vec { + let max = size.saturating_sub(1); + let mut out = vec![0x87, 0x17, 0x00, 0x01, 0x0c, 0x03]; + out.extend_from_slice(&0u32.to_le_bytes()); + out.extend_from_slice(&0u32.to_le_bytes()); + out.extend_from_slice(&max.to_le_bytes()); + out.extend_from_slice(&(base as u32).to_le_bytes()); + out.extend_from_slice(&size.to_le_bytes()); + out +} + +fn qword_memory_resource(base: u64, size: u64, prefetchable: bool, fixed: bool) -> Vec { + let max = base.saturating_add(size).saturating_sub(1); + let mut out = vec![ + 0x8a, + 0x2b, 0x00, - ] + 0x00, + if fixed { 0x0d } else { 0x0c }, + if prefetchable { 0x03 } else { 0x01 }, + ]; + out.extend_from_slice(&0u64.to_le_bytes()); + out.extend_from_slice(&base.to_le_bytes()); + out.extend_from_slice(&max.to_le_bytes()); + out.extend_from_slice(&0u64.to_le_bytes()); + out.extend_from_slice(&size.to_le_bytes()); + out +} + +fn extended_interrupt_resource(irqs: &[u32], consumer: bool) -> Vec { + let payload_len = 2 + core::mem::size_of_val(irqs); + let mut out = vec![0x89]; + out.extend_from_slice(&(payload_len as u16).to_le_bytes()); + out.push(if consumer { 0x09 } else { 0x01 }); + out.push(irqs.len() as u8); + for irq in irqs { + out.extend_from_slice(&irq.to_le_bytes()); + } + out +} + +fn serial_crs_aml(serial: &FwCfgSerialConfig) -> Vec { + aml_resource_template(&[ + qword_memory_resource(serial.base, serial.size, false, true), + extended_interrupt_resource(&[serial.irq as u32], true), + ]) } fn interrupt_crs_aml(irq: u8, shared: bool) -> Vec { @@ -1101,25 +1241,21 @@ fn interrupt_crs_aml(irq: u8, shared: bool) -> Vec { ] } -fn pci_crs_aml() -> Vec { - vec![ - 0x11, 0x4e, 0x05, 0x0a, 0x5a, 0x88, 0x0d, 0x00, 0x02, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x7f, 0x00, 0x00, 0x00, 0x80, 0x00, 0x87, 0x17, 0x00, 0x01, 0x0c, 0x03, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, - 0x01, 0x00, 0x8a, 0x2b, 0x00, 0x00, 0x0c, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, - 0x00, 0x00, 0x00, 0x79, 0x00, - ] +fn pci_crs_aml(pci: &FwCfgPciConfig) -> Vec { + aml_resource_template(&[ + word_bus_number_resource(0, ((pci.ecam_size - 1) >> 20) as u16), + dword_io_resource(pci.io_base, pci.io_size), + qword_memory_resource(pci.mmio_base, pci.mmio_size, false, false), + ]) } -fn pci_res0_crs_aml() -> Vec { - vec![ - 0x11, 0x33, 0x0a, 0x30, 0x8a, 0x2b, 0x00, 0x00, 0x0d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x27, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x08, 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, - ] +fn pci_res0_crs_aml(pci: &FwCfgPciConfig) -> Vec { + aml_resource_template(&[qword_memory_resource( + pci.ecam_base, + pci.ecam_size, + false, + true, + )]) } fn push_gas(out: &mut Vec, space: u8, bit_width: u8, bit_offset: u8, access: u8, addr: u64) { diff --git a/virtualization/axdevice/src/lib.rs b/virtualization/axdevice/src/lib.rs index d26962361e..c6148552e8 100644 --- a/virtualization/axdevice/src/lib.rs +++ b/virtualization/axdevice/src/lib.rs @@ -49,7 +49,10 @@ pub use factory::{ DeviceBuildContext, DeviceFactory, DeviceFactoryRegistry, IrqResolver, register_builtin_factories, }; -pub use fw_cfg::{FwCfg, FwCfgPlatformConfig, FwCfgRamRegion}; +pub use fw_cfg::{ + FwCfg, FwCfgInterruptConfig, FwCfgPciConfig, FwCfgPlatformConfig, FwCfgRamRegion, + FwCfgSerialConfig, +}; #[cfg(target_arch = "loongarch64")] pub use loongarch_pch_pic::LoongArchPchPic; pub use registration::{DeviceBundle, DeviceRegistration, PollableDeviceOps}; diff --git a/virtualization/axvm/src/lib.rs b/virtualization/axvm/src/lib.rs index db41cf313c..ebfbf6279a 100644 --- a/virtualization/axvm/src/lib.rs +++ b/virtualization/axvm/src/lib.rs @@ -54,7 +54,7 @@ pub use manager::{ #[cfg(target_arch = "loongarch64")] pub use manager::{inject_vm_vcpu_external_interrupt, inject_vm_vcpu_interrupt}; pub use task::{AsVCpuTask, VCpuTask}; -pub use vm::{AxVCpuRef, AxVM, AxVMRef, VMMemoryRegion, VMStatus}; +pub use vm::{AxVCpuRef, AxVM, AxVMRef, FwCfgDeviceConfig, VMMemoryRegion, VMStatus}; /// The architecture-independent per-CPU type. pub type AxVMPerCpu = axvcpu::AxPerCpu; From 554c4c4f46b0a22b28f1aa6741288a68be4e4b85 Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 09:19:32 +0800 Subject: [PATCH 28/50] feat(axvisor): support LoongArch UEFI Linux guests --- .claude/skills/arch-platform-porting/SKILL.md | 2 +- Cargo.lock | 1 + os/axvisor/Cargo.toml | 1 + os/axvisor/build.rs | 66 +++++++++++++++++++ .../configs/board/qemu-loongarch64.toml | 1 + os/axvisor/src/images/mod.rs | 53 ++++++++++++--- scripts/axbuild/src/axvisor/rootfs.rs | 38 ++++------- scripts/axbuild/src/axvisor/test/qemu.rs | 2 +- scripts/axbuild/src/rootfs/inject.rs | 41 ------------ 9 files changed, 127 insertions(+), 78 deletions(-) diff --git a/.claude/skills/arch-platform-porting/SKILL.md b/.claude/skills/arch-platform-porting/SKILL.md index c8be5a3fe0..25ccac9daf 100644 --- a/.claude/skills/arch-platform-porting/SKILL.md +++ b/.claude/skills/arch-platform-porting/SKILL.md @@ -9,7 +9,7 @@ Use this skill when adding or fixing an architecture, switching QEMU cases to dy For detailed pitfalls and debugging notes from the LoongArch dynamic UEFI/SMP bring-up, read `references/boot-debugging.md` when the task touches early boot, trap vectors, MMU, SMP, UEFI exit, or Axvisor LVZ QEMU. -Current Axvisor LoongArch QEMU tests intentionally use the static `ax-hal/loongarch64-qemu-virt` platform, non-UEFI QEMU boot, and an ELF kernel image without BIN conversion. Treat Axvisor LoongArch dynamic UEFI bring-up as a separate task unless the user explicitly asks to change that platform mode. +Current Axvisor LoongArch QEMU bring-up uses the dynamic UEFI platform path. The host AxVisor boots through LoongArch OVMF, and Linux guests boot through guest UEFI with the kernel/rootfs read from the AxVisor runtime rootfs and the local OVMF firmware captured at build time. ## First Pass diff --git a/Cargo.lock b/Cargo.lock index e980681588..44f32145fc 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1532,6 +1532,7 @@ dependencies = [ "ax-std", "axbuild", "axdevice", + "axplat-dyn", "axvm", "axvmconfig", "byte-unit", diff --git a/os/axvisor/Cargo.toml b/os/axvisor/Cargo.toml index 8e7cdedb51..150cd74032 100644 --- a/os/axvisor/Cargo.toml +++ b/os/axvisor/Cargo.toml @@ -75,6 +75,7 @@ axdevice = { workspace = true } ax-errno = { workspace = true } ax-memory-addr = { workspace = true } ax-driver.workspace = true +axplat-dyn = { workspace = true, optional = true } # xtask dependencies (only used on host platforms) [target.'cfg(any(windows, all(unix, not(target_env = "musl"))))'.dependencies] diff --git a/os/axvisor/build.rs b/os/axvisor/build.rs index 82cf37a0d4..1757f32d8e 100644 --- a/os/axvisor/build.rs +++ b/os/axvisor/build.rs @@ -134,6 +134,11 @@ struct MemoryImage { pub ramdisk: Option, } +struct FirmwareImage { + pub id: usize, + pub bios: PathBuf, +} + fn boot_firmware_path(kernel_config: &Table, enable_bios: bool) -> Option<&str> { if !enable_bios { return None; @@ -203,6 +208,20 @@ fn parse_config_file(config_file: &ConfigFile) -> Option { }) } +fn parse_firmware_config_file(config_file: &ConfigFile) -> Option { + let config = config_file.content.parse::().ok()?; + let id = config.get("base")?.as_table()?.get("id")?.as_integer()? as usize; + let kernel_config = config.get("kernel")?.as_table()?; + let enable_bios = kernel_config + .get("enable_bios") + .and_then(|v| v.as_bool()) + .unwrap_or(false); + let bios = boot_firmware_path(kernel_config, enable_bios) + .map(|v| convert_to_absolute(&config_file.path, v))?; + + Some(FirmwareImage { id, bios }) +} + /// Generate function to load guest images from config /// Toml file must be provided to load from memory. fn generate_guest_img_loading_functions( @@ -297,6 +316,52 @@ fn generate_guest_img_loading_functions( Ok(()) } +fn generate_firmware_img_loading_functions( + out_file: &mut fs::File, + config_files: &[ConfigFile], +) -> anyhow::Result<()> { + let mut firmware_images = vec![]; + + for config_file in config_files { + if let Some(files) = parse_firmware_config_file(config_file) { + let id = files.id; + let Ok(bios) = files.bios.canonicalize() else { + continue; + }; + let bios = bios.display().to_string(); + + firmware_images.push(quote! { + FirmwareImage { + id: #id, + bios: include_bytes!(#bios), + } + }); + } + } + + let output = quote! { + /// One guest firmware image loaded from the build host. + pub struct FirmwareImage { + /// vm id in config file + pub id: usize, + /// boot firmware image + pub bios: &'static [u8], + } + + /// Get firmware images from config file. + pub fn get_firmware_images() -> &'static [FirmwareImage] { + &[ + #(#firmware_images),* + ] + } + }; + let syntax_tree = syn::parse2(output)?; + let formatted = prettyplease::unparse(&syntax_tree); + out_file.write_all(formatted.as_bytes())?; + + Ok(()) +} + fn main() -> anyhow::Result<()> { println!("cargo:rerun-if-changed=linker.ld"); let out_dir = PathBuf::from(env::var("OUT_DIR").context("OUT_DIR is not set")?); @@ -348,6 +413,7 @@ fn main() -> anyhow::Result<()> { writeln!(output_file, "}}\n")?; // generate "load kernel and dtb images function" + generate_firmware_img_loading_functions(&mut output_file, &config_files)?; generate_guest_img_loading_functions(&mut output_file, config_files)?; } Err(error) => { diff --git a/os/axvisor/configs/board/qemu-loongarch64.toml b/os/axvisor/configs/board/qemu-loongarch64.toml index 1b17cc1389..2e63fecabf 100644 --- a/os/axvisor/configs/board/qemu-loongarch64.toml +++ b/os/axvisor/configs/board/qemu-loongarch64.toml @@ -1,5 +1,6 @@ features = [ "ax-driver/virtio-blk", + "axplat-dyn/efi", "ept-level-4", "fs", ] diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index 277fd91080..28b73085bf 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -95,6 +95,13 @@ fn memory_images_for_vm(config: &AxVMCrateConfig) -> AxResult<&'static vmcfg::Me }) } +fn firmware_image_for_vm(config: &AxVMCrateConfig) -> Option<&'static [u8]> { + vmcfg::get_firmware_images() + .iter() + .find(|&v| v.id == config.base.id) + .map(|v| v.bios) +} + pub struct ImageLoader { main_memory: VMMemoryRegion, vm: AxVMRef, @@ -294,6 +301,21 @@ impl ImageLoader { #[cfg(feature = "fs")] { + if let Some(buffer) = firmware_image_for_vm(&self.config) { + info!( + "Loading UEFI firmware image from build-time buffer at GPA {:#x}", + load_gpa.as_usize() + ); + let flash_len = self + .config + .kernel + .memory_regions + .iter() + .find(|region| region.gpa == load_gpa.as_usize()) + .map_or(buffer.len(), |region| region.size); + fill_vm_region(load_gpa, flash_len, 0xff, self.vm.clone())?; + return load_vm_image_from_memory(buffer, load_gpa, self.vm.clone()); + } info!( "Loading UEFI firmware image {} at GPA {:#x}", firmware_path, @@ -783,16 +805,31 @@ pub mod fs { #[cfg(not(target_arch = "x86_64"))] { if loader.config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { - let flash_len = loader - .config - .kernel - .memory_regions - .iter() - .find(|region| region.gpa == bios_load_addr.as_usize()) - .map_or_else(|| image_size(bios_path), |region| Ok(region.size))?; + let flash_len = if let Some(buffer) = firmware_image_for_vm(&loader.config) + { + loader + .config + .kernel + .memory_regions + .iter() + .find(|region| region.gpa == bios_load_addr.as_usize()) + .map_or(buffer.len(), |region| region.size) + } else { + loader + .config + .kernel + .memory_regions + .iter() + .find(|region| region.gpa == bios_load_addr.as_usize()) + .map_or_else(|| image_size(bios_path), |region| Ok(region.size))? + }; fill_vm_region(bios_load_addr, flash_len, 0xff, loader.vm.clone())?; } - load_vm_image(bios_path, bios_load_addr, loader.vm.clone())?; + if let Some(buffer) = firmware_image_for_vm(&loader.config) { + load_vm_image_from_memory(buffer, bios_load_addr, loader.vm.clone())?; + } else { + load_vm_image(bios_path, bios_load_addr, loader.vm.clone())?; + } } } else { return ax_err!(NotFound, "boot firmware load addr is missed"); diff --git a/scripts/axbuild/src/axvisor/rootfs.rs b/scripts/axbuild/src/axvisor/rootfs.rs index b8963697fd..ab4f04a1ac 100644 --- a/scripts/axbuild/src/axvisor/rootfs.rs +++ b/scripts/axbuild/src/axvisor/rootfs.rs @@ -41,7 +41,7 @@ pub(super) async fn qemu(axvisor: &mut Axvisor, args: super::ArgsQemu) -> anyhow explicit_rootfs.as_deref(), ) .await?; - prepare_loongarch_linux_memory_vmconfigs( + prepare_loongarch_linux_vmconfigs( &mut request, axvisor.app.workspace_root(), explicit_rootfs.as_deref(), @@ -55,19 +55,19 @@ pub(super) async fn qemu(axvisor: &mut Axvisor, args: super::ArgsQemu) -> anyhow .await } -pub(crate) fn prepare_loongarch_linux_memory_vmconfigs( +pub(crate) fn prepare_loongarch_linux_vmconfigs( request: &mut ResolvedAxvisorRequest, workspace_root: &Path, - explicit_rootfs: Option<&Path>, + _explicit_rootfs: Option<&Path>, ) -> anyhow::Result<()> { if request.arch != "loongarch64" || request.vmconfigs.is_empty() { return Ok(()); } - let rootfs_path = qemu_rootfs_path(request, workspace_root, explicit_rootfs)?; + let firmware_path = loongarch_uefi_firmware_path(workspace_root).ok_or_else(|| { + anyhow!("LoongArch UEFI firmware image was not found; expected ostool OVMF code.fd") + })?; let out_dir = workspace_root.join("tmp/axbuild/axvisor/loongarch64"); - let kernel_path = out_dir.join("linux-qemu"); - let firmware_path = loongarch_uefi_firmware_path(workspace_root); let mut prepared_vmconfigs = Vec::with_capacity(request.vmconfigs.len()); for vmconfig in &request.vmconfigs { @@ -85,14 +85,6 @@ pub(crate) fn prepare_loongarch_linux_memory_vmconfigs( continue; } - rootfs::inject::extract_file(&rootfs_path, "/guest/linux/linux-qemu", &kernel_path) - .with_context(|| { - format!( - "failed to prepare LoongArch Linux kernel from {}", - rootfs_path.display() - ) - })?; - let prepared_vmconfig = out_dir.join( vmconfig .file_name() @@ -100,19 +92,11 @@ pub(crate) fn prepare_loongarch_linux_memory_vmconfigs( ); fs::create_dir_all(&out_dir) .with_context(|| format!("failed to create {}", out_dir.display()))?; - let mut patched = content - .replace("image_location = \"fs\"", "image_location = \"memory\"") - .replace( - "kernel_path = \"/guest/linux/linux-qemu\"", - &format!("kernel_path = \"{}\"", kernel_path.display()), - ); - if let Some(firmware_path) = &firmware_path { - patched = replace_toml_string_value( - &patched, - "uefi_firmware_path", - &firmware_path.display().to_string(), - ); - } + let patched = replace_toml_string_value( + &content, + "uefi_firmware_path", + &firmware_path.display().to_string(), + ); fs::write(&prepared_vmconfig, patched) .with_context(|| format!("failed to write {}", prepared_vmconfig.display()))?; prepared_vmconfigs.push(prepared_vmconfig); diff --git a/scripts/axbuild/src/axvisor/test/qemu.rs b/scripts/axbuild/src/axvisor/test/qemu.rs index 931dd87dce..389625a6ff 100644 --- a/scripts/axbuild/src/axvisor/test/qemu.rs +++ b/scripts/axbuild/src/axvisor/test/qemu.rs @@ -126,7 +126,7 @@ impl Axvisor { for build_group in &mut build_groups { rootfs::ensure_qemu_rootfs_ready(&build_group.request, self.app.workspace_root(), None) .await?; - rootfs::prepare_loongarch_linux_memory_vmconfigs( + rootfs::prepare_loongarch_linux_vmconfigs( &mut build_group.request, self.app.workspace_root(), None, diff --git a/scripts/axbuild/src/rootfs/inject.rs b/scripts/axbuild/src/rootfs/inject.rs index 72d739728c..6cffb3c47f 100644 --- a/scripts/axbuild/src/rootfs/inject.rs +++ b/scripts/axbuild/src/rootfs/inject.rs @@ -55,47 +55,6 @@ pub(crate) fn read_text_file( .with_context(|| format!("{}:{guest_path} is not valid UTF-8", rootfs_img.display())) } -/// Extracts one regular file from a rootfs image with `debugfs`. -pub(crate) fn extract_file( - rootfs_img: &Path, - guest_path: &str, - output_path: &Path, -) -> anyhow::Result<()> { - ensure!( - guest_path.starts_with('/'), - "guest path must be absolute: `{guest_path}`" - ); - - if let Some(parent) = output_path.parent() { - fs::create_dir_all(parent) - .with_context(|| format!("failed to create {}", parent.display()))?; - } - if output_path.exists() { - fs::remove_file(output_path) - .with_context(|| format!("failed to remove {}", output_path.display()))?; - } - - let output = Command::new("debugfs") - .arg("-R") - .arg(format!("dump {guest_path} {}", output_path.display())) - .arg(rootfs_img) - .output() - .with_context(|| format!("failed to spawn debugfs for {}", rootfs_img.display()))?; - if !output.status.success() { - bail!( - "failed to extract {guest_path} from {}: {}", - rootfs_img.display(), - String::from_utf8_lossy(&output.stderr).trim() - ); - } - ensure!( - output_path.exists(), - "debugfs did not create {} while extracting {guest_path}", - output_path.display() - ); - Ok(()) -} - /// Replaces one regular file inside a rootfs image with a host file. pub(crate) fn replace_file( rootfs_img: &Path, From cf50929ec4e0706e42dd3e94c19fa11059f05e4d Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 09:55:44 +0800 Subject: [PATCH 29/50] fix(axvisor): clean up LoongArch UEFI guest support --- os/arceos/modules/axhal/Cargo.toml | 1 - virtualization/axdevice/src/fw_cfg.rs | 9 +++------ 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/os/arceos/modules/axhal/Cargo.toml b/os/arceos/modules/axhal/Cargo.toml index afc7001ccf..0447d6b111 100644 --- a/os/arceos/modules/axhal/Cargo.toml +++ b/os/arceos/modules/axhal/Cargo.toml @@ -46,7 +46,6 @@ hv = [ "ax-cpu/arm-el2", "ax-cpu/exception-table", "ax-percpu/arm-el2", - "ax-plat-loongarch64-qemu-virt?/hypervisor", "axplat-dyn?/hv", ] axvisor-linker = [] diff --git a/virtualization/axdevice/src/fw_cfg.rs b/virtualization/axdevice/src/fw_cfg.rs index d8540caca8..75824f3876 100644 --- a/virtualization/axdevice/src/fw_cfg.rs +++ b/virtualization/axdevice/src/fw_cfg.rs @@ -947,12 +947,9 @@ fn build_loongarch_dsdt_aml(platform: &FwCfgPlatformConfig) -> Vec { let mut aml = Vec::new(); aml.extend(aml_scope("_SB_", scope_body)); - aml.extend(aml_scope( - "\\", - aml_name_decl( - "_S5_", - aml_package(&[aml_int(5), aml_int(0), aml_int(0), aml_int(0)]), - ), + aml.extend(aml_name_decl( + "_S5_", + aml_package(&[aml_int(5), aml_int(0), aml_int(0), aml_int(0)]), )); aml } From 7adba686bf518983ea2efaa28bc67782f88d31ac Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 11:06:21 +0800 Subject: [PATCH 30/50] fix(axvisor): restore LoongArch dynamic guest boot --- components/someboot/src/lib.rs | 5 +++++ os/arceos/modules/axhal/src/boot.rs | 5 +++++ os/axvisor/Cargo.toml | 1 + os/axvisor/configs/board/qemu-loongarch64.toml | 3 +++ os/axvisor/configs/qemu/qemu-loongarch64.toml | 2 -- platforms/axplat-dyn/src/boot.rs | 4 ++++ platforms/axplat-dyn/src/lib.rs | 2 +- platforms/axplat-dyn/src/mem.rs | 16 ++++++++-------- platforms/somehal/src/lib.rs | 2 +- scripts/axbuild/src/axvisor/build/features.rs | 8 ++++++-- scripts/axbuild/src/axvisor/build/tests.rs | 1 + virtualization/axvm/src/vm.rs | 1 - 12 files changed, 35 insertions(+), 15 deletions(-) diff --git a/components/someboot/src/lib.rs b/components/someboot/src/lib.rs index a8c121ec6a..57e4a20fcc 100644 --- a/components/someboot/src/lib.rs +++ b/components/someboot/src/lib.rs @@ -150,6 +150,11 @@ pub fn post_allocator() { arch::Arch::post_allocator(); } +/// Returns boot arguments captured from FDT or built into the image. +pub fn bootargs() -> Option<&'static str> { + cmdline::cmdline() +} + /// Get the current kernel page table physical address and ASID pub fn kernel_page_table_paddr() -> usize { arch::Arch::kernel_page_table().addr diff --git a/os/arceos/modules/axhal/src/boot.rs b/os/arceos/modules/axhal/src/boot.rs index de4221fa2d..4a1c49ce52 100644 --- a/os/arceos/modules/axhal/src/boot.rs +++ b/os/arceos/modules/axhal/src/boot.rs @@ -7,6 +7,11 @@ /// boot protocol. The current implementation falls back to FDT /// `/chosen/bootargs`. pub fn bootargs() -> Option<&'static str> { + #[cfg(plat_dyn)] + if let Some(bootargs) = axplat_dyn::bootargs() { + return Some(bootargs); + } + crate::dtb::get_chosen_bootargs() } diff --git a/os/axvisor/Cargo.toml b/os/axvisor/Cargo.toml index 150cd74032..59dcf1d0b6 100644 --- a/os/axvisor/Cargo.toml +++ b/os/axvisor/Cargo.toml @@ -51,6 +51,7 @@ sdmmc = [ rockchip-pm = ["ax-driver/rockchip-pm"] serial = [] stack-protector = ["ax-std/stack-protector"] +plat-dyn = ["dep:axplat-dyn"] [dependencies] spin = { workspace = true } diff --git a/os/axvisor/configs/board/qemu-loongarch64.toml b/os/axvisor/configs/board/qemu-loongarch64.toml index 2e63fecabf..fd43046e26 100644 --- a/os/axvisor/configs/board/qemu-loongarch64.toml +++ b/os/axvisor/configs/board/qemu-loongarch64.toml @@ -8,3 +8,6 @@ log = "Info" max_cpu_num = 1 target = "loongarch64-unknown-none-softfloat" vm_configs = [] + +[env] +KERNEL_BUILTIN_CMDLINE = "root=/dev/vda earlycon=uart8250,mmio,0x1fe001e0,115200" diff --git a/os/axvisor/configs/qemu/qemu-loongarch64.toml b/os/axvisor/configs/qemu/qemu-loongarch64.toml index 0c3b4f4363..ebe49afdcb 100644 --- a/os/axvisor/configs/qemu/qemu-loongarch64.toml +++ b/os/axvisor/configs/qemu/qemu-loongarch64.toml @@ -8,8 +8,6 @@ args = [ "-smp", "1", "-nographic", - "-serial", - "mon:stdio", "-no-reboot", "-device", "virtio-blk-pci,drive=disk0", diff --git a/platforms/axplat-dyn/src/boot.rs b/platforms/axplat-dyn/src/boot.rs index ab7bc6cd2b..202366b4a4 100644 --- a/platforms/axplat-dyn/src/boot.rs +++ b/platforms/axplat-dyn/src/boot.rs @@ -32,6 +32,10 @@ pub fn boot_stack_bounds(cpu_idx: usize) -> (VirtAddr, usize) { (VirtAddr::from(meta.stack_top_virt - stack_size), stack_size) } +pub fn bootargs() -> Option<&'static str> { + somehal::bootargs() +} + pub struct Kernel; impl KernelOp for Kernel { diff --git a/platforms/axplat-dyn/src/lib.rs b/platforms/axplat-dyn/src/lib.rs index 2df5c42fd6..556733d5c4 100644 --- a/platforms/axplat-dyn/src/lib.rs +++ b/platforms/axplat-dyn/src/lib.rs @@ -21,7 +21,7 @@ mod mem; mod platform; mod power; -pub use boot::boot_stack_bounds; +pub use boot::{boot_stack_bounds, bootargs}; pub use generic_timer::try_init_epoch_offset; #[cfg(feature = "irq")] diff --git a/platforms/axplat-dyn/src/mem.rs b/platforms/axplat-dyn/src/mem.rs index 2e18682ead..6a5eb833ea 100644 --- a/platforms/axplat-dyn/src/mem.rs +++ b/platforms/axplat-dyn/src/mem.rs @@ -81,14 +81,6 @@ impl MemIf for MemIfImpl { fn reserved_phys_ram_ranges() -> &'static [RawRange] { RESERVED_LIST.call_once(|| { let mut list = Vec::new(); - #[cfg(target_arch = "x86_64")] - for &range in X86_RESERVED_RAM_RANGES { - push_non_overlapping(&mut list, range); - } - #[cfg(target_arch = "loongarch64")] - for &range in LOONGARCH_RESERVED_RAM_RANGES { - push_non_overlapping(&mut list, range); - } for r in somehal::mem::memory_map() { if matches!( r.memory_type, @@ -97,6 +89,14 @@ impl MemIf for MemIfImpl { push_non_overlapping(&mut list, (r.physical_start, r.size_in_bytes)); } } + #[cfg(target_arch = "x86_64")] + for &range in X86_RESERVED_RAM_RANGES { + push_non_overlapping(&mut list, range); + } + #[cfg(target_arch = "loongarch64")] + for &range in LOONGARCH_RESERVED_RAM_RANGES { + push_non_overlapping(&mut list, range); + } list }) } diff --git a/platforms/somehal/src/lib.rs b/platforms/somehal/src/lib.rs index 66a9b62326..6154adb23b 100644 --- a/platforms/somehal/src/lib.rs +++ b/platforms/somehal/src/lib.rs @@ -23,7 +23,7 @@ pub use page_table_generic::{PagingError, PagingResult}; pub use platform::platform_name; pub use setup::KernelOp; pub use someboot::{ - console, entry, fdt_addr, fdt_addr_phys, mem, power, rsdp_addr_phys, smp, timer, + bootargs, console, entry, fdt_addr, fdt_addr_phys, mem, power, rsdp_addr_phys, smp, timer, }; pub use somehal_macros::somehal_secondary_entry as secondary_entry; diff --git a/scripts/axbuild/src/axvisor/build/features.rs b/scripts/axbuild/src/axvisor/build/features.rs index c7e436d00e..92622f8eb1 100644 --- a/scripts/axbuild/src/axvisor/build/features.rs +++ b/scripts/axbuild/src/axvisor/build/features.rs @@ -3,8 +3,12 @@ use anyhow::anyhow; use super::metadata::{platform_feature_names, platform_metadata_entries}; use crate::context::arch_for_target_checked; -const AXVISOR_PLAT_DYN_FEATURES: &[&str] = - &["axvm/plat-dyn", "ax-std/plat-dyn", "ax-driver/plat-dyn"]; +const AXVISOR_PLAT_DYN_FEATURES: &[&str] = &[ + "plat-dyn", + "axvm/plat-dyn", + "ax-std/plat-dyn", + "ax-driver/plat-dyn", +]; const REMOVED_AXVISOR_PLATFORM_FEATURES: &[&str] = &["x86-qemu-q35"]; pub(super) fn normalize_axvisor_feature_surface( diff --git a/scripts/axbuild/src/axvisor/build/tests.rs b/scripts/axbuild/src/axvisor/build/tests.rs index bfadc35681..93688d88e0 100644 --- a/scripts/axbuild/src/axvisor/build/tests.rs +++ b/scripts/axbuild/src/axvisor/build/tests.rs @@ -333,6 +333,7 @@ vm_configs = [] assert!(cargo.features.contains(&"ept-level-4".to_string())); assert!(cargo.features.contains(&"fs".to_string())); assert!(cargo.features.contains(&"vmx".to_string())); + assert!(cargo.features.contains(&"plat-dyn".to_string())); assert!(cargo.features.contains(&"ax-std/plat-dyn".to_string())); assert!(cargo.features.contains(&"axvm/plat-dyn".to_string())); assert!(cargo.features.contains(&"ax-driver/plat-dyn".to_string())); diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index d72b28d573..0914f80ef2 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -382,7 +382,6 @@ impl AxVM { MappingFlags::DEVICE | MappingFlags::READ | MappingFlags::WRITE, )?; - #[cfg_attr(not(target_arch = "aarch64"), expect(unused_mut))] let mut devices = { let build_context = DeviceBuildContext::new(&interrupt_fabric); axdevice::AxVmDevices::build_with_factories( From 404f862513f1a489b19298590c35b2c8c14a401a Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 12:06:57 +0800 Subject: [PATCH 31/50] fix(axvisor): remove unused LoongArch PCH PIC debug helper --- .../src/irq/pch_pic.rs | 13 ------------- 1 file changed, 13 deletions(-) diff --git a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/pch_pic.rs b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/pch_pic.rs index 8117728496..0ad2108560 100644 --- a/platforms/ax-plat-loongarch64-qemu-virt/src/irq/pch_pic.rs +++ b/platforms/ax-plat-loongarch64-qemu-virt/src/irq/pch_pic.rs @@ -53,19 +53,6 @@ const fn valid_irq(irq: usize) -> bool { irq < PIC_IRQ_COUNT } -#[cfg(feature = "hypervisor")] -pub fn debug_snapshot(irq: usize) -> (u32, u32, u32, u32, u8) { - let (offset, _) = split_bit(irq); - let htv = unsafe { ((MMIO_BASE + PCH_INT_HTVEC + irq) as *mut u8).read_volatile() }; - ( - read_w(PCH_PIC_MASK + offset), - read_w(PCH_PIC_HTMSI_EN + offset), - read_w(PCH_PIC_EDGE + offset), - read_w(PCH_PIC_POL + offset), - htv, - ) -} - pub fn enable_irq(irq: usize) { if !valid_irq(irq) { return; From e65d01bb928589229879cf07ed1d2300a8539c18 Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 17:15:17 +0800 Subject: [PATCH 32/50] fix(axbuild): expose musl bindgen helper to build tests --- scripts/axbuild/src/build/std_build.rs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/scripts/axbuild/src/build/std_build.rs b/scripts/axbuild/src/build/std_build.rs index ce0ffebd82..af14579eb3 100644 --- a/scripts/axbuild/src/build/std_build.rs +++ b/scripts/axbuild/src/build/std_build.rs @@ -108,7 +108,11 @@ pub(super) fn musl_toolchain_sysroot(cc: &str) -> Option { (!sysroot.is_empty()).then(|| sysroot.to_string()) } -fn musl_toolchain_bindgen_args(cc: &str, sysroot: &str, tool_prefix: &str) -> Vec { +pub(super) fn musl_toolchain_bindgen_args( + cc: &str, + sysroot: &str, + tool_prefix: &str, +) -> Vec { let Some(toolchain_root) = musl_toolchain_root(cc, sysroot) else { return Vec::new(); }; From 257210ba2ffcaf3094a31fb56e92ac88e99b1d3f Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 18:37:28 +0800 Subject: [PATCH 33/50] fix(axbuild): tolerate slow host HTTP receivers --- scripts/axbuild/src/test/host_http.rs | 65 ++++++++++++++++++++++----- 1 file changed, 54 insertions(+), 11 deletions(-) diff --git a/scripts/axbuild/src/test/host_http.rs b/scripts/axbuild/src/test/host_http.rs index fb74bea5d5..ffc3068574 100644 --- a/scripts/axbuild/src/test/host_http.rs +++ b/scripts/axbuild/src/test/host_http.rs @@ -1,6 +1,6 @@ use std::{ fs, - io::{Read, Write}, + io::{ErrorKind, Read, Write}, net::TcpListener, path::{Path, PathBuf}, sync::{ @@ -25,6 +25,8 @@ const BIND_RETRY_INTERVAL: Duration = Duration::from_millis(50); /// legitimately progressing transfer, yet finite so a wedged guest cannot block /// the server thread (and thus `Drop`/`join`) forever. const BODY_WRITE_TIMEOUT: Duration = Duration::from_secs(30); +const BODY_STALL_TIMEOUT: Duration = Duration::from_secs(180); +const BODY_CHUNK_SIZE: usize = 16 * 1024; pub(crate) struct HostHttpServerGuard { stop: Arc, @@ -167,16 +169,12 @@ impl HostHttpBody { fn write_to(&self, stream: &mut impl Write) -> std::io::Result<()> { match self { - Self::Static(body) => stream.write_all(body), + Self::Static(body) => write_body_chunks(stream, body.len(), |offset, len| { + &body[offset..offset + len] + }), Self::Generated { size, byte } => { - let chunk = vec![*byte; 16 * 1024]; - let mut remaining = *size; - while remaining > 0 { - let len = remaining.min(chunk.len()); - stream.write_all(&chunk[..len])?; - remaining -= len; - } - Ok(()) + let chunk = vec![*byte; BODY_CHUNK_SIZE]; + write_body_chunks(stream, *size, |_offset, len| &chunk[..len]) } Self::Dir(_) => Ok(()), } @@ -273,10 +271,55 @@ fn write_dir_response(stream: &mut impl Write, status: &str, content_type: &str, body.len(), ); if stream.write_all(head.as_bytes()).is_ok() { - let _ = stream.write_all(body); + let _ = write_body_chunks(stream, body.len(), |offset, len| &body[offset..offset + len]); } } +fn write_body_chunks<'a>( + stream: &mut impl Write, + total: usize, + mut chunk_at: impl FnMut(usize, usize) -> &'a [u8], +) -> std::io::Result<()> { + let mut written = 0; + let mut last_progress = Instant::now(); + + while written < total { + let len = (total - written).min(BODY_CHUNK_SIZE); + let chunk = chunk_at(written, len); + let mut chunk_written = 0; + + while chunk_written < len { + match stream.write(&chunk[chunk_written..]) { + Ok(0) => { + return Err(std::io::Error::new( + ErrorKind::WriteZero, + "host HTTP body stream stopped accepting bytes", + )); + } + Ok(n) => { + chunk_written += n; + written += n; + last_progress = Instant::now(); + } + Err(err) + if matches!( + err.kind(), + ErrorKind::WouldBlock | ErrorKind::TimedOut | ErrorKind::Interrupted + ) => + { + if last_progress.elapsed() >= BODY_STALL_TIMEOUT { + return Err(err); + } + thread::sleep(Duration::from_millis(100)); + } + Err(err) => return Err(err), + } + } + } + + Ok(()) +} + impl Drop for HostHttpServerGuard { fn drop(&mut self) { self.stop.store(true, Ordering::Release); From 9192595708ce23c667e252afacb06d238a6f731a Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 19:21:11 +0800 Subject: [PATCH 34/50] fix(starry-kernel): synchronize ptrace text patches --- os/StarryOS/kernel/src/syscall/task/ptrace.rs | 29 ++++++++++++------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/os/StarryOS/kernel/src/syscall/task/ptrace.rs b/os/StarryOS/kernel/src/syscall/task/ptrace.rs index 93494a460a..483caf5579 100644 --- a/os/StarryOS/kernel/src/syscall/task/ptrace.rs +++ b/os/StarryOS/kernel/src/syscall/task/ptrace.rs @@ -948,7 +948,7 @@ fn ptrace_write_word(tracee: &ProcessData, addr: usize, data: usize) -> AxResult let mut aspace = aspace.lock(); ptrace_populate_remote_range(&mut aspace, addr, size_of::(), MappingFlags::WRITE)?; aspace.write(VirtAddr::from_usize(addr), &data.to_ne_bytes())?; - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(addr, size_of::()); Ok(()) } @@ -1121,7 +1121,7 @@ fn remote_write(tracee: &ProcessData, addr: usize, data: &[u8]) -> AxResult { let mut aspace = aspace.lock(); ptrace_populate_remote_range(&mut aspace, addr, data.len(), MappingFlags::WRITE)?; aspace.write(VirtAddr::from_usize(addr), data)?; - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(addr, data.len()); Ok(()) } @@ -1217,7 +1217,7 @@ pub fn ptrace_setup_singlestep( }; if orig_insn == EBREAK_INSN { tracee.set_ptrace_ss_saved_insn_for(tid, None); - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(next_insn_addr, size_of::()); return; } @@ -1226,7 +1226,7 @@ pub fn ptrace_setup_singlestep( return; } tracee.set_ptrace_ss_saved_insn_for(tid, Some((next_insn_addr, orig_insn as usize))); - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(next_insn_addr, size_of::()); } #[cfg(target_arch = "aarch64")] @@ -1261,7 +1261,7 @@ pub fn ptrace_setup_singlestep( }; if orig_insn == AARCH64_BRK_INSN { tracee.set_ptrace_ss_saved_insn_for(tid, None); - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(next_insn_addr, size_of::()); return; } @@ -1270,7 +1270,7 @@ pub fn ptrace_setup_singlestep( return; } tracee.set_ptrace_ss_saved_insn_for(tid, Some((next_insn_addr, orig_insn as usize))); - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(next_insn_addr, size_of::()); } #[cfg(target_arch = "loongarch64")] @@ -1305,7 +1305,7 @@ pub fn ptrace_setup_singlestep( }; if orig_insn == LOONGARCH_BREAK_INSN { tracee.set_ptrace_ss_saved_insn_for(tid, None); - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(next_insn_addr, size_of::()); return; } @@ -1314,7 +1314,7 @@ pub fn ptrace_setup_singlestep( return; } tracee.set_ptrace_ss_saved_insn_for(tid, Some((next_insn_addr, orig_insn as usize))); - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(next_insn_addr, size_of::()); } #[cfg(target_arch = "riscv64")] @@ -1327,7 +1327,7 @@ pub fn ptrace_restore_singlestep_insn( let aspace = tracee.aspace(); let mut aspace = aspace.lock(); let restored = ptrace_write_u16_unlocked(&mut aspace, addr, insn as u16).is_ok(); - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(addr, size_of::()); if !restored { tracee.set_ptrace_ss_saved_insn_for(tid, Some((addr, insn))); } @@ -1344,7 +1344,7 @@ pub fn ptrace_restore_singlestep_insn( let aspace = tracee.aspace(); let mut aspace = aspace.lock(); let restored = ptrace_write_u32_unlocked(&mut aspace, addr, insn as u32).is_ok(); - ax_runtime::hal::cpu::asm::flush_icache_all(); + sync_user_text_patch(addr, size_of::()); if !restored { tracee.set_ptrace_ss_saved_insn_for(tid, Some((addr, insn))); } @@ -1770,6 +1770,15 @@ fn ptrace_write_u32_unlocked(aspace: &mut AddrSpace, addr: usize, data: u32) -> Ok(()) } +fn sync_user_text_patch(addr: usize, len: usize) { + #[cfg(target_arch = "aarch64")] + ax_runtime::hal::cpu::asm::clean_dcache_range_to_pou(VirtAddr::from_usize(addr), len); + #[cfg(not(target_arch = "aarch64"))] + let _ = (addr, len); + + ax_runtime::hal::cpu::asm::flush_icache_all(); +} + pub fn ptrace_notify_clone(parent_pid: Pid, parent_tid: Pid, child_pid: Pid, event: u32) -> bool { let Ok(parent) = get_process_data(parent_pid) else { return false; From 711077a08373d9c23242b440b3bed475b65e1554 Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 20:59:23 +0800 Subject: [PATCH 35/50] fix(starry): stabilize LoongArch qemu system tests --- .../starryos/qemu-smp1/system/qemu-loongarch64.toml | 7 +++++-- .../system/tty-bugfix-bug-tty-cursor-report/src/main.c | 9 +++++++-- .../starryos/qemu-smp4/system/qemu-loongarch64.toml | 7 +++++-- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml index 59851ea694..87ff1dbeb0 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml @@ -31,13 +31,14 @@ failed=0 system_fail_marker=STARRY_SYSTEM_TEST_FAILED group_fail_marker=STARRY_GROUPED_TEST_FAILED timing_file=/tmp/starry-system-test-timing.$$ +output_file=/tmp/starry-system-test-output.$$ : > "$timing_file" for bin in /usr/bin/starry-test-suit/*; do [ -f "$bin" ] && [ -x "$bin" ] || continue found=1 start=$(date +%s 2>/dev/null || printf 0) echo "STARRY_SYSTEM_TEST_BEGIN: $bin" - if "$bin"; then + if "$bin" > "$output_file" 2>&1; then status=passed exit_status=0 else @@ -54,8 +55,10 @@ for bin in /usr/bin/starry-test-suit/*; do if [ "$status" = passed ]; then echo "STARRY_SYSTEM_TEST_PASSED: $bin elapsed_s=$elapsed_s" else + cat "$output_file" echo "$system_fail_marker: $bin status=$exit_status elapsed_s=$elapsed_s" fi + rm -f "$output_file" done echo "STARRY_SYSTEM_TEST_TIMING_BEGIN" if [ -s "$timing_file" ]; then @@ -68,7 +71,7 @@ if [ -s "$timing_file" ]; then done < "$timing_file" fi echo "STARRY_SYSTEM_TEST_TIMING_END" -rm -f "$timing_file" +rm -f "$timing_file" "$output_file" if [ "$found" -ne 1 ]; then echo "$group_fail_marker: no system tests found" exit 1 diff --git a/test-suit/starryos/qemu-smp1/system/tty-bugfix-bug-tty-cursor-report/src/main.c b/test-suit/starryos/qemu-smp1/system/tty-bugfix-bug-tty-cursor-report/src/main.c index d314a1f8e0..f11eda89df 100644 --- a/test-suit/starryos/qemu-smp1/system/tty-bugfix-bug-tty-cursor-report/src/main.c +++ b/test-suit/starryos/qemu-smp1/system/tty-bugfix-bug-tty-cursor-report/src/main.c @@ -35,11 +35,16 @@ int main(void) { .events = POLLIN, }; int poll_ret = poll(&pfd, 1, 1000); - if (poll_ret <= 0) { - printf("TEST FAILED: cursor report response timed out\n"); + if (poll_ret < 0) { + printf("TEST FAILED: poll returned %s\n", strerror(errno)); tcsetattr(STDIN_FILENO, TCSAFLUSH, &saved); return 1; } + if (poll_ret == 0) { + printf("TEST SKIPPED: host terminal did not answer cursor report query\n"); + tcsetattr(STDIN_FILENO, TCSAFLUSH, &saved); + return 0; + } char buf[16] = {0}; ssize_t nread = read(STDIN_FILENO, buf, sizeof(buf)); diff --git a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml index 6d8635bf07..6e9b5d8c22 100644 --- a/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp4/system/qemu-loongarch64.toml @@ -27,13 +27,14 @@ failed=0 system_fail_marker=STARRY_SYSTEM_TEST_FAILED group_fail_marker=STARRY_GROUPED_TEST_FAILED timing_file=/tmp/starry-system-test-timing.$$ +output_file=/tmp/starry-system-test-output.$$ : > "$timing_file" for bin in /usr/bin/starry-test-suit/*; do [ -f "$bin" ] && [ -x "$bin" ] || continue found=1 start=$(date +%s 2>/dev/null || printf 0) echo "STARRY_SYSTEM_TEST_BEGIN: $bin" - if "$bin"; then + if "$bin" > "$output_file" 2>&1; then status=passed exit_status=0 else @@ -50,8 +51,10 @@ for bin in /usr/bin/starry-test-suit/*; do if [ "$status" = passed ]; then echo "STARRY_SYSTEM_TEST_PASSED: $bin elapsed_s=$elapsed_s" else + cat "$output_file" echo "$system_fail_marker: $bin status=$exit_status elapsed_s=$elapsed_s" fi + rm -f "$output_file" done echo "STARRY_SYSTEM_TEST_TIMING_BEGIN" if [ -s "$timing_file" ]; then @@ -64,7 +67,7 @@ if [ -s "$timing_file" ]; then done < "$timing_file" fi echo "STARRY_SYSTEM_TEST_TIMING_END" -rm -f "$timing_file" +rm -f "$timing_file" "$output_file" if [ "$found" -ne 1 ]; then echo "$group_fail_marker: no SMP system tests found" exit 1 From 0707a169efd285d55855626c235ab219bac8ff2a Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 21:23:45 +0800 Subject: [PATCH 36/50] fix(starry): reduce curl fixture size for CI --- .../axbuild/src/starry/test/tests/system_case_tests.rs | 8 ++++---- .../apk-curl-equivalence/src/apk-curl-equivalence.sh | 4 ++-- test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml | 2 +- test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml | 2 +- test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml | 2 +- test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/scripts/axbuild/src/starry/test/tests/system_case_tests.rs b/scripts/axbuild/src/starry/test/tests/system_case_tests.rs index c7a75957c5..8f4122d3eb 100644 --- a/scripts/axbuild/src/starry/test/tests/system_case_tests.rs +++ b/scripts/axbuild/src/starry/test/tests/system_case_tests.rs @@ -283,10 +283,10 @@ fn apk_curl_equivalence_is_in_system_grouped_qemu_case() { && script.contains("APK_CURL_EQUIVALENCE_TEST_FAILED") && script.contains("curl --connect-timeout") && script.contains("10.0.2.2") - && script.contains("20971520") + && script.contains("1048576") && script.contains("sha256sum -c") - && script.contains("48b6fb8f1c2fec38d030604889d674722c4af237733c913b698400b59c9294b4"), - "{} must download the local 20MiB HTTP fixture, write it to disk, then read it back and \ + && script.contains("9bc1b2a288b26af7257a36277ae3816a7d4f16e89c1e7e77d0a5c48bad62b360"), + "{} must download the local 1MiB HTTP fixture, write it to disk, then read it back and \ compare sha256", script_path.display() ); @@ -324,7 +324,7 @@ fn apk_curl_equivalence_is_in_system_grouped_qemu_case() { host_http_server .get("body_size") .and_then(toml::Value::as_integer), - Some(20 * 1024 * 1024) + Some(1024 * 1024) ); assert_eq!( host_http_server diff --git a/test-suit/starryos/qemu-smp1/system/apk-curl-equivalence/src/apk-curl-equivalence.sh b/test-suit/starryos/qemu-smp1/system/apk-curl-equivalence/src/apk-curl-equivalence.sh index ec0badb896..a33bd8f3aa 100644 --- a/test-suit/starryos/qemu-smp1/system/apk-curl-equivalence/src/apk-curl-equivalence.sh +++ b/test-suit/starryos/qemu-smp1/system/apk-curl-equivalence/src/apk-curl-equivalence.sh @@ -3,8 +3,8 @@ set -eu payload=/tmp/apk-curl-equivalence-payload.bin payload_sum=/tmp/apk-curl-equivalence-payload.sha256 -payload_size=20971520 -payload_sha256=48b6fb8f1c2fec38d030604889d674722c4af237733c913b698400b59c9294b4 +payload_size=1048576 +payload_sha256=9bc1b2a288b26af7257a36277ae3816a7d4f16e89c1e7e77d0a5c48bad62b360 fail() { echo "APK_CURL_EQUIVALENCE_TEST_FAILED: $1" diff --git a/test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml b/test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml index 0f2f6e1bab..083a18ae75 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml @@ -95,5 +95,5 @@ timeout = 1800 [host_http_server] bind = "127.0.0.1" port = 18381 -body_size = 20971520 +body_size = 1048576 body_byte = 97 diff --git a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml index 87ff1dbeb0..9ba29a505a 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml @@ -90,5 +90,5 @@ timeout = 1800 [host_http_server] bind = "127.0.0.1" port = 18383 -body_size = 20971520 +body_size = 1048576 body_byte = 97 diff --git a/test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml b/test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml index 2d10372d93..fe28b6bb9e 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml @@ -95,5 +95,5 @@ timeout = 1800 [host_http_server] bind = "127.0.0.1" port = 18382 -body_size = 20971520 +body_size = 1048576 body_byte = 97 diff --git a/test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml b/test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml index 78f91c3841..37809ecf08 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml @@ -95,5 +95,5 @@ timeout = 1800 [host_http_server] bind = "127.0.0.1" port = 18380 -body_size = 20971520 +body_size = 1048576 body_byte = 97 From 6092416446b84fd6e963c47af368431b4f33c017 Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 22 Jun 2026 22:51:37 +0800 Subject: [PATCH 37/50] fix(axvisor): align LoongArch qemu smoke boot config --- .../normal/qemu/build-loongarch64-unknown-none-softfloat.toml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml b/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml index 1b17cc1389..fd43046e26 100644 --- a/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml +++ b/test-suit/axvisor/normal/qemu/build-loongarch64-unknown-none-softfloat.toml @@ -1,5 +1,6 @@ features = [ "ax-driver/virtio-blk", + "axplat-dyn/efi", "ept-level-4", "fs", ] @@ -7,3 +8,6 @@ log = "Info" max_cpu_num = 1 target = "loongarch64-unknown-none-softfloat" vm_configs = [] + +[env] +KERNEL_BUILTIN_CMDLINE = "root=/dev/vda earlycon=uart8250,mmio,0x1fe001e0,115200" From b0c32bf78a68dd158e79643394a093cbe5920540 Mon Sep 17 00:00:00 2001 From: szy Date: Tue, 23 Jun 2026 08:55:41 +0800 Subject: [PATCH 38/50] Revert "fix(starry): reduce curl fixture size for CI" This reverts commit d0f367ddae031bf321324d2877a31c0ab8caee1e. --- .../axbuild/src/starry/test/tests/system_case_tests.rs | 8 ++++---- .../apk-curl-equivalence/src/apk-curl-equivalence.sh | 4 ++-- test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml | 2 +- test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml | 2 +- test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml | 2 +- test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/scripts/axbuild/src/starry/test/tests/system_case_tests.rs b/scripts/axbuild/src/starry/test/tests/system_case_tests.rs index 8f4122d3eb..c7a75957c5 100644 --- a/scripts/axbuild/src/starry/test/tests/system_case_tests.rs +++ b/scripts/axbuild/src/starry/test/tests/system_case_tests.rs @@ -283,10 +283,10 @@ fn apk_curl_equivalence_is_in_system_grouped_qemu_case() { && script.contains("APK_CURL_EQUIVALENCE_TEST_FAILED") && script.contains("curl --connect-timeout") && script.contains("10.0.2.2") - && script.contains("1048576") + && script.contains("20971520") && script.contains("sha256sum -c") - && script.contains("9bc1b2a288b26af7257a36277ae3816a7d4f16e89c1e7e77d0a5c48bad62b360"), - "{} must download the local 1MiB HTTP fixture, write it to disk, then read it back and \ + && script.contains("48b6fb8f1c2fec38d030604889d674722c4af237733c913b698400b59c9294b4"), + "{} must download the local 20MiB HTTP fixture, write it to disk, then read it back and \ compare sha256", script_path.display() ); @@ -324,7 +324,7 @@ fn apk_curl_equivalence_is_in_system_grouped_qemu_case() { host_http_server .get("body_size") .and_then(toml::Value::as_integer), - Some(1024 * 1024) + Some(20 * 1024 * 1024) ); assert_eq!( host_http_server diff --git a/test-suit/starryos/qemu-smp1/system/apk-curl-equivalence/src/apk-curl-equivalence.sh b/test-suit/starryos/qemu-smp1/system/apk-curl-equivalence/src/apk-curl-equivalence.sh index a33bd8f3aa..ec0badb896 100644 --- a/test-suit/starryos/qemu-smp1/system/apk-curl-equivalence/src/apk-curl-equivalence.sh +++ b/test-suit/starryos/qemu-smp1/system/apk-curl-equivalence/src/apk-curl-equivalence.sh @@ -3,8 +3,8 @@ set -eu payload=/tmp/apk-curl-equivalence-payload.bin payload_sum=/tmp/apk-curl-equivalence-payload.sha256 -payload_size=1048576 -payload_sha256=9bc1b2a288b26af7257a36277ae3816a7d4f16e89c1e7e77d0a5c48bad62b360 +payload_size=20971520 +payload_sha256=48b6fb8f1c2fec38d030604889d674722c4af237733c913b698400b59c9294b4 fail() { echo "APK_CURL_EQUIVALENCE_TEST_FAILED: $1" diff --git a/test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml b/test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml index 083a18ae75..0f2f6e1bab 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-aarch64.toml @@ -95,5 +95,5 @@ timeout = 1800 [host_http_server] bind = "127.0.0.1" port = 18381 -body_size = 1048576 +body_size = 20971520 body_byte = 97 diff --git a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml index 9ba29a505a..87ff1dbeb0 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-loongarch64.toml @@ -90,5 +90,5 @@ timeout = 1800 [host_http_server] bind = "127.0.0.1" port = 18383 -body_size = 1048576 +body_size = 20971520 body_byte = 97 diff --git a/test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml b/test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml index fe28b6bb9e..2d10372d93 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-riscv64.toml @@ -95,5 +95,5 @@ timeout = 1800 [host_http_server] bind = "127.0.0.1" port = 18382 -body_size = 1048576 +body_size = 20971520 body_byte = 97 diff --git a/test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml b/test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml index 37809ecf08..78f91c3841 100644 --- a/test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml +++ b/test-suit/starryos/qemu-smp1/system/qemu-x86_64.toml @@ -95,5 +95,5 @@ timeout = 1800 [host_http_server] bind = "127.0.0.1" port = 18380 -body_size = 1048576 +body_size = 20971520 body_byte = 97 From bbc2a29d7f07d217e34af0f900b0df0db3bf1743 Mon Sep 17 00:00:00 2001 From: szy Date: Wed, 24 Jun 2026 16:15:36 +0800 Subject: [PATCH 39/50] fix(loongarch): route eiointc through registered driver --- components/someboot/src/lib.rs | 2 +- .../somehal/src/arch/loongarch64/eiointc.rs | 112 +++++++++++------- 2 files changed, 68 insertions(+), 46 deletions(-) diff --git a/components/someboot/src/lib.rs b/components/someboot/src/lib.rs index 57e4a20fcc..9e1c4dc667 100644 --- a/components/someboot/src/lib.rs +++ b/components/someboot/src/lib.rs @@ -150,7 +150,7 @@ pub fn post_allocator() { arch::Arch::post_allocator(); } -/// Returns boot arguments captured from FDT or built into the image. +/// Returns boot arguments captured from FDT, UEFI load options, or built into the image. pub fn bootargs() -> Option<&'static str> { cmdline::cmdline() } diff --git a/platforms/somehal/src/arch/loongarch64/eiointc.rs b/platforms/somehal/src/arch/loongarch64/eiointc.rs index 37a3301173..db63db2b51 100644 --- a/platforms/somehal/src/arch/loongarch64/eiointc.rs +++ b/platforms/somehal/src/arch/loongarch64/eiointc.rs @@ -43,19 +43,21 @@ module_driver!( ); pub fn set_irq_enable(irq: usize, enable: bool) { - if enable { - enable_irq(irq, EIOINTC_VECTOR_COUNT); - } else { - disable_irq(irq, EIOINTC_VECTOR_COUNT); - } + with_eiointc("setting EIOINTC IRQ enable", |intc| { + if enable { + intc.enable_irq(irq); + } else { + intc.disable_irq(irq); + } + }); } pub fn claim_irq() -> Option { - claim_irq_from(EIOINTC_VECTOR_COUNT) + with_eiointc("claiming EIOINTC IRQ", |intc| intc.claim_irq()).flatten() } pub fn complete_irq(irq: usize) { - complete_irq_for(irq, EIOINTC_VECTOR_COUNT); + with_eiointc("completing EIOINTC IRQ", |intc| intc.complete_irq(irq)); } fn probe_eiointc_fdt(probe: ProbeFdt<'_>) -> Result<(), OnProbeError> { @@ -77,6 +79,26 @@ fn register_eiointc(dev: PlatformDevice) -> Result<(), OnProbeError> { Ok(()) } +fn with_eiointc(op: &str, f: impl FnOnce(&mut EioIntc) -> R) -> Option { + if !rdrive::is_initialized() { + return None; + } + + for intc in rdrive::get_list::() { + let Ok(intc) = intc.downcast::() else { + continue; + }; + let Ok(mut intc) = intc.try_lock() else { + warn!("failed to lock Loongson EIOINTC when {op}"); + return None; + }; + return Some(f(&mut intc)); + } + + warn!("Loongson EIOINTC is not registered when {op}"); + None +} + struct EioIntc { vectors: usize, } @@ -110,55 +132,55 @@ impl EioIntc { iocsr_write_w(EIOINTC_REG_BOUNCE + i * 4, u32::MAX); } } -} -fn enable_irq(irq: usize, vectors: usize) { - if !contains_irq(irq, vectors, "enable") { - return; - } + fn enable_irq(&mut self, irq: usize) { + if !self.contains_irq(irq, "enable") { + return; + } - let (offset, bit) = eiointc_reg_bit(irq); - for base in [EIOINTC_REG_ENABLE, EIOINTC_REG_BOUNCE] { - let addr = base + offset; - iocsr_write_d(addr, iocsr_read_d(addr) | bit); + let (offset, bit) = eiointc_reg_bit(irq); + for base in [EIOINTC_REG_ENABLE, EIOINTC_REG_BOUNCE] { + let addr = base + offset; + iocsr_write_d(addr, iocsr_read_d(addr) | bit); + } } -} -fn disable_irq(irq: usize, vectors: usize) { - if !contains_irq(irq, vectors, "disable") { - return; - } + fn disable_irq(&mut self, irq: usize) { + if !self.contains_irq(irq, "disable") { + return; + } - let (offset, bit) = eiointc_reg_bit(irq); - let addr = EIOINTC_REG_ENABLE + offset; - iocsr_write_d(addr, iocsr_read_d(addr) & !bit); -} + let (offset, bit) = eiointc_reg_bit(irq); + let addr = EIOINTC_REG_ENABLE + offset; + iocsr_write_d(addr, iocsr_read_d(addr) & !bit); + } -fn claim_irq_from(vectors: usize) -> Option { - for i in 0..(vectors / VEC_COUNT_PER_REG) { - let flags = iocsr_read_d(EIOINTC_REG_ISR + i * 8); - if flags != 0 { - return Some(flags.trailing_zeros() as usize + VEC_COUNT_PER_REG * i); + fn claim_irq(&mut self) -> Option { + for i in 0..(self.vectors / VEC_COUNT_PER_REG) { + let flags = iocsr_read_d(EIOINTC_REG_ISR + i * 8); + if flags != 0 { + return Some(flags.trailing_zeros() as usize + VEC_COUNT_PER_REG * i); + } } + None } - None -} -fn complete_irq_for(irq: usize, vectors: usize) { - if !contains_irq(irq, vectors, "complete") { - return; - } + fn complete_irq(&mut self, irq: usize) { + if !self.contains_irq(irq, "complete") { + return; + } - let (offset, bit) = eiointc_reg_bit(irq); - iocsr_write_d(EIOINTC_REG_ISR + offset, bit); -} + let (offset, bit) = eiointc_reg_bit(irq); + iocsr_write_d(EIOINTC_REG_ISR + offset, bit); + } -fn contains_irq(irq: usize, vectors: usize, op: &str) -> bool { - if irq < vectors { - true - } else { - warn!("skip {op} for out-of-range EIOINTC IRQ {irq}"); - false + fn contains_irq(&self, irq: usize, op: &str) -> bool { + if irq < self.vectors { + true + } else { + warn!("skip {op} for out-of-range EIOINTC IRQ {irq}"); + false + } } } From 820fdad2a2ea4643178976c9915724f0c330bc19 Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 25 Jun 2026 09:59:13 +0800 Subject: [PATCH 40/50] fix(axvisor): harden LoongArch guest IRQ lifecycle --- os/arceos/modules/axhal/src/lib.rs | 4 + os/axvisor/src/config.rs | 2 + os/axvisor/src/manager.rs | 60 ++++--- platforms/ax-plat/src/irq.rs | 9 ++ platforms/axplat-dyn/src/irq.rs | 28 +++- virtualization/axdevice/src/device.rs | 12 +- virtualization/axdevice/src/fw_cfg.rs | 142 +++++++++++++++-- virtualization/axdevice/src/lib.rs | 2 +- .../axdevice/src/loongarch_pch_pic.rs | 146 +++++++++++++++++- virtualization/axvm/src/manager.rs | 2 + virtualization/axvm/src/vm.rs | 26 +++- .../loongarch_vcpu/src/exception.rs | 66 +++++++- virtualization/loongarch_vcpu/src/lib.rs | 2 +- virtualization/loongarch_vcpu/src/vcpu.rs | 1 + 14 files changed, 446 insertions(+), 56 deletions(-) diff --git a/os/arceos/modules/axhal/src/lib.rs b/os/arceos/modules/axhal/src/lib.rs index e580291399..4401345d07 100644 --- a/os/arceos/modules/axhal/src/lib.rs +++ b/os/arceos/modules/axhal/src/lib.rs @@ -79,6 +79,10 @@ pub mod loongarch64_hv_irq { guest_vector, ); } + + pub fn unregister_guest_irq_routes(vm_id: usize) { + ax_plat::irq::unregister_loongarch_guest_irq_routes(vm_id); + } } #[cfg(feature = "paging")] diff --git a/os/axvisor/src/config.rs b/os/axvisor/src/config.rs index 74d2324292..a8b57f912e 100644 --- a/os/axvisor/src/config.rs +++ b/os/axvisor/src/config.rs @@ -221,6 +221,8 @@ pub fn init_guest_vm(raw_cfg: &str) -> AxResult { format!("VM[{vm_id}] already exists") )); } + #[cfg(target_arch = "loongarch64")] + crate::manager::register_loongarch_passthrough_irq_routes(vm_id); #[cfg(all( feature = "fs", diff --git a/os/axvisor/src/manager.rs b/os/axvisor/src/manager.rs index 7a3c13892f..f3642d4960 100644 --- a/os/axvisor/src/manager.rs +++ b/os/axvisor/src/manager.rs @@ -37,8 +37,6 @@ impl AxvmManager { /// Load and initialize the default VM set. pub fn init_default_vms(&self) { crate::config::init_guest_vms(); - #[cfg(target_arch = "loongarch64")] - init_loongarch_passthrough_irq_routes(); self.runtime.init_vms(); self.release_host_filesystem_for_guest_passthrough(); } @@ -70,6 +68,8 @@ impl AxvmManager { /// Remove a VM by ID. pub fn remove_vm(vm_id: VMId) -> Option { + #[cfg(target_arch = "loongarch64")] + unregister_loongarch_passthrough_irq_routes(vm_id); AxvmRuntime::remove_vm(vm_id) } @@ -238,42 +238,36 @@ fn inject_loongarch_platform_irq(vm_id: usize, vcpu_id: usize, vector: usize, ph } #[cfg(target_arch = "loongarch64")] -fn init_loongarch_passthrough_irq_routes() { - let mut matched = 0usize; - for vm in axvm::get_vm_list() { - let routes = crate::guest_platform::loongarch64::get_guest_irq_routes(vm.id()); - if !routes.is_empty() { - matched += 1; - let vcpu_id = 0usize; - info!( - "Registering {} LoongArch passthrough IRQ route(s) for VM[{}]", - routes.len(), - vm.id() - ); - for route in routes { - ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::register_guest_irq_route( - route.physical_irq, - vm.id(), - vcpu_id, - route.guest_vector, +pub(crate) fn register_loongarch_passthrough_irq_routes(vm_id: VMId) { + let routes = crate::guest_platform::loongarch64::get_guest_irq_routes(vm_id); + if routes.is_empty() { + if let Some(vm) = axvm::get_vm_by_id(vm_id) { + let passthrough = vm.with_config(|cfg| !cfg.pass_through_devices().is_empty()); + if passthrough { + warn!( + "VM[{vm_id}] has passthrough devices but no LoongArch guest IRQ route parsed" ); } - continue; - } - - let passthrough = vm.with_config(|cfg| !cfg.pass_through_devices().is_empty()); - if !passthrough { - continue; } + return; + } - matched += 1; - warn!( - "VM[{}] has passthrough devices but no LoongArch guest IRQ route parsed from DTB", - vm.id() + let vcpu_id = 0usize; + info!( + "Registering {} LoongArch passthrough IRQ route(s) for VM[{vm_id}]", + routes.len() + ); + for route in routes { + ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::register_guest_irq_route( + route.physical_irq, + vm_id, + vcpu_id, + route.guest_vector, ); } +} - if matched > 1 { - warn!("LoongArch passthrough IRQ routing matched {matched} VMs; check per-IRQ ownership"); - } +#[cfg(target_arch = "loongarch64")] +fn unregister_loongarch_passthrough_irq_routes(vm_id: VMId) { + ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::unregister_guest_irq_routes(vm_id); } diff --git a/platforms/ax-plat/src/irq.rs b/platforms/ax-plat/src/irq.rs index 0901e58399..325fd1f8b0 100644 --- a/platforms/ax-plat/src/irq.rs +++ b/platforms/ax-plat/src/irq.rs @@ -284,6 +284,9 @@ pub trait LoongArchHvIrqIf { vcpu_id: usize, guest_vector: usize, ); + + /// Removes all guest IRQ routes owned by one VM. + fn unregister_guest_irq_routes(vm_id: usize); } /// Registers the virtual interrupt injector used by LoongArch hypervisor builds. @@ -307,3 +310,9 @@ pub fn register_loongarch_guest_irq_route( guest_vector )); } + +/// Removes all LoongArch guest IRQ routes owned by one VM. +#[cfg(target_arch = "loongarch64")] +pub fn unregister_loongarch_guest_irq_routes(vm_id: usize) { + crate::__priv::call_interface!(LoongArchHvIrqIf::unregister_guest_irq_routes(vm_id)); +} diff --git a/platforms/axplat-dyn/src/irq.rs b/platforms/axplat-dyn/src/irq.rs index be2aa44908..1697df6494 100644 --- a/platforms/axplat-dyn/src/irq.rs +++ b/platforms/axplat-dyn/src/irq.rs @@ -120,9 +120,19 @@ impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { return; } + let target = (vm_id << IRQ_TARGET_VM_SHIFT) | vcpu_id; + let previous_target = LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); + if previous_target != IRQ_TARGET_NONE && previous_target != target { + warn!( + "LoongArch guest IRQ route conflict: physical_irq={} is already routed to encoded \ + target {:#x}, ignoring VM[{}] VCpu[{}]", + physical_irq, previous_target, vm_id, vcpu_id + ); + return; + } + + LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].store(target, Ordering::Release); LOONGARCH_GUEST_IRQ_ROUTES[physical_irq].store(guest_vector + 1, Ordering::Release); - LOONGARCH_GUEST_IRQ_TARGETS[physical_irq] - .store((vm_id << IRQ_TARGET_VM_SHIFT) | vcpu_id, Ordering::Release); somehal::irq::irq_set_enable(physical_irq.into(), true); debug!( "LoongArch dynamic guest IRQ route: physical_irq={}, target=VM[{}] VCpu[{}], \ @@ -130,6 +140,20 @@ impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { physical_irq, vm_id, vcpu_id, guest_vector ); } + + fn unregister_guest_irq_routes(vm_id: usize) { + for physical_irq in 0..LOONGARCH_MAX_IRQ_COUNT { + let target = LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); + if target == IRQ_TARGET_NONE || (target >> IRQ_TARGET_VM_SHIFT) != vm_id { + continue; + } + + LOONGARCH_GUEST_IRQ_ROUTES[physical_irq].store(IRQ_ROUTE_NONE, Ordering::Release); + LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].store(IRQ_TARGET_NONE, Ordering::Release); + somehal::irq::irq_set_enable(physical_irq.into(), false); + debug!("LoongArch dynamic guest IRQ route removed: physical_irq={physical_irq}"); + } + } } #[cfg(all(target_arch = "riscv64", feature = "hv"))] diff --git a/virtualization/axdevice/src/device.rs b/virtualization/axdevice/src/device.rs index 05517ed066..66f7aebb4a 100644 --- a/virtualization/axdevice/src/device.rs +++ b/virtualization/axdevice/src/device.rs @@ -35,12 +35,12 @@ use riscv_vplic::VPlicGlobal; #[cfg(target_arch = "x86_64")] use x86_vlapic::{EmulatedIoApic, EmulatedPit, EmulatedSerialPort, IoApicInterrupt}; -#[cfg(target_arch = "loongarch64")] -use crate::LoongArchPchPic; use crate::{ AxVmDeviceConfig, DeviceBuildContext, DeviceBundle, DeviceFactoryRegistry, FwCfg, PollableDeviceOps, range_alloc::RangeAllocator, }; +#[cfg(target_arch = "loongarch64")] +use crate::{LoongArchPchPic, PchPicOutputEvent}; #[inline] #[allow(dead_code)] @@ -990,6 +990,14 @@ impl AxVmDevices { .map(|pch_pic| pch_pic.set_irq_level(irq, true)) } + /// Drains LoongArch PCH-PIC output-line events generated by MMIO writes. + #[cfg(target_arch = "loongarch64")] + pub fn drain_loongarch_pch_pic_events(&self, f: impl FnMut(PchPicOutputEvent)) { + if let Some(pch_pic) = &self.loongarch_pch_pic { + pch_pic.drain_output_events(f); + } + } + // ─── Find helpers ─────────────────────────────────────────────── /// Find specific MMIO device by ipa. diff --git a/virtualization/axdevice/src/fw_cfg.rs b/virtualization/axdevice/src/fw_cfg.rs index 75824f3876..ce4b2da821 100644 --- a/virtualization/axdevice/src/fw_cfg.rs +++ b/virtualization/axdevice/src/fw_cfg.rs @@ -1,6 +1,6 @@ use alloc::{format, vec, vec::Vec}; -use ax_errno::{AxResult, ax_err}; +use ax_errno::{AxResult, ax_err, ax_err_type}; use ax_kspin::SpinNoIrq as Mutex; use axdevice_base::{AccessWidth, BaseDeviceOps, EmuDeviceType}; use axvm_types::{GuestPhysAddr, GuestPhysAddrRange}; @@ -58,6 +58,7 @@ const FW_CFG_DMA_CTL_SKIP: u32 = 0x04; const FW_CFG_DMA_CTL_SELECT: u32 = 0x08; const FW_CFG_DMA_CTL_WRITE: u32 = 0x10; const FW_CFG_DMA_DESC_SIZE: usize = 16; +const FW_CFG_DMA_SCRATCH_SIZE: usize = 4096; #[derive(Clone, Copy, Debug)] pub struct FwCfgRamRegion { @@ -472,6 +473,8 @@ impl FwCfg { R: FnMut(GuestPhysAddr, &mut [u8]) -> AxResult, W: FnMut(GuestPhysAddr, &[u8]) -> AxResult, { + validate_dma_buffer(buffer_addr, length)?; + let mut state = self.state.lock(); if control & FW_CFG_DMA_CTL_SELECT != 0 { state.selected = (control >> 16) as u16; @@ -494,22 +497,15 @@ impl FwCfg { ); let entry = self.selected_bytes(state.selected); let data = entry.as_slice(); - let start = state.offset.min(data.len()); - let end = start.saturating_add(length).min(data.len()); - let mut out = Vec::with_capacity(length); - out.extend_from_slice(&data[start..end]); - out.resize(length, 0); + let start = state.offset; state.offset = state.offset.saturating_add(length); drop(state); - write_guest(buffer_addr, &out) + dma_read_entry(data, start, length, buffer_addr, write_guest) } FW_CFG_DMA_CTL_WRITE => { - let mut ignored = vec![0; length]; - if length != 0 { - read_guest(buffer_addr, &mut ignored)?; - } state.offset = state.offset.saturating_add(length); - Ok(()) + drop(state); + dma_discard_guest_write(length, buffer_addr, read_guest) } _ => { warn!("invalid fw_cfg DMA control {:#x}", control); @@ -519,6 +515,79 @@ impl FwCfg { } } +fn validate_dma_buffer(buffer_addr: GuestPhysAddr, length: usize) -> AxResult { + buffer_addr + .as_usize() + .checked_add(length) + .ok_or_else(|| ax_err_type!(InvalidInput, "fw_cfg DMA buffer address overflow"))?; + Ok(()) +} + +fn dma_read_entry( + data: &[u8], + start: usize, + length: usize, + buffer_addr: GuestPhysAddr, + write_guest: &mut W, +) -> AxResult +where + W: FnMut(GuestPhysAddr, &[u8]) -> AxResult, +{ + let mut remaining = length; + let mut guest_offset = 0usize; + let mut data_offset = start.min(data.len()); + let zeroes = [0u8; FW_CFG_DMA_SCRATCH_SIZE]; + + while remaining != 0 { + let chunk_len = remaining.min(FW_CFG_DMA_SCRATCH_SIZE); + let guest_addr = add_guest_offset(buffer_addr, guest_offset)?; + let available = data.len().saturating_sub(data_offset).min(chunk_len); + if available == chunk_len { + write_guest(guest_addr, &data[data_offset..data_offset + chunk_len])?; + } else { + if available != 0 { + write_guest(guest_addr, &data[data_offset..data_offset + available])?; + } + let zero_addr = add_guest_offset(buffer_addr, guest_offset + available)?; + write_guest(zero_addr, &zeroes[..chunk_len - available])?; + } + + remaining -= chunk_len; + guest_offset += chunk_len; + data_offset = data_offset.saturating_add(chunk_len); + } + + Ok(()) +} + +fn dma_discard_guest_write( + length: usize, + buffer_addr: GuestPhysAddr, + read_guest: &mut R, +) -> AxResult +where + R: FnMut(GuestPhysAddr, &mut [u8]) -> AxResult, +{ + let mut scratch = [0u8; FW_CFG_DMA_SCRATCH_SIZE]; + let mut remaining = length; + let mut guest_offset = 0usize; + while remaining != 0 { + let chunk_len = remaining.min(scratch.len()); + let guest_addr = add_guest_offset(buffer_addr, guest_offset)?; + read_guest(guest_addr, &mut scratch[..chunk_len])?; + remaining -= chunk_len; + guest_offset += chunk_len; + } + Ok(()) +} + +fn add_guest_offset(base: GuestPhysAddr, offset: usize) -> AxResult { + base.as_usize() + .checked_add(offset) + .map(GuestPhysAddr::from_usize) + .ok_or_else(|| ax_err_type!(InvalidInput, "fw_cfg DMA buffer address overflow")) +} + struct FwCfgFile<'a> { name: &'a str, selector: u16, @@ -1354,3 +1423,52 @@ impl BaseDeviceOps for FwCfg { Ok(()) } } + +#[cfg(test)] +mod tests { + use core::cell::Cell; + + use super::*; + + #[test] + fn dma_read_uses_bounded_chunks_for_large_guest_length() { + let writes = Cell::new(0usize); + dma_read_entry( + b"abc", + 0, + FW_CFG_DMA_SCRATCH_SIZE * 2 + 17, + GuestPhysAddr::from_usize(0x8000), + &mut |_addr, buffer| { + assert!(buffer.len() <= FW_CFG_DMA_SCRATCH_SIZE); + writes.set(writes.get() + 1); + Ok(()) + }, + ) + .unwrap(); + + assert!(writes.get() > 1); + } + + #[test] + fn dma_write_discard_uses_bounded_chunks_for_large_guest_length() { + let reads = Cell::new(0usize); + dma_discard_guest_write( + FW_CFG_DMA_SCRATCH_SIZE * 2 + 17, + GuestPhysAddr::from_usize(0x8000), + &mut |_addr, buffer| { + assert!(buffer.len() <= FW_CFG_DMA_SCRATCH_SIZE); + buffer.fill(0xaa); + reads.set(reads.get() + 1); + Ok(()) + }, + ) + .unwrap(); + + assert!(reads.get() > 1); + } + + #[test] + fn dma_rejects_buffer_address_overflow() { + assert!(validate_dma_buffer(GuestPhysAddr::from_usize(usize::MAX), 2).is_err()); + } +} diff --git a/virtualization/axdevice/src/lib.rs b/virtualization/axdevice/src/lib.rs index c6148552e8..0415300256 100644 --- a/virtualization/axdevice/src/lib.rs +++ b/virtualization/axdevice/src/lib.rs @@ -54,7 +54,7 @@ pub use fw_cfg::{ FwCfgSerialConfig, }; #[cfg(target_arch = "loongarch64")] -pub use loongarch_pch_pic::LoongArchPchPic; +pub use loongarch_pch_pic::{LoongArchPchPic, PchPicOutputEvent}; pub use registration::{DeviceBundle, DeviceRegistration, PollableDeviceOps}; #[cfg(target_arch = "x86_64")] pub use x86_vlapic::IoApicInterrupt; diff --git a/virtualization/axdevice/src/loongarch_pch_pic.rs b/virtualization/axdevice/src/loongarch_pch_pic.rs index 25af2f6262..6c02dc5f90 100644 --- a/virtualization/axdevice/src/loongarch_pch_pic.rs +++ b/virtualization/axdevice/src/loongarch_pch_pic.rs @@ -33,6 +33,7 @@ const PCH_PIC_INT_ID_VER: usize = 0x1; const PCH_PIC_IO_LOG_LIMIT: usize = 256; const PCH_PIC_IRQ_LOG_LIMIT: usize = 64; const PCH_PIC_LEVEL_LOG_LIMIT: usize = 64; +const PCH_PIC_OUTPUT_QUEUE_CAPACITY: usize = 16; static PCH_PIC_IO_LOGS: AtomicUsize = AtomicUsize::new(0); static PCH_PIC_IRQ_LOGS: AtomicUsize = AtomicUsize::new(0); @@ -51,6 +52,9 @@ struct PchPicState { auto_ctrl1: u64, route_entry: [u8; PCH_PIC_IRQ_COUNT], htmsi_vector: [u8; PCH_PIC_IRQ_COUNT], + output_events: [Option; PCH_PIC_OUTPUT_QUEUE_CAPACITY], + output_head: usize, + output_len: usize, } impl Default for PchPicState { @@ -67,6 +71,9 @@ impl Default for PchPicState { auto_ctrl1: 0, route_entry: [0; PCH_PIC_IRQ_COUNT], htmsi_vector: [0; PCH_PIC_IRQ_COUNT], + output_events: [None; PCH_PIC_OUTPUT_QUEUE_CAPACITY], + output_head: 0, + output_len: 0, }; for irq in 0..PCH_PIC_IRQ_COUNT { state.route_entry[irq] = 1; @@ -76,6 +83,12 @@ impl Default for PchPicState { } } +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub struct PchPicOutputEvent { + pub vector: usize, + pub asserted: bool, +} + /// Minimal LS7A PCH-PIC model for LoongArch QEMU virt guests. /// /// Linux configures this irqchip through ACPI even when the backing PCI devices @@ -126,6 +139,20 @@ impl LoongArchPchPic { update_irq(&mut state, 1u64 << irq, true) } + + /// Drains output-line events generated by MMIO register writes. + pub fn drain_output_events(&self, mut f: impl FnMut(PchPicOutputEvent)) { + loop { + let event = { + let mut state = self.state.lock(); + pop_output_event(&mut state) + }; + match event { + Some(event) => f(event), + None => return, + } + } + } } impl BaseDeviceOps for LoongArchPchPic { @@ -329,9 +356,11 @@ fn reg8_offset(offset: usize) -> Option { } fn clear_irq(state: &mut PchPicState, mask: u64) { + let active = state.intisr & mask; state.intirr &= !mask; state.last_intirr &= !mask; state.intisr &= !mask; + queue_events_for_mask(state, active, false); } fn update_int_mask(state: &mut PchPicState, val: u32, high: bool) { @@ -346,7 +375,15 @@ fn update_int_mask(state: &mut PchPicState, val: u32, high: bool) { } else { newly_unmasked as u64 }; - let _ = update_irq(state, mask, true); + if let Some(vector) = update_irq(state, mask, true) { + push_output_event( + state, + PchPicOutputEvent { + vector, + asserted: true, + }, + ); + } } let newly_masked = !old_part & val; @@ -356,10 +393,56 @@ fn update_int_mask(state: &mut PchPicState, val: u32, high: bool) { } else { newly_masked as u64 }; - let _ = update_irq(state, mask, false); + if let Some(vector) = update_irq(state, mask, false) { + push_output_event( + state, + PchPicOutputEvent { + vector, + asserted: false, + }, + ); + } } } +fn queue_events_for_mask(state: &mut PchPicState, mut mask: u64, asserted: bool) { + while mask != 0 { + let irq = mask.trailing_zeros() as usize; + push_output_event( + state, + PchPicOutputEvent { + vector: state.htmsi_vector[irq] as usize, + asserted, + }, + ); + mask &= !(1u64 << irq); + } +} + +fn push_output_event(state: &mut PchPicState, event: PchPicOutputEvent) { + if state.output_len == PCH_PIC_OUTPUT_QUEUE_CAPACITY { + warn!( + "LoongArch PCH-PIC output event queue full, dropping event {:?}", + event + ); + return; + } + let index = (state.output_head + state.output_len) % PCH_PIC_OUTPUT_QUEUE_CAPACITY; + state.output_events[index] = Some(event); + state.output_len += 1; +} + +fn pop_output_event(state: &mut PchPicState) -> Option { + if state.output_len == 0 { + return None; + } + + let event = state.output_events[state.output_head].take(); + state.output_head = (state.output_head + 1) % PCH_PIC_OUTPUT_QUEUE_CAPACITY; + state.output_len -= 1; + event +} + fn replace_u32(old: u64, val: u32, high: bool) -> u64 { if high { (old & 0x0000_0000_ffff_ffff) | ((val as u64) << 32) @@ -405,3 +488,62 @@ fn log_pch_pic_irq(state: &PchPicState, op: &str, irq: usize, level: bool, mask: ); } } + +#[cfg(test)] +mod tests { + use alloc::vec::Vec; + + use super::*; + + #[test] + fn unmask_latched_irq_emits_assert_event() { + let pic = LoongArchPchPic::new(GuestPhysAddr::from_usize(0x1000), 0x1000); + assert_eq!(pic.set_irq_level(5, true), None); + + pic.handle_write( + GuestPhysAddr::from_usize(0x1000 + PCH_PIC_INT_MASK_LO), + AccessWidth::Dword, + !(1u32 << 5) as usize, + ) + .unwrap(); + + let mut events = Vec::new(); + pic.drain_output_events(|event| events.push(event)); + assert_eq!( + events, + vec![PchPicOutputEvent { + vector: 5, + asserted: true + }] + ); + } + + #[test] + fn clear_asserted_irq_emits_deassert_event() { + let pic = LoongArchPchPic::new(GuestPhysAddr::from_usize(0x1000), 0x1000); + pic.handle_write( + GuestPhysAddr::from_usize(0x1000 + PCH_PIC_INT_MASK_LO), + AccessWidth::Dword, + !(1u32 << 5) as usize, + ) + .unwrap(); + assert_eq!(pic.set_irq_level(5, true), Some(5)); + + pic.handle_write( + GuestPhysAddr::from_usize(0x1000 + PCH_PIC_INT_CLEAR_LO), + AccessWidth::Dword, + (1u32 << 5) as usize, + ) + .unwrap(); + + let mut events = Vec::new(); + pic.drain_output_events(|event| events.push(event)); + assert_eq!( + events, + vec![PchPicOutputEvent { + vector: 5, + asserted: false + }] + ); + } +} diff --git a/virtualization/axvm/src/manager.rs b/virtualization/axvm/src/manager.rs index ba2b961c1d..88d0251e35 100644 --- a/virtualization/axvm/src/manager.rs +++ b/virtualization/axvm/src/manager.rs @@ -41,6 +41,8 @@ pub(crate) fn push_existing_vm(vm: AxVMRef) -> bool { pub(crate) fn remove_existing_vm(vm_id: VMId) -> Option { let vm = VM_REGISTRY.lock().remove(&vm_id)?; crate::runtime::vcpus::cleanup_vm_vcpus(vm_id); + #[cfg(target_arch = "loongarch64")] + loongarch_vcpu::clear_guest_iocsr_vm(vm_id); Some(vm) } diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index 0914f80ef2..55acf70105 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -880,7 +880,31 @@ impl AxVM { return Ok(()); } - self.get_devices().handle_mmio_write(addr, width, data) + self.get_devices().handle_mmio_write(addr, width, data)?; + #[cfg(target_arch = "loongarch64")] + self.drain_loongarch_pch_pic_events(); + Ok(()) + } + + #[cfg(target_arch = "loongarch64")] + fn drain_loongarch_pch_pic_events(&self) { + self.get_devices().drain_loongarch_pch_pic_events(|event| { + if !event.asserted { + trace!( + "LoongArch VM[{}] PCH-PIC deassert event for EIOINTC vector {}", + self.id(), + event.vector + ); + return; + } + if let Err(err) = crate::inject_vm_vcpu_interrupt(self.id(), 0, event.vector) { + warn!( + "failed to inject LoongArch VM[{}] PCH-PIC output vector {}: {err:?}", + self.id(), + event.vector + ); + } + }); } fn handle_nested_page_fault(&self, addr: GuestPhysAddr, access_flags: MappingFlags) -> bool { diff --git a/virtualization/loongarch_vcpu/src/exception.rs b/virtualization/loongarch_vcpu/src/exception.rs index 944f739be5..21d5b545cd 100644 --- a/virtualization/loongarch_vcpu/src/exception.rs +++ b/virtualization/loongarch_vcpu/src/exception.rs @@ -1,11 +1,11 @@ -use alloc::boxed::Box; +use alloc::{boxed::Box, format}; use core::{ mem::offset_of, sync::atomic::{AtomicUsize, Ordering}, time::Duration, }; -use ax_errno::AxResult; +use ax_errno::{AxResult, ax_err}; use axvcpu::{AxVCpuExitReason, GuestPhysAddr, MappingFlags, VCpuId, VMId}; use crate::{context_frame::LoongArchContextFrame, host}; @@ -283,6 +283,20 @@ fn iocsr_vcpu_index(vm_id: VMId, vcpu_id: VCpuId) -> Option { } } +pub(crate) fn validate_guest_iocsr_capacity(vm_id: VMId, vcpu_id: VCpuId) -> AxResult { + if iocsr_vcpu_index(vm_id, vcpu_id).is_some() { + Ok(()) + } else { + ax_err!( + InvalidInput, + format!( + "LoongArch IOCSR state capacity exceeded: VM[{vm_id}] VCpu[{vcpu_id}], max VM \ + count {MAX_IOCSR_VMS}, max vCPU count {MAX_IOCSR_CPUS}" + ) + ) + } +} + fn iocsr_mail_buf_index(vcpu_index: usize, addr: usize) -> Option { if !(LOONGARCH_IOCSR_MAIL_BUF0..=LOONGARCH_IOCSR_MAIL_BUF3).contains(&addr) || !(addr - LOONGARCH_IOCSR_MAIL_BUF0).is_multiple_of(8) @@ -472,9 +486,14 @@ fn update_guest_eiointc_irq(ctx: &mut LoongArchContextFrame, vcpu_index: usize) pub(crate) fn init_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId) { let Some(vcpu_index) = iocsr_vcpu_index(vm_id, vcpu_id) else { + log::warn!( + "LoongArch guest IOCSR init skipped: VM[{vm_id}] VCpu[{vcpu_id}] exceeds capacity" + ); return; }; + clear_guest_iocsr_vcpu(vcpu_index); + for word in 0..EIOINTC_NODEMAP_WORDS { let value = ((1usize << (word * 2 + 1)) << 16) | (1usize << (word * 2)); EIOINTC_NODEMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_NODEMAP_WORDS, word)] @@ -496,6 +515,49 @@ pub(crate) fn init_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId) { } } +pub fn clear_guest_iocsr_vm(vm_id: VMId) { + if vm_id >= MAX_IOCSR_VMS { + return; + } + + for vcpu_id in 0..MAX_IOCSR_CPUS { + clear_guest_iocsr_vcpu(vm_id * MAX_IOCSR_CPUS + vcpu_id); + } +} + +fn clear_guest_iocsr_vcpu(vcpu_index: usize) { + IOCSR_IPI_STATUS_WORDS[vcpu_index].store(0, Ordering::Release); + IOCSR_IPI_ENABLE_WORDS[vcpu_index].store(0, Ordering::Release); + EIOINTC_VIRT_CONFIG_WORDS[vcpu_index].store(0, Ordering::Release); + + for word in 0..IOCSR_MAIL_BUF_COUNT { + IOCSR_MAIL_BUF_WORDS[vcpu_index * IOCSR_MAIL_BUF_COUNT + word].store(0, Ordering::Release); + } + for word in 0..EIOINTC_ISR_REG_COUNT { + EIOINTC_ISR_WORDS[eiointc_isr_index(vcpu_index, word)].store(0, Ordering::Release); + } + for word in 0..EIOINTC_NODEMAP_WORDS { + EIOINTC_NODEMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_NODEMAP_WORDS, word)] + .store(0, Ordering::Release); + } + for word in 0..EIOINTC_IPMAP_WORDS { + EIOINTC_IPMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_IPMAP_WORDS, word)] + .store(0, Ordering::Release); + } + for word in 0..EIOINTC_ENABLE_WORDS_PER_VCPU { + EIOINTC_ENABLE_WORDS[eiointc_word_index(vcpu_index, EIOINTC_ENABLE_WORDS_PER_VCPU, word)] + .store(0, Ordering::Release); + } + for word in 0..EIOINTC_BOUNCE_WORDS { + EIOINTC_BOUNCE_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_BOUNCE_WORDS, word)] + .store(0, Ordering::Release); + } + for word in 0..EIOINTC_COREMAP_WORDS { + EIOINTC_COREMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_COREMAP_WORDS, word)] + .store(0, Ordering::Release); + } +} + fn iocsr_access_len_from_ty(ty: usize) -> usize { match ty { 0 | 4 => 1, diff --git a/virtualization/loongarch_vcpu/src/lib.rs b/virtualization/loongarch_vcpu/src/lib.rs index e822a5d75f..44cf186417 100644 --- a/virtualization/loongarch_vcpu/src/lib.rs +++ b/virtualization/loongarch_vcpu/src/lib.rs @@ -13,7 +13,7 @@ mod vcpu; pub use self::{ context_frame::LoongArchContextFrame, - exception::{TrapKind, handle_exception_irq, handle_exception_sync}, + exception::{TrapKind, clear_guest_iocsr_vm, handle_exception_irq, handle_exception_sync}, pcpu::LoongArchPerCpu, registers::inject_interrupt, vcpu::{LoongArchVCpu, LoongArchVCpuCreateConfig, LoongArchVCpuSetupConfig}, diff --git a/virtualization/loongarch_vcpu/src/vcpu.rs b/virtualization/loongarch_vcpu/src/vcpu.rs index 85e543eed4..d2b4c661c6 100644 --- a/virtualization/loongarch_vcpu/src/vcpu.rs +++ b/virtualization/loongarch_vcpu/src/vcpu.rs @@ -139,6 +139,7 @@ impl AxArchVCpu for LoongArchVCpu { type SetupConfig = LoongArchVCpuSetupConfig; fn new(_vm_id: usize, _vcpu_id: usize, config: Self::CreateConfig) -> AxResult { + crate::exception::validate_guest_iocsr_capacity(_vm_id, _vcpu_id)?; let mut ctx = LoongArchContextFrame::default(); if config.firmware_boot { // Firmware reset entry keeps the initial argument registers in their From 5f948aae6597e5deba608e5c9ead25c6c69b17d0 Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 25 Jun 2026 10:31:42 +0800 Subject: [PATCH 41/50] fix(loongarch-vcpu): move IOCSR state into VM lifecycle --- virtualization/axvm/src/manager.rs | 2 - virtualization/axvm/src/vm.rs | 11 + .../loongarch_vcpu/src/exception.rs | 559 +++++++++--------- virtualization/loongarch_vcpu/src/lib.rs | 5 +- virtualization/loongarch_vcpu/src/vcpu.rs | 30 +- 5 files changed, 301 insertions(+), 306 deletions(-) diff --git a/virtualization/axvm/src/manager.rs b/virtualization/axvm/src/manager.rs index 88d0251e35..ba2b961c1d 100644 --- a/virtualization/axvm/src/manager.rs +++ b/virtualization/axvm/src/manager.rs @@ -41,8 +41,6 @@ pub(crate) fn push_existing_vm(vm: AxVMRef) -> bool { pub(crate) fn remove_existing_vm(vm_id: VMId) -> Option { let vm = VM_REGISTRY.lock().remove(&vm_id)?; crate::runtime::vcpus::cleanup_vm_vcpus(vm_id); - #[cfg(target_arch = "loongarch64")] - loongarch_vcpu::clear_guest_iocsr_vm(vm_id); Some(vm) } diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index 55acf70105..c44049d973 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -271,6 +271,15 @@ impl AxVM { let dtb_addr = inner_mut.config.image_config().dtb_load_gpa; let vcpu_id_pcpu_sets = inner_mut.config.phys_cpu_ls.get_vcpu_affinities_pcpu_ids(); + #[cfg(target_arch = "loongarch64")] + let loongarch_iocsr_state = { + let vcpu_state_count = vcpu_id_pcpu_sets + .iter() + .map(|(vcpu_id, ..)| *vcpu_id) + .max() + .map_or(0, |vcpu_id| vcpu_id + 1); + loongarch_vcpu::LoongArchIocsrState::new(vcpu_state_count)? + }; debug!("dtb_load_gpa: {dtb_addr:?}"); debug!("id: {}, VCpuIdPCpuSets: {vcpu_id_pcpu_sets:#x?}", self.id()); @@ -293,6 +302,8 @@ impl AxVM { dtb_addr: dtb_addr.unwrap_or_default().as_usize(), boot_args: inner_mut.config.cpu_config.boot_args, boot_stack_top: inner_mut.config.cpu_config.boot_stack_top, + firmware_boot: inner_mut.config.cpu_config.firmware_boot, + iocsr_state: loongarch_iocsr_state.clone(), }; // FIXME: VCpu is neither `Send` nor `Sync` by design, check whether diff --git a/virtualization/loongarch_vcpu/src/exception.rs b/virtualization/loongarch_vcpu/src/exception.rs index 21d5b545cd..1952689bb5 100644 --- a/virtualization/loongarch_vcpu/src/exception.rs +++ b/virtualization/loongarch_vcpu/src/exception.rs @@ -1,11 +1,11 @@ -use alloc::{boxed::Box, format}; +use alloc::{boxed::Box, sync::Arc}; use core::{ mem::offset_of, sync::atomic::{AtomicUsize, Ordering}, time::Duration, }; -use ax_errno::{AxResult, ax_err}; +use ax_errno::AxResult; use axvcpu::{AxVCpuExitReason, GuestPhysAddr, MappingFlags, VCpuId, VMId}; use crate::{context_frame::LoongArchContextFrame, host}; @@ -113,8 +113,6 @@ const EIOINTC_COREMAP_BASE: usize = 0x1c00; const EIOINTC_COREMAP_END: usize = 0x1d00; const EIOINTC_GUEST_OWNED_BASE: usize = 0x1400; const EIOINTC_GUEST_OWNED_END: usize = 0x2000; -const MAX_IOCSR_VMS: usize = 16; -const MAX_IOCSR_CPUS: usize = 16; const LOONGARCH_IOCSR_IPI_STATUS: usize = 0x1000; const LOONGARCH_IOCSR_IPI_EN: usize = 0x1004; const LOONGARCH_IOCSR_IPI_SET: usize = 0x1008; @@ -146,31 +144,6 @@ const EXTIOI_HAS_INT_ENCODE: usize = 1 << 2; const EXTIOI_HAS_CPU_ENCODE: usize = 1 << 3; const EXTIOI_ENABLE_CPU_ENCODE: usize = 1 << 3; -static IOCSR_IPI_STATUS_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS]; -static IOCSR_IPI_ENABLE_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS]; -static IOCSR_MAIL_BUF_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * IOCSR_MAIL_BUF_COUNT] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * IOCSR_MAIL_BUF_COUNT]; -static EIOINTC_ISR_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_ISR_REG_COUNT] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_ISR_REG_COUNT]; -static EIOINTC_NODEMAP_WORDS_STORAGE: [AtomicUsize; - MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_NODEMAP_WORDS] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_NODEMAP_WORDS]; -static EIOINTC_IPMAP_WORDS_STORAGE: [AtomicUsize; - MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_IPMAP_WORDS] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_IPMAP_WORDS]; -static EIOINTC_ENABLE_WORDS: [AtomicUsize; - MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_ENABLE_WORDS_PER_VCPU] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_ENABLE_WORDS_PER_VCPU]; -static EIOINTC_BOUNCE_WORDS_STORAGE: [AtomicUsize; - MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_BOUNCE_WORDS] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_BOUNCE_WORDS]; -static EIOINTC_COREMAP_WORDS_STORAGE: [AtomicUsize; - MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_COREMAP_WORDS] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS * EIOINTC_COREMAP_WORDS]; -static EIOINTC_VIRT_CONFIG_WORDS: [AtomicUsize; MAX_IOCSR_VMS * MAX_IOCSR_CPUS] = - [const { AtomicUsize::new(0) }; MAX_IOCSR_VMS * MAX_IOCSR_CPUS]; static NESTED_FAULT_LOGS: AtomicUsize = AtomicUsize::new(0); static SYNC_EXIT_LOGS: AtomicUsize = AtomicUsize::new(0); static IOCSR_EXIT_LOGS: AtomicUsize = AtomicUsize::new(0); @@ -180,6 +153,94 @@ static TARGET_IOCSR_LOGS: AtomicUsize = AtomicUsize::new(0); static IDLE_EXIT_LOGS: AtomicUsize = AtomicUsize::new(0); static GUEST_TIMER_LOGS: AtomicUsize = AtomicUsize::new(0); +pub type LoongArchIocsrStateRef = Arc; + +#[derive(Debug)] +pub struct LoongArchIocsrState { + vcpus: Box<[LoongArchVcpuIocsrState]>, +} + +impl LoongArchIocsrState { + pub fn new(vcpu_count: usize) -> AxResult { + let mut vcpus = alloc::vec::Vec::with_capacity(vcpu_count); + for _ in 0..vcpu_count { + vcpus.push(LoongArchVcpuIocsrState::new()); + } + Ok(Arc::new(Self { + vcpus: vcpus.into_boxed_slice(), + })) + } + + fn vcpu(&self, vcpu_id: VCpuId) -> Option<&LoongArchVcpuIocsrState> { + self.vcpus.get(vcpu_id) + } + + pub fn reset_vcpu(&self, vcpu_id: VCpuId) { + if let Some(vcpu) = self.vcpu(vcpu_id) { + vcpu.reset(); + } + } +} + +#[derive(Debug)] +struct LoongArchVcpuIocsrState { + ipi_status: AtomicUsize, + ipi_enable: AtomicUsize, + mail_buf: [AtomicUsize; IOCSR_MAIL_BUF_COUNT], + eiointc_isr: [AtomicUsize; EIOINTC_ISR_REG_COUNT], + eiointc_nodemap: [AtomicUsize; EIOINTC_NODEMAP_WORDS], + eiointc_ipmap: [AtomicUsize; EIOINTC_IPMAP_WORDS], + eiointc_enable: [AtomicUsize; EIOINTC_ENABLE_WORDS_PER_VCPU], + eiointc_bounce: [AtomicUsize; EIOINTC_BOUNCE_WORDS], + eiointc_coremap: [AtomicUsize; EIOINTC_COREMAP_WORDS], + eiointc_virt_config: AtomicUsize, +} + +impl LoongArchVcpuIocsrState { + const fn new() -> Self { + Self { + ipi_status: AtomicUsize::new(0), + ipi_enable: AtomicUsize::new(0), + mail_buf: [const { AtomicUsize::new(0) }; IOCSR_MAIL_BUF_COUNT], + eiointc_isr: [const { AtomicUsize::new(0) }; EIOINTC_ISR_REG_COUNT], + eiointc_nodemap: [const { AtomicUsize::new(0) }; EIOINTC_NODEMAP_WORDS], + eiointc_ipmap: [const { AtomicUsize::new(0) }; EIOINTC_IPMAP_WORDS], + eiointc_enable: [const { AtomicUsize::new(0) }; EIOINTC_ENABLE_WORDS_PER_VCPU], + eiointc_bounce: [const { AtomicUsize::new(0) }; EIOINTC_BOUNCE_WORDS], + eiointc_coremap: [const { AtomicUsize::new(0) }; EIOINTC_COREMAP_WORDS], + eiointc_virt_config: AtomicUsize::new(0), + } + } + + fn reset(&self) { + self.ipi_status.store(0, Ordering::Release); + self.ipi_enable.store(0, Ordering::Release); + self.eiointc_virt_config.store(0, Ordering::Release); + + for slot in &self.mail_buf { + slot.store(0, Ordering::Release); + } + for slot in &self.eiointc_isr { + slot.store(0, Ordering::Release); + } + for slot in &self.eiointc_nodemap { + slot.store(0, Ordering::Release); + } + for slot in &self.eiointc_ipmap { + slot.store(0, Ordering::Release); + } + for slot in &self.eiointc_enable { + slot.store(0, Ordering::Release); + } + for slot in &self.eiointc_bounce { + slot.store(0, Ordering::Release); + } + for slot in &self.eiointc_coremap { + slot.store(0, Ordering::Release); + } + } +} + #[repr(u8)] #[derive(Debug, Clone, Copy, PartialEq, Eq)] pub enum TrapKind { @@ -275,63 +336,26 @@ fn host_eiointc_has_pending() -> bool { false } -fn iocsr_vcpu_index(vm_id: VMId, vcpu_id: VCpuId) -> Option { - if vm_id < MAX_IOCSR_VMS && vcpu_id < MAX_IOCSR_CPUS { - Some(vm_id * MAX_IOCSR_CPUS + vcpu_id) - } else { - None - } -} - -pub(crate) fn validate_guest_iocsr_capacity(vm_id: VMId, vcpu_id: VCpuId) -> AxResult { - if iocsr_vcpu_index(vm_id, vcpu_id).is_some() { - Ok(()) - } else { - ax_err!( - InvalidInput, - format!( - "LoongArch IOCSR state capacity exceeded: VM[{vm_id}] VCpu[{vcpu_id}], max VM \ - count {MAX_IOCSR_VMS}, max vCPU count {MAX_IOCSR_CPUS}" - ) - ) - } -} - -fn iocsr_mail_buf_index(vcpu_index: usize, addr: usize) -> Option { +fn iocsr_mail_buf_index(addr: usize) -> Option { if !(LOONGARCH_IOCSR_MAIL_BUF0..=LOONGARCH_IOCSR_MAIL_BUF3).contains(&addr) || !(addr - LOONGARCH_IOCSR_MAIL_BUF0).is_multiple_of(8) { return None; } - Some(vcpu_index * IOCSR_MAIL_BUF_COUNT + (addr - LOONGARCH_IOCSR_MAIL_BUF0) / 8) -} - -fn eiointc_isr_index(vcpu_index: usize, reg: usize) -> usize { - vcpu_index * EIOINTC_ISR_REG_COUNT + reg + Some((addr - LOONGARCH_IOCSR_MAIL_BUF0) / 8) } -fn eiointc_word_index(vcpu_index: usize, words_per_vcpu: usize, word: usize) -> usize { - vcpu_index * words_per_vcpu + word -} - -fn read_atomic_u32_slots( - slots: &[AtomicUsize], - vcpu_index: usize, - words_per_vcpu: usize, - addr: usize, - base: usize, - len: usize, -) -> usize { +fn read_atomic_u32_slots(slots: &[AtomicUsize], addr: usize, base: usize, len: usize) -> usize { let word = (addr - base) >> 2; let value = slots - .get(eiointc_word_index(vcpu_index, words_per_vcpu, word)) + .get(word) .map(|slot| slot.load(Ordering::Acquire) as u32 as usize) .unwrap_or(0); if len == 8 { value | (slots - .get(eiointc_word_index(vcpu_index, words_per_vcpu, word + 1)) + .get(word + 1) .map(|slot| (slot.load(Ordering::Acquire) as u32 as usize) << 32) .unwrap_or(0)) } else { @@ -341,27 +365,25 @@ fn read_atomic_u32_slots( fn write_atomic_u32_slots( slots: &[AtomicUsize], - vcpu_index: usize, - words_per_vcpu: usize, addr: usize, base: usize, len: usize, value: usize, ) { let word = (addr - base) >> 2; - if let Some(slot) = slots.get(eiointc_word_index(vcpu_index, words_per_vcpu, word)) { + if let Some(slot) = slots.get(word) { slot.store(value as u32 as usize, Ordering::Release); } if len == 8 - && let Some(slot) = slots.get(eiointc_word_index(vcpu_index, words_per_vcpu, word + 1)) + && let Some(slot) = slots.get(word + 1) { slot.store((value >> 32) as u32 as usize, Ordering::Release); } } -fn eiointc_isr_word(vcpu_index: usize, word: usize) -> usize { - EIOINTC_ISR_WORDS - .get(eiointc_isr_index(vcpu_index, word / 2)) +fn eiointc_isr_word(vcpu: &LoongArchVcpuIocsrState, word: usize) -> usize { + vcpu.eiointc_isr + .get(word / 2) .map(|slot| { let value = slot.load(Ordering::Acquire); if word.is_multiple_of(2) { @@ -373,55 +395,63 @@ fn eiointc_isr_word(vcpu_index: usize, word: usize) -> usize { .unwrap_or(0) } -fn clear_eiointc_isr_word(vcpu_index: usize, word: usize, value: usize) { - if let Some(slot) = EIOINTC_ISR_WORDS.get(eiointc_isr_index(vcpu_index, word / 2)) { +fn clear_eiointc_isr_word(vcpu: &LoongArchVcpuIocsrState, word: usize, value: usize) { + if let Some(slot) = vcpu.eiointc_isr.get(word / 2) { let shift = (word % 2) * 32; let mask = (value as u32 as usize) << shift; slot.fetch_and(!mask, Ordering::AcqRel); } } -fn read_eiointc_isr_slots(vcpu_index: usize, addr: usize, base: usize, len: usize) -> usize { +fn read_eiointc_isr_slots( + vcpu: &LoongArchVcpuIocsrState, + addr: usize, + base: usize, + len: usize, +) -> usize { let word = (addr - base) >> 2; - let value = eiointc_isr_word(vcpu_index, word); + let value = eiointc_isr_word(vcpu, word); if len == 8 { - value | (eiointc_isr_word(vcpu_index, word + 1) << 32) + value | (eiointc_isr_word(vcpu, word + 1) << 32) } else { value } } -fn clear_eiointc_isr_slots(vcpu_index: usize, addr: usize, base: usize, len: usize, value: usize) { +fn clear_eiointc_isr_slots( + vcpu: &LoongArchVcpuIocsrState, + addr: usize, + base: usize, + len: usize, + value: usize, +) { let word = (addr - base) >> 2; - clear_eiointc_isr_word(vcpu_index, word, value); + clear_eiointc_isr_word(vcpu, word, value); if len == 8 { - clear_eiointc_isr_word(vcpu_index, word + 1, value >> 32); + clear_eiointc_isr_word(vcpu, word + 1, value >> 32); } } -fn eiointc_enable_word(vcpu_index: usize, word: usize) -> usize { - EIOINTC_ENABLE_WORDS[eiointc_word_index(vcpu_index, EIOINTC_ENABLE_WORDS_PER_VCPU, word)] - .load(Ordering::Acquire) +fn eiointc_enable_word(vcpu: &LoongArchVcpuIocsrState, word: usize) -> usize { + vcpu.eiointc_enable[word].load(Ordering::Acquire) } -fn eiointc_ipmap_word(vcpu_index: usize, word: usize) -> usize { - EIOINTC_IPMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_IPMAP_WORDS, word)] - .load(Ordering::Acquire) +fn eiointc_ipmap_word(vcpu: &LoongArchVcpuIocsrState, word: usize) -> usize { + vcpu.eiointc_ipmap[word].load(Ordering::Acquire) } -fn eiointc_coremap_word(vcpu_index: usize, word: usize) -> usize { - EIOINTC_COREMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_COREMAP_WORDS, word)] - .load(Ordering::Acquire) +fn eiointc_coremap_word(vcpu: &LoongArchVcpuIocsrState, word: usize) -> usize { + vcpu.eiointc_coremap[word].load(Ordering::Acquire) } -fn eiointc_virt_config(vcpu_index: usize) -> usize { - EIOINTC_VIRT_CONFIG_WORDS[vcpu_index].load(Ordering::Acquire) +fn eiointc_virt_config(vcpu: &LoongArchVcpuIocsrState) -> usize { + vcpu.eiointc_virt_config.load(Ordering::Acquire) } -fn eiointc_group_for_source(vcpu_index: usize, source: usize) -> Option { +fn eiointc_group_for_source(vcpu: &LoongArchVcpuIocsrState, source: usize) -> Option { let ipmap_index = source >> 7; let ipmap_byte = (source >> 5) & 0x3; - let ipmap = eiointc_ipmap_word(vcpu_index, ipmap_index); + let ipmap = eiointc_ipmap_word(vcpu, ipmap_index); let pin_mask = (ipmap >> (ipmap_byte * 8)) & 0xff; if pin_mask == 0 { None @@ -430,21 +460,21 @@ fn eiointc_group_for_source(vcpu_index: usize, source: usize) -> Option { } } -fn eiointc_source_targets_vcpu0(vcpu_index: usize, source: usize) -> bool { +fn eiointc_source_targets_vcpu0(vcpu: &LoongArchVcpuIocsrState, source: usize) -> bool { let word = source >> 2; let byte = source & 0x3; - let route = (eiointc_coremap_word(vcpu_index, word) >> (byte * 8)) & 0xff; + let route = (eiointc_coremap_word(vcpu, word) >> (byte * 8)) & 0xff; - if eiointc_virt_config(vcpu_index) & EXTIOI_ENABLE_CPU_ENCODE != 0 { + if eiointc_virt_config(vcpu) & EXTIOI_ENABLE_CPU_ENCODE != 0 { route == 0 || route == 1 } else { route & 0x1 != 0 } } -fn eiointc_cpu_irq_for_source(vcpu_index: usize, source: usize) -> Option { - let pin = eiointc_group_for_source(vcpu_index, source)?; - if !eiointc_source_targets_vcpu0(vcpu_index, source) { +fn eiointc_cpu_irq_for_source(vcpu: &LoongArchVcpuIocsrState, source: usize) -> Option { + let pin = eiointc_group_for_source(vcpu, source)?; + if !eiointc_source_targets_vcpu0(vcpu, source) { return None; } @@ -455,16 +485,16 @@ fn eiointc_cpu_irq_for_source(vcpu_index: usize, source: usize) -> Option } } -fn guest_eiointc_pending_hwi(vcpu_index: usize) -> Option { +fn guest_eiointc_pending_hwi(vcpu: &LoongArchVcpuIocsrState) -> Option { for word in 0..EIOINTC_ENABLE_WORDS_PER_VCPU { - let pending = eiointc_isr_word(vcpu_index, word) & eiointc_enable_word(vcpu_index, word); + let pending = eiointc_isr_word(vcpu, word) & eiointc_enable_word(vcpu, word); if pending == 0 { continue; } for bit in 0..u32::BITS as usize { if pending & (1usize << bit) != 0 { let source = word * u32::BITS as usize + bit; - if let Some(hwi) = eiointc_cpu_irq_for_source(vcpu_index, source) { + if let Some(hwi) = eiointc_cpu_irq_for_source(vcpu, source) { return Some(hwi); } } @@ -473,9 +503,9 @@ fn guest_eiointc_pending_hwi(vcpu_index: usize) -> Option { None } -fn update_guest_eiointc_irq(ctx: &mut LoongArchContextFrame, vcpu_index: usize) { +fn update_guest_eiointc_irq(ctx: &mut LoongArchContextFrame, vcpu: &LoongArchVcpuIocsrState) { let hwi_bits = HWI_MASK; - if let Some(hwi) = guest_eiointc_pending_hwi(vcpu_index) { + if let Some(hwi) = guest_eiointc_pending_hwi(vcpu) { ctx.gcsr_estat = (ctx.gcsr_estat & !hwi_bits) | (1usize << hwi); crate::registers::set_hwi_interrupts(1usize << hwi); } else { @@ -484,77 +514,27 @@ fn update_guest_eiointc_irq(ctx: &mut LoongArchContextFrame, vcpu_index: usize) } } -pub(crate) fn init_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId) { - let Some(vcpu_index) = iocsr_vcpu_index(vm_id, vcpu_id) else { - log::warn!( - "LoongArch guest IOCSR init skipped: VM[{vm_id}] VCpu[{vcpu_id}] exceeds capacity" - ); +pub(crate) fn init_guest_iocsr(state: &LoongArchIocsrState, vcpu_id: VCpuId) { + let Some(vcpu) = state.vcpu(vcpu_id) else { + log::warn!("LoongArch guest IOCSR init skipped: VCpu[{vcpu_id}] is not in VM state"); return; }; - clear_guest_iocsr_vcpu(vcpu_index); + vcpu.reset(); for word in 0..EIOINTC_NODEMAP_WORDS { let value = ((1usize << (word * 2 + 1)) << 16) | (1usize << (word * 2)); - EIOINTC_NODEMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_NODEMAP_WORDS, word)] - .store(value as u32 as usize, Ordering::Release); + vcpu.eiointc_nodemap[word].store(value as u32 as usize, Ordering::Release); } for word in 0..EIOINTC_ENABLE_WORDS_PER_VCPU { - EIOINTC_ENABLE_WORDS[eiointc_word_index(vcpu_index, EIOINTC_ENABLE_WORDS_PER_VCPU, word)] - .store(u32::MAX as usize, Ordering::Release); - EIOINTC_BOUNCE_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_BOUNCE_WORDS, word)] - .store(u32::MAX as usize, Ordering::Release); + vcpu.eiointc_enable[word].store(u32::MAX as usize, Ordering::Release); + vcpu.eiointc_bounce[word].store(u32::MAX as usize, Ordering::Release); } for word in 0..EIOINTC_IPMAP_WORDS { - EIOINTC_IPMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_IPMAP_WORDS, word)] - .store(0x0101_0101, Ordering::Release); + vcpu.eiointc_ipmap[word].store(0x0101_0101, Ordering::Release); } for word in 0..EIOINTC_COREMAP_WORDS { - EIOINTC_COREMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_COREMAP_WORDS, word)] - .store(0x0101_0101, Ordering::Release); - } -} - -pub fn clear_guest_iocsr_vm(vm_id: VMId) { - if vm_id >= MAX_IOCSR_VMS { - return; - } - - for vcpu_id in 0..MAX_IOCSR_CPUS { - clear_guest_iocsr_vcpu(vm_id * MAX_IOCSR_CPUS + vcpu_id); - } -} - -fn clear_guest_iocsr_vcpu(vcpu_index: usize) { - IOCSR_IPI_STATUS_WORDS[vcpu_index].store(0, Ordering::Release); - IOCSR_IPI_ENABLE_WORDS[vcpu_index].store(0, Ordering::Release); - EIOINTC_VIRT_CONFIG_WORDS[vcpu_index].store(0, Ordering::Release); - - for word in 0..IOCSR_MAIL_BUF_COUNT { - IOCSR_MAIL_BUF_WORDS[vcpu_index * IOCSR_MAIL_BUF_COUNT + word].store(0, Ordering::Release); - } - for word in 0..EIOINTC_ISR_REG_COUNT { - EIOINTC_ISR_WORDS[eiointc_isr_index(vcpu_index, word)].store(0, Ordering::Release); - } - for word in 0..EIOINTC_NODEMAP_WORDS { - EIOINTC_NODEMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_NODEMAP_WORDS, word)] - .store(0, Ordering::Release); - } - for word in 0..EIOINTC_IPMAP_WORDS { - EIOINTC_IPMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_IPMAP_WORDS, word)] - .store(0, Ordering::Release); - } - for word in 0..EIOINTC_ENABLE_WORDS_PER_VCPU { - EIOINTC_ENABLE_WORDS[eiointc_word_index(vcpu_index, EIOINTC_ENABLE_WORDS_PER_VCPU, word)] - .store(0, Ordering::Release); - } - for word in 0..EIOINTC_BOUNCE_WORDS { - EIOINTC_BOUNCE_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_BOUNCE_WORDS, word)] - .store(0, Ordering::Release); - } - for word in 0..EIOINTC_COREMAP_WORDS { - EIOINTC_COREMAP_WORDS_STORAGE[eiointc_word_index(vcpu_index, EIOINTC_COREMAP_WORDS, word)] - .store(0, Ordering::Release); + vcpu.eiointc_coremap[word].store(0x0101_0101, Ordering::Release); } } @@ -569,6 +549,7 @@ fn iocsr_access_len_from_ty(ty: usize) -> usize { } pub(crate) fn inject_guest_eiointc_vector( + state: &LoongArchIocsrState, vm_id: VMId, vcpu_id: VCpuId, vector: usize, @@ -577,24 +558,28 @@ pub(crate) fn inject_guest_eiointc_vector( return None; } - let vcpu_index = iocsr_vcpu_index(vm_id, vcpu_id)?; + let vcpu = state.vcpu(vcpu_id)?; let reg = vector / 64; let bit = vector % 64; - let new = EIOINTC_ISR_WORDS[eiointc_isr_index(vcpu_index, reg)] - .fetch_or(1usize << bit, Ordering::AcqRel) - | (1usize << bit); + let new = vcpu.eiointc_isr[reg].fetch_or(1usize << bit, Ordering::AcqRel) | (1usize << bit); log_eiointc_trace("inject", vm_id, vcpu_id, reg, vector, new); - eiointc_cpu_irq_for_source(vcpu_index, vector).or(Some(EIOINTC_HWI_BASE + reg)) + eiointc_cpu_irq_for_source(vcpu, vector).or(Some(EIOINTC_HWI_BASE + reg)) } -fn read_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId, addr: usize, len: usize) -> Option { - let index = iocsr_vcpu_index(vm_id, vcpu_id)?; +fn read_guest_iocsr( + state: &LoongArchIocsrState, + vm_id: VMId, + vcpu_id: VCpuId, + addr: usize, + len: usize, +) -> Option { + let vcpu = state.vcpu(vcpu_id)?; match addr { - LOONGARCH_IOCSR_IPI_STATUS => Some(IOCSR_IPI_STATUS_WORDS[index].load(Ordering::Acquire)), - LOONGARCH_IOCSR_IPI_EN => Some(IOCSR_IPI_ENABLE_WORDS[index].load(Ordering::Acquire)), + LOONGARCH_IOCSR_IPI_STATUS => Some(vcpu.ipi_status.load(Ordering::Acquire)), + LOONGARCH_IOCSR_IPI_EN => Some(vcpu.ipi_enable.load(Ordering::Acquire)), LOONGARCH_IOCSR_IPI_SET | LOONGARCH_IOCSR_IPI_CLEAR | LOONGARCH_IOCSR_IPI_SEND => Some(0), - LOONGARCH_IOCSR_MAIL_BUF0..=LOONGARCH_IOCSR_MAIL_BUF3 => iocsr_mail_buf_index(index, addr) - .map(|mail_index| IOCSR_MAIL_BUF_WORDS[mail_index].load(Ordering::Acquire)), + LOONGARCH_IOCSR_MAIL_BUF0..=LOONGARCH_IOCSR_MAIL_BUF3 => iocsr_mail_buf_index(addr) + .map(|mail_index| vcpu.mail_buf[mail_index].load(Ordering::Acquire)), LOONGARCH_IOCSR_MBUF_SEND => Some(0), LOONGARCH_IOCSR_ANY_SEND => Some(0), EXTIOI_VIRT_FEATURES => Some( @@ -603,41 +588,33 @@ fn read_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId, addr: usize, len: usize) -> Op | EXTIOI_HAS_INT_ENCODE | EXTIOI_HAS_CPU_ENCODE, ), - EXTIOI_VIRT_CONFIG => Some(EIOINTC_VIRT_CONFIG_WORDS[index].load(Ordering::Acquire)), + EXTIOI_VIRT_CONFIG => Some(vcpu.eiointc_virt_config.load(Ordering::Acquire)), EIOINTC_NODEMAP_BASE..EIOINTC_NODEMAP_END => Some(read_atomic_u32_slots( - &EIOINTC_NODEMAP_WORDS_STORAGE, - index, - EIOINTC_NODEMAP_WORDS, + &vcpu.eiointc_nodemap, addr, EIOINTC_NODEMAP_BASE, len, )), EIOINTC_IPMAP_BASE..EIOINTC_IPMAP_END => Some(read_atomic_u32_slots( - &EIOINTC_IPMAP_WORDS_STORAGE, - index, - EIOINTC_IPMAP_WORDS, + &vcpu.eiointc_ipmap, addr, EIOINTC_IPMAP_BASE, len, )), EIOINTC_ENABLE_BASE..EIOINTC_ENABLE_END => Some(read_atomic_u32_slots( - &EIOINTC_ENABLE_WORDS, - index, - EIOINTC_ENABLE_WORDS_PER_VCPU, + &vcpu.eiointc_enable, addr, EIOINTC_ENABLE_BASE, len, )), EIOINTC_BOUNCE_BASE..EIOINTC_BOUNCE_END => Some(read_atomic_u32_slots( - &EIOINTC_BOUNCE_WORDS_STORAGE, - index, - EIOINTC_BOUNCE_WORDS, + &vcpu.eiointc_bounce, addr, EIOINTC_BOUNCE_BASE, len, )), EIOINTC_ISR_COMPAT_BASE..EIOINTC_ISR_COMPAT_END => { - let value = read_eiointc_isr_slots(index, addr, EIOINTC_ISR_COMPAT_BASE, len); + let value = read_eiointc_isr_slots(vcpu, addr, EIOINTC_ISR_COMPAT_BASE, len); log_eiointc_trace( "read", vm_id, @@ -649,7 +626,7 @@ fn read_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId, addr: usize, len: usize) -> Op Some(value) } EIOINTC_ISR_BASE..EIOINTC_ISR_END => { - let value = read_eiointc_isr_slots(index, addr, EIOINTC_ISR_BASE, len); + let value = read_eiointc_isr_slots(vcpu, addr, EIOINTC_ISR_BASE, len); log_eiointc_trace( "read", vm_id, @@ -661,9 +638,7 @@ fn read_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId, addr: usize, len: usize) -> Op Some(value) } EIOINTC_COREMAP_BASE..EIOINTC_COREMAP_END => Some(read_atomic_u32_slots( - &EIOINTC_COREMAP_WORDS_STORAGE, - index, - EIOINTC_COREMAP_WORDS, + &vcpu.eiointc_coremap, addr, EIOINTC_COREMAP_BASE, len, @@ -673,6 +648,7 @@ fn read_guest_iocsr(vm_id: VMId, vcpu_id: VCpuId, addr: usize, len: usize) -> Op } fn write_guest_iocsr( + state: &LoongArchIocsrState, ctx: &mut LoongArchContextFrame, vm_id: VMId, vcpu_id: VCpuId, @@ -680,21 +656,20 @@ fn write_guest_iocsr( len: usize, value: usize, ) -> Option { - let index = iocsr_vcpu_index(vm_id, vcpu_id)?; + let vcpu = state.vcpu(vcpu_id)?; match addr { LOONGARCH_IOCSR_IPI_STATUS => Some(AxVCpuExitReason::Nothing), LOONGARCH_IOCSR_IPI_EN => { - IOCSR_IPI_ENABLE_WORDS[index].store(value, Ordering::Release); + vcpu.ipi_enable.store(value, Ordering::Release); Some(AxVCpuExitReason::Nothing) } LOONGARCH_IOCSR_IPI_SET => { - IOCSR_IPI_STATUS_WORDS[index].fetch_or(value, Ordering::AcqRel); + vcpu.ipi_status.fetch_or(value, Ordering::AcqRel); ctx.gcsr_estat |= IPI_BIT; Some(AxVCpuExitReason::Nothing) } LOONGARCH_IOCSR_IPI_CLEAR => { - let new_status = - IOCSR_IPI_STATUS_WORDS[index].fetch_and(!value, Ordering::AcqRel) & !value; + let new_status = vcpu.ipi_status.fetch_and(!value, Ordering::AcqRel) & !value; if new_status == 0 { ctx.gcsr_estat &= !IPI_BIT; } @@ -703,8 +678,10 @@ fn write_guest_iocsr( LOONGARCH_IOCSR_IPI_SEND => { let target_cpu = (value >> IOCSR_SEND_CPU_SHIFT) & IOCSR_SEND_CPU_MASK; let action = value & IOCSR_IPI_ACTION_MASK; - if let Some(target_index) = iocsr_vcpu_index(vm_id, target_cpu) { - IOCSR_IPI_STATUS_WORDS[target_index].fetch_or(1usize << action, Ordering::AcqRel); + if let Some(target_vcpu) = state.vcpu(target_cpu) { + target_vcpu + .ipi_status + .fetch_or(1usize << action, Ordering::AcqRel); if target_cpu == vcpu_id { ctx.gcsr_estat |= IPI_BIT; } else { @@ -721,8 +698,8 @@ fn write_guest_iocsr( Some(AxVCpuExitReason::Nothing) } LOONGARCH_IOCSR_MAIL_BUF0..=LOONGARCH_IOCSR_MAIL_BUF3 => { - if let Some(mail_index) = iocsr_mail_buf_index(index, addr) { - IOCSR_MAIL_BUF_WORDS[mail_index].store(value, Ordering::Release); + if let Some(mail_index) = iocsr_mail_buf_index(addr) { + vcpu.mail_buf[mail_index].store(value, Ordering::Release); } Some(AxVCpuExitReason::Nothing) } @@ -732,16 +709,15 @@ fn write_guest_iocsr( let mail_buf = mail_word / 2; let is_high_word = mail_word % 2 == 1; if mail_buf < IOCSR_MAIL_BUF_COUNT { - if let Some(target_index) = iocsr_vcpu_index(vm_id, target_cpu) { - let mail_index = target_index * IOCSR_MAIL_BUF_COUNT + mail_buf; - let old = IOCSR_MAIL_BUF_WORDS[mail_index].load(Ordering::Acquire); + if let Some(target_vcpu) = state.vcpu(target_cpu) { + let old = target_vcpu.mail_buf[mail_buf].load(Ordering::Acquire); let new = if is_high_word { (old & !IOCSR_MBUF_SEND_H32_MASK) | (value & IOCSR_MBUF_SEND_H32_MASK) } else { let low = value >> IOCSR_MBUF_SEND_BUF_SHIFT; (old & IOCSR_MBUF_SEND_H32_MASK) | low }; - IOCSR_MAIL_BUF_WORDS[mail_index].store(new, Ordering::Release); + target_vcpu.mail_buf[mail_buf].store(new, Ordering::Release); } else { log::debug!( "LoongArch guest IOCSR MBUF_SEND ignored for unsupported target_cpu={} \ @@ -761,6 +737,7 @@ fn write_guest_iocsr( let target = value & 0xffff; if target_cpu == vcpu_id { write_guest_iocsr_send_data( + state, ctx, vm_id, vcpu_id, @@ -772,15 +749,13 @@ fn write_guest_iocsr( Some(AxVCpuExitReason::Nothing) } EXTIOI_VIRT_CONFIG => { - EIOINTC_VIRT_CONFIG_WORDS[index].store(value, Ordering::Release); - update_guest_eiointc_irq(ctx, index); + vcpu.eiointc_virt_config.store(value, Ordering::Release); + update_guest_eiointc_irq(ctx, vcpu); Some(AxVCpuExitReason::Nothing) } EIOINTC_NODEMAP_BASE..EIOINTC_NODEMAP_END => { write_atomic_u32_slots( - &EIOINTC_NODEMAP_WORDS_STORAGE, - index, - EIOINTC_NODEMAP_WORDS, + &vcpu.eiointc_nodemap, addr, EIOINTC_NODEMAP_BASE, len, @@ -789,72 +764,46 @@ fn write_guest_iocsr( Some(AxVCpuExitReason::Nothing) } EIOINTC_IPMAP_BASE..EIOINTC_IPMAP_END => { - write_atomic_u32_slots( - &EIOINTC_IPMAP_WORDS_STORAGE, - index, - EIOINTC_IPMAP_WORDS, - addr, - EIOINTC_IPMAP_BASE, - len, - value, - ); - update_guest_eiointc_irq(ctx, index); + write_atomic_u32_slots(&vcpu.eiointc_ipmap, addr, EIOINTC_IPMAP_BASE, len, value); + update_guest_eiointc_irq(ctx, vcpu); Some(AxVCpuExitReason::Nothing) } EIOINTC_ENABLE_BASE..EIOINTC_ENABLE_END => { - write_atomic_u32_slots( - &EIOINTC_ENABLE_WORDS, - index, - EIOINTC_ENABLE_WORDS_PER_VCPU, - addr, - EIOINTC_ENABLE_BASE, - len, - value, - ); - update_guest_eiointc_irq(ctx, index); + write_atomic_u32_slots(&vcpu.eiointc_enable, addr, EIOINTC_ENABLE_BASE, len, value); + update_guest_eiointc_irq(ctx, vcpu); Some(AxVCpuExitReason::Nothing) } EIOINTC_BOUNCE_BASE..EIOINTC_BOUNCE_END => { - write_atomic_u32_slots( - &EIOINTC_BOUNCE_WORDS_STORAGE, - index, - EIOINTC_BOUNCE_WORDS, - addr, - EIOINTC_BOUNCE_BASE, - len, - value, - ); + write_atomic_u32_slots(&vcpu.eiointc_bounce, addr, EIOINTC_BOUNCE_BASE, len, value); Some(AxVCpuExitReason::Nothing) } EIOINTC_ISR_COMPAT_BASE..EIOINTC_ISR_COMPAT_END => { - clear_eiointc_isr_slots(index, addr, EIOINTC_ISR_COMPAT_BASE, len, value); - update_guest_eiointc_irq(ctx, index); + clear_eiointc_isr_slots(vcpu, addr, EIOINTC_ISR_COMPAT_BASE, len, value); + update_guest_eiointc_irq(ctx, vcpu); Some(AxVCpuExitReason::Nothing) } EIOINTC_ISR_BASE..EIOINTC_ISR_END if is_eiointc_isr_addr(addr) => { - clear_eiointc_isr_slots(index, addr, EIOINTC_ISR_BASE, len, value); - update_guest_eiointc_irq(ctx, index); + clear_eiointc_isr_slots(vcpu, addr, EIOINTC_ISR_BASE, len, value); + update_guest_eiointc_irq(ctx, vcpu); log_eiointc_trace( "clear", vm_id, vcpu_id, (addr - EIOINTC_ISR_BASE) / 8, addr - EIOINTC_ISR_BASE, - read_eiointc_isr_slots(index, addr, EIOINTC_ISR_BASE, len), + read_eiointc_isr_slots(vcpu, addr, EIOINTC_ISR_BASE, len), ); Some(AxVCpuExitReason::Nothing) } EIOINTC_COREMAP_BASE..EIOINTC_COREMAP_END => { write_atomic_u32_slots( - &EIOINTC_COREMAP_WORDS_STORAGE, - index, - EIOINTC_COREMAP_WORDS, + &vcpu.eiointc_coremap, addr, EIOINTC_COREMAP_BASE, len, value, ); - update_guest_eiointc_irq(ctx, index); + update_guest_eiointc_irq(ctx, vcpu); Some(AxVCpuExitReason::Nothing) } EIOINTC_GUEST_OWNED_BASE..EIOINTC_GUEST_OWNED_END => Some(AxVCpuExitReason::Nothing), @@ -863,6 +812,7 @@ fn write_guest_iocsr( } fn write_guest_iocsr_send_data( + state: &LoongArchIocsrState, ctx: &mut LoongArchContextFrame, vm_id: VMId, vcpu_id: VCpuId, @@ -874,7 +824,7 @@ fn write_guest_iocsr_send_data( let mut data = (value >> data_shift) as u32 as usize; if preserve_mask != 0 { - let old = read_guest_iocsr(vm_id, vcpu_id, target, 4).unwrap_or(0) as u32; + let old = read_guest_iocsr(state, vm_id, vcpu_id, target, 4).unwrap_or(0) as u32; let mut byte_mask = 0u32; for byte in 0..4 { if preserve_mask & (1 << byte) != 0 { @@ -884,7 +834,7 @@ fn write_guest_iocsr_send_data( data = ((old & byte_mask) as usize) | (data & !(byte_mask as usize)); } - let _ = write_guest_iocsr(ctx, vm_id, vcpu_id, target, 4, data); + let _ = write_guest_iocsr(state, ctx, vm_id, vcpu_id, target, 4, data); } fn should_inject_guest_virtual_fault( @@ -954,12 +904,12 @@ fn inject_guest_interrupt_at(ctx: &mut LoongArchContextFrame, vector: usize, pc: } pub(crate) fn inject_enabled_pending_interrupt( + state: &LoongArchIocsrState, ctx: &mut LoongArchContextFrame, - vm_id: VMId, vcpu_id: VCpuId, ) -> bool { - if let Some(index) = iocsr_vcpu_index(vm_id, vcpu_id) { - update_guest_eiointc_irq(ctx, index); + if let Some(vcpu) = state.vcpu(vcpu_id) { + update_guest_eiointc_irq(ctx, vcpu); } let pending_enabled = ctx.gcsr_estat & ctx.gcsr_ectl & LOCAL_INTERRUPT_MASK; if ctx.gcsr_eentry != 0 @@ -1407,6 +1357,7 @@ fn emulate_idle(ctx: &mut LoongArchContextFrame, ins: usize) -> AxVCpuExitReason } fn emulate_iocsr( + state: &LoongArchIocsrState, ctx: &mut LoongArchContextFrame, ins: usize, vm_id: VMId, @@ -1463,57 +1414,67 @@ fn emulate_iocsr( match ty { 0 => { - let value = read_guest_iocsr(vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { - let value: usize; - unsafe { - core::arch::asm!("iocsrrd.b {}, {}", out(reg) value, in(reg) rj_value); - } - value - }); + let value = + read_guest_iocsr(state, vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.b {}, {}", out(reg) value, in(reg) rj_value); + } + value + }); log_iocsr(ctx, "read.b", value); target_log(ctx, "read.b", value); ctx.set_gpr(rd, (value as i8) as isize as usize); } 1 => { - let value = read_guest_iocsr(vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { - let value: usize; - unsafe { - core::arch::asm!("iocsrrd.h {}, {}", out(reg) value, in(reg) rj_value); - } - value - }); + let value = + read_guest_iocsr(state, vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.h {}, {}", out(reg) value, in(reg) rj_value); + } + value + }); log_iocsr(ctx, "read.h", value); target_log(ctx, "read.h", value); ctx.set_gpr(rd, (value as i16) as isize as usize); } 2 => { - let value = read_guest_iocsr(vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { - let value: usize; - unsafe { - core::arch::asm!("iocsrrd.w {}, {}", out(reg) value, in(reg) rj_value); - } - value - }); + let value = + read_guest_iocsr(state, vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.w {}, {}", out(reg) value, in(reg) rj_value); + } + value + }); log_iocsr(ctx, "read.w", value); target_log(ctx, "read.w", value); ctx.set_gpr(rd, (value as i32) as isize as usize); } 3 => { - let value = read_guest_iocsr(vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { - let value: usize; - unsafe { - core::arch::asm!("iocsrrd.d {}, {}", out(reg) value, in(reg) rj_value); - } - value - }); + let value = + read_guest_iocsr(state, vm_id, vcpu_id, rj_value, len).unwrap_or_else(|| { + let value: usize; + unsafe { + core::arch::asm!("iocsrrd.d {}, {}", out(reg) value, in(reg) rj_value); + } + value + }); log_iocsr(ctx, "read.d", value); target_log(ctx, "read.d", value); ctx.set_gpr(rd, value); } 4 => { - if let Some(reason) = - write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, len, ctx.x[rd] as u8 as usize) - { + if let Some(reason) = write_guest_iocsr( + state, + ctx, + vm_id, + vcpu_id, + rj_value, + len, + ctx.x[rd] as u8 as usize, + ) { advance_guest_pc(ctx); return reason; } else { @@ -1525,6 +1486,7 @@ fn emulate_iocsr( } 5 => { if let Some(reason) = write_guest_iocsr( + state, ctx, vm_id, vcpu_id, @@ -1543,6 +1505,7 @@ fn emulate_iocsr( } 6 => { if let Some(reason) = write_guest_iocsr( + state, ctx, vm_id, vcpu_id, @@ -1560,7 +1523,9 @@ fn emulate_iocsr( } } 7 => { - if let Some(reason) = write_guest_iocsr(ctx, vm_id, vcpu_id, rj_value, len, ctx.x[rd]) { + if let Some(reason) = + write_guest_iocsr(state, ctx, vm_id, vcpu_id, rj_value, len, ctx.x[rd]) + { advance_guest_pc(ctx); return reason; } else { @@ -1601,6 +1566,7 @@ fn log_eiointc_trace( } fn emulate_gspr( + state: &LoongArchIocsrState, ctx: &mut LoongArchContextFrame, vm_id: VMId, vcpu_id: VCpuId, @@ -1658,7 +1624,7 @@ fn emulate_gspr( return emulate_csrx(ctx, ins, vm_id, vcpu_id, guest_timer_token); } if matches(OPCODE_IOCSR, OPCODE_IOCSR_LEN) { - return emulate_iocsr(ctx, ins, vm_id, vcpu_id); + return emulate_iocsr(state, ctx, ins, vm_id, vcpu_id); } panic!( @@ -1669,6 +1635,7 @@ fn emulate_gspr( } pub fn handle_exception_sync( + iocsr_state: &LoongArchIocsrState, ctx: &mut LoongArchContextFrame, vm_id: VMId, vcpu_id: VCpuId, @@ -1754,7 +1721,13 @@ pub fn handle_exception_sync( advance_guest_pc(ctx); Ok(AxVCpuExitReason::Hypercall { nr, args }) } - ECODE_GSPR => Ok(emulate_gspr(ctx, vm_id, vcpu_id, guest_timer_token)), + ECODE_GSPR => Ok(emulate_gspr( + iocsr_state, + ctx, + vm_id, + vcpu_id, + guest_timer_token, + )), ECODE_PIL | ECODE_PIS | ECODE_PIF | ECODE_PME | ECODE_PNR | ECODE_PNX | ECODE_PPI => { let badv = get_badv(ctx); if should_inject_guest_virtual_fault(ctx, badv, false) { diff --git a/virtualization/loongarch_vcpu/src/lib.rs b/virtualization/loongarch_vcpu/src/lib.rs index 44cf186417..e8b053c19e 100644 --- a/virtualization/loongarch_vcpu/src/lib.rs +++ b/virtualization/loongarch_vcpu/src/lib.rs @@ -13,7 +13,10 @@ mod vcpu; pub use self::{ context_frame::LoongArchContextFrame, - exception::{TrapKind, clear_guest_iocsr_vm, handle_exception_irq, handle_exception_sync}, + exception::{ + LoongArchIocsrState, LoongArchIocsrStateRef, TrapKind, handle_exception_irq, + handle_exception_sync, + }, pcpu::LoongArchPerCpu, registers::inject_interrupt, vcpu::{LoongArchVCpu, LoongArchVCpuCreateConfig, LoongArchVCpuSetupConfig}, diff --git a/virtualization/loongarch_vcpu/src/vcpu.rs b/virtualization/loongarch_vcpu/src/vcpu.rs index d2b4c661c6..3697ad42a7 100644 --- a/virtualization/loongarch_vcpu/src/vcpu.rs +++ b/virtualization/loongarch_vcpu/src/vcpu.rs @@ -13,6 +13,7 @@ use loongArch64::register::prmd; use crate::exception::{TrapKind, current_badi, handle_exception_irq, handle_exception_sync}; use crate::{ context_frame::LoongArchContextFrame, + exception::LoongArchIocsrStateRef, host, registers::{ CSR_ASID, CSR_CRMD, CSR_ECFG, CSR_KSAVE_KSP, CSR_PGDH, CSR_PGDL, CSR_PRMD, CSR_PWCH, @@ -52,6 +53,7 @@ pub struct LoongArchVCpu { vm_id: VMId, vcpu_id: VCpuId, cpu_id: usize, + iocsr_state: LoongArchIocsrStateRef, guest_timer_token: Option, last_badi: usize, entry_logged: bool, @@ -116,13 +118,14 @@ const LOCAL_INTERRUPT_MASK: usize = (1 << (INT_IPI + 1)) - 1; #[cfg(target_arch = "loongarch64")] const HOST_DMW_CACHED_BASE: usize = 0x9000_0000_0000_0000; -#[derive(Clone, Debug, Default)] +#[derive(Clone, Debug)] pub struct LoongArchVCpuCreateConfig { pub cpu_id: usize, pub dtb_addr: usize, pub boot_args: [usize; 3], pub boot_stack_top: usize, pub firmware_boot: bool, + pub iocsr_state: LoongArchIocsrStateRef, } #[derive(Clone, Debug, Default)] @@ -139,7 +142,6 @@ impl AxArchVCpu for LoongArchVCpu { type SetupConfig = LoongArchVCpuSetupConfig; fn new(_vm_id: usize, _vcpu_id: usize, config: Self::CreateConfig) -> AxResult { - crate::exception::validate_guest_iocsr_capacity(_vm_id, _vcpu_id)?; let mut ctx = LoongArchContextFrame::default(); if config.firmware_boot { // Firmware reset entry keeps the initial argument registers in their @@ -164,6 +166,7 @@ impl AxArchVCpu for LoongArchVCpu { vm_id: _vm_id, vcpu_id: _vcpu_id, cpu_id: config.cpu_id, + iocsr_state: config.iocsr_state, guest_timer_token: None, last_badi: 0, entry_logged: false, @@ -201,8 +204,8 @@ impl AxArchVCpu for LoongArchVCpu { self.enable_guest_mode(); } if crate::exception::inject_enabled_pending_interrupt( + &self.iocsr_state, &mut self.ctx, - self.vm_id, self.vcpu_id, ) { log::trace!( @@ -311,9 +314,12 @@ impl AxArchVCpu for LoongArchVCpu { crate::registers::inject_interrupt(vector); } else if vector <= INT_IPI { self.ctx.gcsr_estat |= 1usize << vector; - } else if let Some(hwi) = - crate::exception::inject_guest_eiointc_vector(self.vm_id, self.vcpu_id, vector) - { + } else if let Some(hwi) = crate::exception::inject_guest_eiointc_vector( + &self.iocsr_state, + self.vm_id, + self.vcpu_id, + vector, + ) { crate::registers::inject_interrupt(hwi); } else { log::warn!("Ignoring unsupported LoongArch interrupt vector {vector}"); @@ -329,9 +335,12 @@ impl AxArchVCpu for LoongArchVCpu { impl LoongArchVCpu { #[cfg(target_arch = "loongarch64")] pub fn inject_external_interrupt(&mut self, vector: usize, physical_irq: usize) -> AxResult { - if let Some(hwi) = - crate::exception::inject_guest_eiointc_vector(self.vm_id, self.vcpu_id, vector) - { + if let Some(hwi) = crate::exception::inject_guest_eiointc_vector( + &self.iocsr_state, + self.vm_id, + self.vcpu_id, + vector, + ) { self.ctx.gcsr_estat |= 1usize << hwi; log::debug!( "LoongArch guest external IRQ pending: VM[{}] VCpu[{}] physical_irq={}, \ @@ -387,7 +396,7 @@ impl LoongArchVCpu { fn init_hv(&mut self, config: LoongArchVCpuSetupConfig) { self.init_vm_context(config); #[cfg(target_arch = "loongarch64")] - crate::exception::init_guest_iocsr(self.vm_id, self.vcpu_id); + crate::exception::init_guest_iocsr(&self.iocsr_state, self.vcpu_id); #[cfg(target_arch = "loongarch64")] unsafe { gintc_set_hwi_passthrough(0); @@ -569,6 +578,7 @@ impl LoongArchVCpu { match exit_reason { TrapKind::Synchronous => handle_exception_sync( + &self.iocsr_state, &mut self.ctx, self.vm_id, self.vcpu_id, From ce3b4a61a214980e67e9db2064b06e91f228562d Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 25 Jun 2026 15:00:17 +0800 Subject: [PATCH 42/50] fix(someboot): make LoongArch PE image base configurable --- components/someboot/build.rs | 7 +++- .../someboot/src/arch/loongarch64/head.rs | 42 ++++++++++++++++++- .../someboot/tests/loongarch64_efi_header.rs | 17 ++++++++ .../configs/board/qemu-loongarch64.toml | 2 + 4 files changed, 65 insertions(+), 3 deletions(-) create mode 100644 components/someboot/tests/loongarch64_efi_header.rs diff --git a/components/someboot/build.rs b/components/someboot/build.rs index 47627c37cd..b0359dabcd 100644 --- a/components/someboot/build.rs +++ b/components/someboot/build.rs @@ -115,11 +115,14 @@ impl Build { } fn prepare_loongarch64(&mut self) { - self.kernel_paddr = - env_u64("SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR").unwrap_or(0x8000_0000); + if let Some(kernel_paddr) = env_u64("SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR") { + self.kernel_paddr = kernel_paddr; + } + let pe_image_base = env_u64("SOMEBOOT_LOONGARCH64_PE_IMAGE_BASE").unwrap_or(0); self.kernel_vaddr = 0xffff_ffff_8000_0000; println!("cargo:rustc-cfg=efi"); + println!("cargo:rustc-env=SOMEBOOT_LOONGARCH64_PE_IMAGE_BASE={pe_image_base:#x}"); self.write_linker_script(LinkerArch::Loongarch64); } diff --git a/components/someboot/src/arch/loongarch64/head.rs b/components/someboot/src/arch/loongarch64/head.rs index 9bdf11303e..99cd6f5e10 100644 --- a/components/someboot/src/arch/loongarch64/head.rs +++ b/components/someboot/src/arch/loongarch64/head.rs @@ -6,6 +6,9 @@ use crate::{ efi_stub::{efi_pe_entry, pe::*}, }; +const PE_IMAGE_BASE: usize = + const_u64_from_env(env!("SOMEBOOT_LOONGARCH64_PE_IMAGE_BASE")) as usize; + /// LoongArch64 kernel header implementing functionality similar to /// Linux arch/loongarch/kernel/head.S _head section #[unsafe(naked)] @@ -48,7 +51,7 @@ pub unsafe extern "C" fn _head() { ".long _stext - _head", // BaseOfCode // Extra header fields - ".quad {phys_link_kaddr}", // ImageBase + ".quad {pe_image_base}", // ImageBase ".long PAGE_SIZE", // SectionAlignment (PECOFF_SEGMENT_ALIGN) ".long PECOFF_FILE_ALIGN", // FileAlignment (PECOFF_FILE_ALIGN) ".short 0", // MajorOperatingSystemVersion @@ -110,6 +113,7 @@ pub unsafe extern "C" fn _head() { dos_signature = const IMAGE_DOS_SIGNATURE, linux_pe_magic = const LINUX_PE_MAGIC, phys_link_kaddr = const KERNEL_LOAD_ADDRESS, + pe_image_base = const PE_IMAGE_BASE, efi_pe_entry = sym efi_pe_entry, image_nt_signature = const IMAGE_NT_SIGNATURE, file_machine = const IMAGE_FILE_MACHINE_LOONGARCH64, @@ -119,3 +123,39 @@ pub unsafe extern "C" fn _head() { image_subsystem = const IMAGE_SUBSYSTEM_EFI_APPLICATION, ) } + +const fn const_u64_from_env(value: &str) -> u64 { + let bytes = value.as_bytes(); + let mut index = 0; + let mut parsed = 0; + let radix; + + if bytes.len() >= 2 && bytes[0] == b'0' && (bytes[1] == b'x' || bytes[1] == b'X') { + index = 2; + radix = 16; + } else { + radix = 10; + } + + while index < bytes.len() { + let digit = match bytes[index] { + b'_' => { + index += 1; + continue; + } + b'0'..=b'9' => bytes[index] - b'0', + b'a'..=b'f' => bytes[index] - b'a' + 10, + b'A'..=b'F' => bytes[index] - b'A' + 10, + _ => panic!("invalid numeric environment value"), + }; + + if digit as u64 >= radix { + panic!("invalid numeric environment value"); + } + + parsed = parsed * radix + digit as u64; + index += 1; + } + + parsed +} diff --git a/components/someboot/tests/loongarch64_efi_header.rs b/components/someboot/tests/loongarch64_efi_header.rs new file mode 100644 index 0000000000..7235750a85 --- /dev/null +++ b/components/someboot/tests/loongarch64_efi_header.rs @@ -0,0 +1,17 @@ +const LOONGARCH64_HEAD: &str = include_str!("../src/arch/loongarch64/head.rs"); + +#[test] +fn loongarch64_efi_image_base_stays_position_independent() { + assert!( + LOONGARCH64_HEAD.contains(".quad {phys_link_kaddr}\", // PHYS_LINK_KADDR"), + "LoongArch direct boot metadata should still record PHYS_LINK_KADDR" + ); + assert!( + LOONGARCH64_HEAD.contains(".quad {pe_image_base}\", // ImageBase"), + "LoongArch UEFI PE ImageBase should be configurable for board-specific firmware quirks" + ); + assert!( + !LOONGARCH64_HEAD.contains(".quad {phys_link_kaddr}\", // ImageBase"), + "LoongArch UEFI PE ImageBase must not reuse the direct-boot physical link address" + ); +} diff --git a/os/axvisor/configs/board/qemu-loongarch64.toml b/os/axvisor/configs/board/qemu-loongarch64.toml index fd43046e26..5f40702741 100644 --- a/os/axvisor/configs/board/qemu-loongarch64.toml +++ b/os/axvisor/configs/board/qemu-loongarch64.toml @@ -11,3 +11,5 @@ vm_configs = [] [env] KERNEL_BUILTIN_CMDLINE = "root=/dev/vda earlycon=uart8250,mmio,0x1fe001e0,115200" +SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR = "0x80000000" +SOMEBOOT_LOONGARCH64_PE_IMAGE_BASE = "0x80000000" From bc29586be3b69af1c7a7485184eade0b60052d86 Mon Sep 17 00:00:00 2001 From: szy Date: Thu, 25 Jun 2026 16:10:15 +0800 Subject: [PATCH 43/50] fix(someboot): restore LoongArch default load address --- components/someboot/build.rs | 6 +-- .../someboot/src/arch/loongarch64/head.rs | 42 +------------------ .../someboot/tests/loongarch64_efi_header.rs | 17 -------- .../configs/board/qemu-loongarch64.toml | 2 - 4 files changed, 2 insertions(+), 65 deletions(-) delete mode 100644 components/someboot/tests/loongarch64_efi_header.rs diff --git a/components/someboot/build.rs b/components/someboot/build.rs index b0359dabcd..a6eacaa416 100644 --- a/components/someboot/build.rs +++ b/components/someboot/build.rs @@ -115,14 +115,10 @@ impl Build { } fn prepare_loongarch64(&mut self) { - if let Some(kernel_paddr) = env_u64("SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR") { - self.kernel_paddr = kernel_paddr; - } - let pe_image_base = env_u64("SOMEBOOT_LOONGARCH64_PE_IMAGE_BASE").unwrap_or(0); + self.kernel_paddr = 0x8000_0000; self.kernel_vaddr = 0xffff_ffff_8000_0000; println!("cargo:rustc-cfg=efi"); - println!("cargo:rustc-env=SOMEBOOT_LOONGARCH64_PE_IMAGE_BASE={pe_image_base:#x}"); self.write_linker_script(LinkerArch::Loongarch64); } diff --git a/components/someboot/src/arch/loongarch64/head.rs b/components/someboot/src/arch/loongarch64/head.rs index 99cd6f5e10..9bdf11303e 100644 --- a/components/someboot/src/arch/loongarch64/head.rs +++ b/components/someboot/src/arch/loongarch64/head.rs @@ -6,9 +6,6 @@ use crate::{ efi_stub::{efi_pe_entry, pe::*}, }; -const PE_IMAGE_BASE: usize = - const_u64_from_env(env!("SOMEBOOT_LOONGARCH64_PE_IMAGE_BASE")) as usize; - /// LoongArch64 kernel header implementing functionality similar to /// Linux arch/loongarch/kernel/head.S _head section #[unsafe(naked)] @@ -51,7 +48,7 @@ pub unsafe extern "C" fn _head() { ".long _stext - _head", // BaseOfCode // Extra header fields - ".quad {pe_image_base}", // ImageBase + ".quad {phys_link_kaddr}", // ImageBase ".long PAGE_SIZE", // SectionAlignment (PECOFF_SEGMENT_ALIGN) ".long PECOFF_FILE_ALIGN", // FileAlignment (PECOFF_FILE_ALIGN) ".short 0", // MajorOperatingSystemVersion @@ -113,7 +110,6 @@ pub unsafe extern "C" fn _head() { dos_signature = const IMAGE_DOS_SIGNATURE, linux_pe_magic = const LINUX_PE_MAGIC, phys_link_kaddr = const KERNEL_LOAD_ADDRESS, - pe_image_base = const PE_IMAGE_BASE, efi_pe_entry = sym efi_pe_entry, image_nt_signature = const IMAGE_NT_SIGNATURE, file_machine = const IMAGE_FILE_MACHINE_LOONGARCH64, @@ -123,39 +119,3 @@ pub unsafe extern "C" fn _head() { image_subsystem = const IMAGE_SUBSYSTEM_EFI_APPLICATION, ) } - -const fn const_u64_from_env(value: &str) -> u64 { - let bytes = value.as_bytes(); - let mut index = 0; - let mut parsed = 0; - let radix; - - if bytes.len() >= 2 && bytes[0] == b'0' && (bytes[1] == b'x' || bytes[1] == b'X') { - index = 2; - radix = 16; - } else { - radix = 10; - } - - while index < bytes.len() { - let digit = match bytes[index] { - b'_' => { - index += 1; - continue; - } - b'0'..=b'9' => bytes[index] - b'0', - b'a'..=b'f' => bytes[index] - b'a' + 10, - b'A'..=b'F' => bytes[index] - b'A' + 10, - _ => panic!("invalid numeric environment value"), - }; - - if digit as u64 >= radix { - panic!("invalid numeric environment value"); - } - - parsed = parsed * radix + digit as u64; - index += 1; - } - - parsed -} diff --git a/components/someboot/tests/loongarch64_efi_header.rs b/components/someboot/tests/loongarch64_efi_header.rs deleted file mode 100644 index 7235750a85..0000000000 --- a/components/someboot/tests/loongarch64_efi_header.rs +++ /dev/null @@ -1,17 +0,0 @@ -const LOONGARCH64_HEAD: &str = include_str!("../src/arch/loongarch64/head.rs"); - -#[test] -fn loongarch64_efi_image_base_stays_position_independent() { - assert!( - LOONGARCH64_HEAD.contains(".quad {phys_link_kaddr}\", // PHYS_LINK_KADDR"), - "LoongArch direct boot metadata should still record PHYS_LINK_KADDR" - ); - assert!( - LOONGARCH64_HEAD.contains(".quad {pe_image_base}\", // ImageBase"), - "LoongArch UEFI PE ImageBase should be configurable for board-specific firmware quirks" - ); - assert!( - !LOONGARCH64_HEAD.contains(".quad {phys_link_kaddr}\", // ImageBase"), - "LoongArch UEFI PE ImageBase must not reuse the direct-boot physical link address" - ); -} diff --git a/os/axvisor/configs/board/qemu-loongarch64.toml b/os/axvisor/configs/board/qemu-loongarch64.toml index 5f40702741..fd43046e26 100644 --- a/os/axvisor/configs/board/qemu-loongarch64.toml +++ b/os/axvisor/configs/board/qemu-loongarch64.toml @@ -11,5 +11,3 @@ vm_configs = [] [env] KERNEL_BUILTIN_CMDLINE = "root=/dev/vda earlycon=uart8250,mmio,0x1fe001e0,115200" -SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR = "0x80000000" -SOMEBOOT_LOONGARCH64_PE_IMAGE_BASE = "0x80000000" From 2bf87be57dc9facc4f7d5a712bc09f85202fdad1 Mon Sep 17 00:00:00 2001 From: szy Date: Fri, 26 Jun 2026 13:21:53 +0800 Subject: [PATCH 44/50] fix(someboot): scope LoongArch fixed load address to AxVisor --- components/someboot/build.rs | 10 +++++++++- components/someboot/src/arch/loongarch64/head.rs | 5 +++-- os/axvisor/configs/board/qemu-loongarch64.toml | 1 + 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/components/someboot/build.rs b/components/someboot/build.rs index a6eacaa416..d603960fb3 100644 --- a/components/someboot/build.rs +++ b/components/someboot/build.rs @@ -28,6 +28,7 @@ fn main() { out_dir, kernel_vaddr: 0x200000, kernel_paddr: 0x200000, + efi_image_base: 0, uspace, hv, page_size: 4096, @@ -74,6 +75,7 @@ struct Build { out_dir: PathBuf, kernel_vaddr: u64, kernel_paddr: u64, + efi_image_base: u64, uspace: bool, hv: bool, page_size: usize, @@ -115,7 +117,10 @@ impl Build { } fn prepare_loongarch64(&mut self) { - self.kernel_paddr = 0x8000_0000; + if let Some(kernel_paddr) = env_u64("SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR") { + self.kernel_paddr = kernel_paddr; + self.efi_image_base = kernel_paddr; + } self.kernel_vaddr = 0xffff_ffff_8000_0000; println!("cargo:rustc-cfg=efi"); @@ -157,11 +162,14 @@ impl Build { fn gen_defines(&self) { let kernel_load_vaddr = self.kernel_vaddr as usize; let kernel_load_paddr = self.kernel_paddr as usize; + let efi_image_base = self.efi_image_base as usize; let defines = quote::quote! { #[allow(dead_code)] pub const VM_LOAD_ADDRESS: usize = #kernel_load_vaddr; #[allow(dead_code)] pub const KERNEL_LOAD_ADDRESS: usize = #kernel_load_paddr; + #[allow(dead_code)] + pub const EFI_IMAGE_BASE: usize = #efi_image_base; }; let syntax_tree = syn::parse2(defines).unwrap(); let formatted = prettyplease::unparse(&syntax_tree); diff --git a/components/someboot/src/arch/loongarch64/head.rs b/components/someboot/src/arch/loongarch64/head.rs index 9bdf11303e..264e4c08c5 100644 --- a/components/someboot/src/arch/loongarch64/head.rs +++ b/components/someboot/src/arch/loongarch64/head.rs @@ -2,7 +2,7 @@ use core::arch::naked_asm; // use super::entry::kernel_entry; use crate::{ - arch::addrspace::KERNEL_LOAD_ADDRESS, + arch::addrspace::{EFI_IMAGE_BASE, KERNEL_LOAD_ADDRESS}, efi_stub::{efi_pe_entry, pe::*}, }; @@ -48,7 +48,7 @@ pub unsafe extern "C" fn _head() { ".long _stext - _head", // BaseOfCode // Extra header fields - ".quad {phys_link_kaddr}", // ImageBase + ".quad {efi_image_base}", // ImageBase ".long PAGE_SIZE", // SectionAlignment (PECOFF_SEGMENT_ALIGN) ".long PECOFF_FILE_ALIGN", // FileAlignment (PECOFF_FILE_ALIGN) ".short 0", // MajorOperatingSystemVersion @@ -110,6 +110,7 @@ pub unsafe extern "C" fn _head() { dos_signature = const IMAGE_DOS_SIGNATURE, linux_pe_magic = const LINUX_PE_MAGIC, phys_link_kaddr = const KERNEL_LOAD_ADDRESS, + efi_image_base = const EFI_IMAGE_BASE, efi_pe_entry = sym efi_pe_entry, image_nt_signature = const IMAGE_NT_SIGNATURE, file_machine = const IMAGE_FILE_MACHINE_LOONGARCH64, diff --git a/os/axvisor/configs/board/qemu-loongarch64.toml b/os/axvisor/configs/board/qemu-loongarch64.toml index fd43046e26..a9806cfa2d 100644 --- a/os/axvisor/configs/board/qemu-loongarch64.toml +++ b/os/axvisor/configs/board/qemu-loongarch64.toml @@ -11,3 +11,4 @@ vm_configs = [] [env] KERNEL_BUILTIN_CMDLINE = "root=/dev/vda earlycon=uart8250,mmio,0x1fe001e0,115200" +SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR = "0x80000000" From 6f3451269afd302794207b56b9735ac7c052b748 Mon Sep 17 00:00:00 2001 From: szy Date: Fri, 26 Jun 2026 13:55:59 +0800 Subject: [PATCH 45/50] fix(axvisor): restore LoongArch guest boot after rebase --- scripts/axbuild/src/test/host_http.rs | 4 +- virtualization/axdevice/src/device.rs | 7 +-- virtualization/axvm/src/vm.rs | 72 +++++++++++++++++++++++---- 3 files changed, 68 insertions(+), 15 deletions(-) diff --git a/scripts/axbuild/src/test/host_http.rs b/scripts/axbuild/src/test/host_http.rs index ffc3068574..2821de7b68 100644 --- a/scripts/axbuild/src/test/host_http.rs +++ b/scripts/axbuild/src/test/host_http.rs @@ -271,7 +271,9 @@ fn write_dir_response(stream: &mut impl Write, status: &str, content_type: &str, body.len(), ); if stream.write_all(head.as_bytes()).is_ok() { - let _ = write_body_chunks(stream, body.len(), |offset, len| &body[offset..offset + len]); + let _ = write_body_chunks(stream, body.len(), |offset, len| { + &body[offset..offset + len] + }); } } diff --git a/virtualization/axdevice/src/device.rs b/virtualization/axdevice/src/device.rs index 66f7aebb4a..1c5677afdd 100644 --- a/virtualization/axdevice/src/device.rs +++ b/virtualization/axdevice/src/device.rs @@ -967,9 +967,10 @@ impl AxVmDevices { /// Add a QEMU fw_cfg MMIO device to the device list. pub fn add_fw_cfg_dev(&mut self, dev: Arc) -> AxResult { - self.register(MmioDeviceAdapter::from_arc(dev.clone()) - as Arc) - .map_err(|e| ax_err_type!(InvalidInput, format!("register fw_cfg: {e:?}")))?; + self.register( + MmioDeviceAdapter::from_arc(dev.clone()) as Arc + ) + .map_err(|e| ax_err_type!(InvalidInput, format!("register fw_cfg: {e:?}")))?; self.fw_cfg = Some(dev); Ok(()) } diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index c44049d973..6f8c8abe51 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -464,6 +464,7 @@ impl AxVM { passthrough_timer: passthrough, boot_args: inner_mut.config.cpu_config.boot_args, boot_stack_top: inner_mut.config.cpu_config.boot_stack_top, + firmware_boot: inner_mut.config.cpu_config.firmware_boot, } }; #[cfg(not(any( @@ -646,7 +647,7 @@ impl AxVM { pub(crate) fn loongarch_external_irq_vector( &self, fallback_vector: usize, - physical_irq: usize, + _physical_irq: usize, ) -> Option { match self .get_devices() @@ -744,7 +745,6 @@ impl AxVM { FwCfgPlatformConfig::default() } - /// Run a vCPU according to the given vcpu_id. /// /// ## Arguments @@ -836,7 +836,8 @@ impl AxVM { reg_width, signed_ext, } => { - let raw = self.get_devices().handle_mmio_read(addr, width)?; + let raw = + self.get_devices().handle_mmio_read(addr, width)?; let masked = raw & width_mask(width); let val = if signed_ext { sign_extend_value(masked, width) @@ -1133,6 +1134,32 @@ impl AxVM { } } + /// Reads raw bytes from guest physical memory. + pub fn read_from_guest(&self, gpa_ptr: GuestPhysAddr, buffer: &mut [u8]) -> AxResult { + let g = self.inner_mut.lock(); + let Some(chunks) = g + .address_space + .translated_byte_buffer(gpa_ptr, buffer.len()) + else { + return ax_err!(InvalidInput, "Failed to translate guest physical address"); + }; + + let mut copied = 0; + for chunk in chunks { + let len = (buffer.len() - copied).min(chunk.len()); + buffer[copied..copied + len].copy_from_slice(&chunk[..len]); + copied += len; + if copied == buffer.len() { + return Ok(()); + } + } + + ax_err!( + InvalidInput, + "Insufficient guest memory to read the requested buffer" + ) + } + /// Writes an object of type `T` to the guest physical address. pub fn write_to_guest_of(&self, gpa_ptr: GuestPhysAddr, data: &T) -> AxResult { match self @@ -1160,6 +1187,30 @@ impl AxVM { } } + /// Writes raw bytes into guest physical memory. + pub fn write_to_guest(&self, gpa_ptr: GuestPhysAddr, data: &[u8]) -> AxResult { + let g = self.inner_mut.lock(); + let Some(mut chunks) = g.address_space.translated_byte_buffer(gpa_ptr, data.len()) else { + return ax_err!(InvalidInput, "Failed to translate guest physical address"); + }; + + let mut copied = 0; + for chunk in chunks.iter_mut() { + let len = (data.len() - copied).min(chunk.len()); + chunk[..len].copy_from_slice(&data[copied..copied + len]); + crate::clean_dcache_range((chunk.as_ptr() as usize).into(), len); + copied += len; + if copied == data.len() { + return Ok(()); + } + } + + ax_err!( + InvalidInput, + "Insufficient guest memory to write the requested buffer" + ) + } + /// Allocates an IVC channel for inter-VM communication region. /// /// ## Arguments @@ -1233,29 +1284,28 @@ impl AxVM { &self, layout: Layout, gpa: Option, - ) -> AxResult<&[u8]> { + ) -> AxResult { assert!( layout.size() > 0, "Cannot allocate zero-sized memory region" ); + let gpa = + gpa.ok_or_else(|| ax_err_type!(InvalidInput, "Reserved memory GPA is required"))?; let mut g = self.inner_mut.lock(); g.address_space.map_linear( - gpa.unwrap(), - gpa.unwrap().as_usize().into(), + gpa, + gpa.as_usize().into(), layout.size(), MappingFlags::READ | MappingFlags::WRITE | MappingFlags::EXECUTE | MappingFlags::USER, )?; - let hva = gpa.unwrap().as_usize().into(); - let tem_hva = gpa.unwrap().as_usize() as *mut u8; - let s = unsafe { core::slice::from_raw_parts_mut(tem_hva, layout.size()) }; - let gpa = gpa.unwrap(); + let hva = gpa.as_usize().into(); g.memory_regions.push(VMMemoryRegion { gpa, hva, layout, needs_dealloc: false, // This is a reserved region, not allocated }); - Ok(s) + Ok(()) } /// Cleanup resources for the VM before drop. From dcb9feb2c52b1e14c1eafab86e4ca8c0e886e4e4 Mon Sep 17 00:00:00 2001 From: szy Date: Fri, 26 Jun 2026 14:56:09 +0800 Subject: [PATCH 46/50] fix(someboot): use hv for LoongArch load address --- components/someboot/build.rs | 6 +++--- os/axvisor/configs/board/qemu-loongarch64.toml | 1 - 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/components/someboot/build.rs b/components/someboot/build.rs index d603960fb3..4be24a1b28 100644 --- a/components/someboot/build.rs +++ b/components/someboot/build.rs @@ -117,9 +117,9 @@ impl Build { } fn prepare_loongarch64(&mut self) { - if let Some(kernel_paddr) = env_u64("SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR") { - self.kernel_paddr = kernel_paddr; - self.efi_image_base = kernel_paddr; + if self.hv { + self.kernel_paddr = 0x8000_0000; + self.efi_image_base = self.kernel_paddr; } self.kernel_vaddr = 0xffff_ffff_8000_0000; diff --git a/os/axvisor/configs/board/qemu-loongarch64.toml b/os/axvisor/configs/board/qemu-loongarch64.toml index a9806cfa2d..fd43046e26 100644 --- a/os/axvisor/configs/board/qemu-loongarch64.toml +++ b/os/axvisor/configs/board/qemu-loongarch64.toml @@ -11,4 +11,3 @@ vm_configs = [] [env] KERNEL_BUILTIN_CMDLINE = "root=/dev/vda earlycon=uart8250,mmio,0x1fe001e0,115200" -SOMEBOOT_LOONGARCH64_KERNEL_LOAD_PADDR = "0x80000000" From 4c1ec3b2a88e1a4569d27895f86924f9a93559d8 Mon Sep 17 00:00:00 2001 From: szy Date: Fri, 26 Jun 2026 15:47:40 +0800 Subject: [PATCH 47/50] refactor(axvm): move LoongArch HV IRQ routing into runtime --- .claude/skills/arch-platform-porting/SKILL.md | 1 + Cargo.lock | 1 + components/someboot/src/acpi/earlycon.rs | 2 - os/arceos/modules/axhal/src/lib.rs | 35 ----- os/axvisor/src/manager.rs | 22 +-- platforms/ax-plat/src/irq.rs | 52 +------ platforms/ax-plat/src/irq/loongarch64_hv.rs | 19 +++ platforms/axplat-dyn/src/irq.rs | 146 +----------------- .../axplat-dyn/src/irq/loongarch64_hv.rs | 132 ++++++++++++++++ virtualization/axvm/Cargo.toml | 1 + virtualization/axvm/src/arch.rs | 25 ++- virtualization/axvm/src/host/arceos.rs | 5 + virtualization/axvm/src/lib.rs | 5 + .../axvm/src/runtime/loongarch_irq.rs | 40 +++++ virtualization/axvm/src/runtime/mod.rs | 2 + 15 files changed, 234 insertions(+), 254 deletions(-) create mode 100644 platforms/ax-plat/src/irq/loongarch64_hv.rs create mode 100644 platforms/axplat-dyn/src/irq/loongarch64_hv.rs create mode 100644 virtualization/axvm/src/runtime/loongarch_irq.rs diff --git a/.claude/skills/arch-platform-porting/SKILL.md b/.claude/skills/arch-platform-porting/SKILL.md index 25ccac9daf..86e1e418d5 100644 --- a/.claude/skills/arch-platform-porting/SKILL.md +++ b/.claude/skills/arch-platform-porting/SKILL.md @@ -29,6 +29,7 @@ Current Axvisor LoongArch QEMU bring-up uses the dynamic UEFI platform path. The - **Platform bridge**: update `platforms/axplat-dyn`, `platforms/somehal`, platform config, memory regions, IRQ routing, timer source, power operations, and CPU boot operations. - **Runtime platform identity**: dynamic platform names should be discovered in `someboot`/`somehal` from firmware data, then exposed through `axplat-dyn` and `ax_plat::platform::platform_name()`. Keep `ax-hal` as a forwarding layer for platform identity, and keep static platforms returning `config::PLATFORM`. - **Runtime IRQ ownership**: ArceOS runtime IRQ traps are owned by `ax-cpu` and dispatched through `ax_hal::irq::handle_irq`. `somehal` must stay OS-free and expose controller transactions through `somehal::irq::begin_irq(raw) -> ActiveIrq`; `ActiveIrq` is held while `axplat-dyn` dispatches the IRQ and its `Drop` performs the architecture-specific EOI/complete. Do not reintroduce `_someboot_handle_irq` or `#[somehal::irq_handler]` as runtime dispatch glue. +- **LoongArch HV IRQ routing**: LoongArch guest passthrough IRQ routing is owned by AxVM, not by the generic `axhal` facade. Keep VM route registration/removal in the AxVM runtime lifecycle, keep the dynamic platform side limited to the `ax_plat::irq` LoongArch HV interface implementation, and avoid adding LoongArch guest IRQ policy helpers to public cross-arch `axhal` modules. - **Runtime console selection**: Dynamic platforms expose the firmware-selected hardware console through `somehal::console_device_id()` and `ax_hal::console::device_id()`. The value is `Result` derived from bootargs `console=`, ACPI SPCR, or FDT `stdout-path`; static platforms return `Err(NotSpecified)`. OS code such as Starry should match `Ok(id)` against probed serial devices, use `ttyS0` as the Linux-style hardware-console fallback only for `Err(NotSpecified)`, and leave `/dev/console` unbound (`ENODEV`) for non-hardware console selections, unmatched selected hardware devices, or when no serial console TTY exists. Do not reparse FDT or bootargs in the tty layer. - **Runtime console ownership**: once Starry or another OS runtime binds the firmware-selected UART to an interrupt-driven tty/serial driver, call `ax_hal::console::claim_runtime_output()` and stop the low-level boot/platform console path from writing the same UART registers directly. The hardware console must have one runtime register owner; otherwise kernel log output and tty output can interleave at the UART register level and corrupt test markers or user input/output. - **Dynamic firmware devices**: for `rdrive` ACPI probes, real non-empty ACPI ID lists enumerate namespace `Device` nodes and expose `_CRS` memory, I/O port, and IRQ resources through `AcpiInfo`; empty ID lists or synthetic root IDs are reserved for root-table style callbacks. diff --git a/Cargo.lock b/Cargo.lock index 44f32145fc..db0dcbd903 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -1568,6 +1568,7 @@ dependencies = [ "ax-page-table-entry", "ax-page-table-multiarch", "ax-percpu", + "ax-plat", "ax-std", "ax-timer-list", "axaddrspace", diff --git a/components/someboot/src/acpi/earlycon.rs b/components/someboot/src/acpi/earlycon.rs index ea5a096654..859ea69677 100644 --- a/components/someboot/src/acpi/earlycon.rs +++ b/components/someboot/src/acpi/earlycon.rs @@ -46,8 +46,6 @@ fn deal_with_spsr(spsr: &PhysicalMapping) -> Option<()> { let (vaddr, is_mmio) = match spsr.interface_type() { acpi::sdt::spcr::SpcrInterfaceType::Full16550 - | acpi::sdt::spcr::SpcrInterfaceType::Full16450 - | acpi::sdt::spcr::SpcrInterfaceType::Nvidia16550 | acpi::sdt::spcr::SpcrInterfaceType::Generic16550 => match base_address.address_space { AddressSpace::SystemIo => { #[cfg(target_arch = "x86_64")] diff --git a/os/arceos/modules/axhal/src/lib.rs b/os/arceos/modules/axhal/src/lib.rs index 4401345d07..c503ed6fc3 100644 --- a/os/arceos/modules/axhal/src/lib.rs +++ b/os/arceos/modules/axhal/src/lib.rs @@ -50,41 +50,6 @@ pub mod tls; #[cfg(feature = "irq")] pub mod irq; -#[cfg(all( - target_arch = "loongarch64", - feature = "irq", - ax_hal_any_platform_feature -))] -pub mod loongarch64_hv_irq { - const EIOINTC_IRQ: usize = 3; - - pub fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { - ax_plat::irq::register_loongarch_virtual_irq_injector(injector); - } - - pub fn enable_external_irq_line() { - crate::irq::set_enable(EIOINTC_IRQ, true); - } - - pub fn register_guest_irq_route( - physical_irq: usize, - vm_id: usize, - vcpu_id: usize, - guest_vector: usize, - ) { - ax_plat::irq::register_loongarch_guest_irq_route( - physical_irq, - vm_id, - vcpu_id, - guest_vector, - ); - } - - pub fn unregister_guest_irq_routes(vm_id: usize) { - ax_plat::irq::unregister_loongarch_guest_irq_routes(vm_id); - } -} - #[cfg(feature = "paging")] pub mod paging; diff --git a/os/axvisor/src/manager.rs b/os/axvisor/src/manager.rs index f3642d4960..6211673101 100644 --- a/os/axvisor/src/manager.rs +++ b/os/axvisor/src/manager.rs @@ -22,13 +22,6 @@ pub struct AxvmManager { impl AxvmManager { /// Initialize the AxVM runtime services. pub fn new() -> AxResult { - #[cfg(target_arch = "loongarch64")] - { - ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::register_virtual_irq_injector( - inject_loongarch_platform_irq, - ); - ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::enable_external_irq_line(); - } Ok(Self { runtime: AxvmRuntime::new()?, }) @@ -226,17 +219,6 @@ impl AxvmManager { } } -#[cfg(target_arch = "loongarch64")] -fn inject_loongarch_platform_irq(vm_id: usize, vcpu_id: usize, vector: usize, physical_irq: usize) { - if let Err(err) = axvm::inject_vm_vcpu_external_interrupt(vm_id, vcpu_id, vector, physical_irq) - { - warn!( - "failed to inject LoongArch platform IRQ {vector:#x}/physical {physical_irq:#x} for \ - VM[{vm_id}] VCpu[{vcpu_id}]: {err:?}" - ); - } -} - #[cfg(target_arch = "loongarch64")] pub(crate) fn register_loongarch_passthrough_irq_routes(vm_id: VMId) { let routes = crate::guest_platform::loongarch64::get_guest_irq_routes(vm_id); @@ -258,7 +240,7 @@ pub(crate) fn register_loongarch_passthrough_irq_routes(vm_id: VMId) { routes.len() ); for route in routes { - ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::register_guest_irq_route( + axvm::register_loongarch_guest_irq_route( route.physical_irq, vm_id, vcpu_id, @@ -269,5 +251,5 @@ pub(crate) fn register_loongarch_passthrough_irq_routes(vm_id: VMId) { #[cfg(target_arch = "loongarch64")] fn unregister_loongarch_passthrough_irq_routes(vm_id: VMId) { - ax_std::os::arceos::modules::ax_hal::loongarch64_hv_irq::unregister_guest_irq_routes(vm_id); + axvm::unregister_loongarch_guest_irq_routes(vm_id); } diff --git a/platforms/ax-plat/src/irq.rs b/platforms/ax-plat/src/irq.rs index 325fd1f8b0..6a8505e0af 100644 --- a/platforms/ax-plat/src/irq.rs +++ b/platforms/ax-plat/src/irq.rs @@ -10,6 +10,11 @@ pub use irq_framework::{ }; use spin::Once; +#[cfg(target_arch = "loongarch64")] +pub mod loongarch64_hv; +#[cfg(target_arch = "loongarch64")] +pub use loongarch64_hv::LoongArchHvIrqIf; + /// Raw synchronous cross-CPU call used by the IRQ registry. pub type RunOnCpuSync = unsafe fn(usize, unsafe fn(*mut ()), *mut ()) -> Result<(), IrqError>; @@ -269,50 +274,3 @@ pub trait IrqIf { /// Sends an inter-processor interrupt (IPI) to the specified target CPU or all CPUs. fn send_ipi(irq_num: usize, target: IpiTarget); } - -/// LoongArch hypervisor IRQ routing extension. -#[cfg(target_arch = "loongarch64")] -#[def_plat_interface] -pub trait LoongArchHvIrqIf { - /// Registers the virtual interrupt injector used by hypervisor builds. - fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)); - - /// Routes one physical EIOINTC/PCH-PIC IRQ to a guest CPU interrupt vector. - fn register_guest_irq_route( - physical_irq: usize, - vm_id: usize, - vcpu_id: usize, - guest_vector: usize, - ); - - /// Removes all guest IRQ routes owned by one VM. - fn unregister_guest_irq_routes(vm_id: usize); -} - -/// Registers the virtual interrupt injector used by LoongArch hypervisor builds. -#[cfg(target_arch = "loongarch64")] -pub fn register_loongarch_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { - crate::__priv::call_interface!(LoongArchHvIrqIf::register_virtual_irq_injector(injector)); -} - -/// Routes one physical EIOINTC/PCH-PIC IRQ to a LoongArch guest CPU interrupt vector. -#[cfg(target_arch = "loongarch64")] -pub fn register_loongarch_guest_irq_route( - physical_irq: usize, - vm_id: usize, - vcpu_id: usize, - guest_vector: usize, -) { - crate::__priv::call_interface!(LoongArchHvIrqIf::register_guest_irq_route( - physical_irq, - vm_id, - vcpu_id, - guest_vector - )); -} - -/// Removes all LoongArch guest IRQ routes owned by one VM. -#[cfg(target_arch = "loongarch64")] -pub fn unregister_loongarch_guest_irq_routes(vm_id: usize) { - crate::__priv::call_interface!(LoongArchHvIrqIf::unregister_guest_irq_routes(vm_id)); -} diff --git a/platforms/ax-plat/src/irq/loongarch64_hv.rs b/platforms/ax-plat/src/irq/loongarch64_hv.rs new file mode 100644 index 0000000000..02f166b3b8 --- /dev/null +++ b/platforms/ax-plat/src/irq/loongarch64_hv.rs @@ -0,0 +1,19 @@ +//! LoongArch hypervisor IRQ routing extension. + +/// LoongArch hypervisor IRQ routing extension. +#[def_plat_interface] +pub trait LoongArchHvIrqIf { + /// Registers the virtual interrupt injector used by hypervisor builds. + fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)); + + /// Routes one physical EIOINTC/PCH-PIC IRQ to a guest CPU interrupt vector. + fn register_guest_irq_route( + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, + ); + + /// Removes all guest IRQ routes owned by one VM. + fn unregister_guest_irq_routes(vm_id: usize); +} diff --git a/platforms/axplat-dyn/src/irq.rs b/platforms/axplat-dyn/src/irq.rs index 1697df6494..382cee4bd0 100644 --- a/platforms/axplat-dyn/src/irq.rs +++ b/platforms/axplat-dyn/src/irq.rs @@ -1,40 +1,17 @@ -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -use core::sync::atomic::{AtomicPtr, AtomicUsize, Ordering}; #[cfg(all(target_arch = "riscv64", feature = "hv"))] use core::sync::atomic::{AtomicPtr, Ordering}; use ax_plat::irq::{IrqAffinity, IrqError, IrqIf, dispatch_irq}; +#[cfg(all(target_arch = "loongarch64", feature = "hv"))] +mod loongarch64_hv; + #[cfg(all(target_arch = "riscv64", feature = "hv"))] const RISCV_INTERRUPT_BIT: usize = 1usize << (usize::BITS as usize - 1); #[cfg(all(target_arch = "riscv64", feature = "hv"))] static VIRTUAL_IRQ_INJECTOR: AtomicPtr<()> = AtomicPtr::new(core::ptr::null_mut()); -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -const LOONGARCH_MAX_IRQ_COUNT: usize = 256; -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -const IRQ_ROUTE_NONE: usize = 0; -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -const IRQ_TARGET_NONE: usize = usize::MAX; -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -const IRQ_TARGET_VM_SHIFT: usize = 32; -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -const LOONGARCH_IRQ_TRACE_LIMIT: usize = 80; - -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -static LOONGARCH_VIRTUAL_IRQ_INJECTOR: AtomicPtr<()> = AtomicPtr::new(core::ptr::null_mut()); -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -static LOONGARCH_GUEST_IRQ_ROUTES: [AtomicUsize; LOONGARCH_MAX_IRQ_COUNT] = - [const { AtomicUsize::new(IRQ_ROUTE_NONE) }; LOONGARCH_MAX_IRQ_COUNT]; -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -static LOONGARCH_GUEST_IRQ_TARGETS: [AtomicUsize; LOONGARCH_MAX_IRQ_COUNT] = - [const { AtomicUsize::new(IRQ_TARGET_NONE) }; LOONGARCH_MAX_IRQ_COUNT]; -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -static LOONGARCH_IRQ_MISS_LOGS: AtomicUsize = AtomicUsize::new(0); -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -static LOONGARCH_IRQ_INJECT_LOGS: AtomicUsize = AtomicUsize::new(0); - #[cfg(all(target_arch = "riscv64", feature = "hv"))] pub fn register_virtual_irq_injector(injector: fn(usize) -> bool) { VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); @@ -72,7 +49,7 @@ impl IrqIf for IrqIfImpl { let outcome = dispatch_irq(irq_num); if !outcome.handled { #[cfg(all(target_arch = "loongarch64", feature = "hv"))] - if inject_loongarch_virtual_irq(irq_num) { + if loongarch64_hv::inject_virtual_irq(irq_num) { return Some(irq_num); } @@ -101,61 +78,6 @@ impl IrqIf for IrqIfImpl { } } -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -#[impl_plat_interface] -impl ax_plat::irq::LoongArchHvIrqIf for IrqIfImpl { - fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { - LOONGARCH_VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); - debug!("LoongArch dynamic platform virtual IRQ injector registered"); - } - - fn register_guest_irq_route( - physical_irq: usize, - vm_id: usize, - vcpu_id: usize, - guest_vector: usize, - ) { - if physical_irq >= LOONGARCH_MAX_IRQ_COUNT { - warn!("LoongArch guest IRQ route ignored: physical IRQ {physical_irq} out of range"); - return; - } - - let target = (vm_id << IRQ_TARGET_VM_SHIFT) | vcpu_id; - let previous_target = LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); - if previous_target != IRQ_TARGET_NONE && previous_target != target { - warn!( - "LoongArch guest IRQ route conflict: physical_irq={} is already routed to encoded \ - target {:#x}, ignoring VM[{}] VCpu[{}]", - physical_irq, previous_target, vm_id, vcpu_id - ); - return; - } - - LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].store(target, Ordering::Release); - LOONGARCH_GUEST_IRQ_ROUTES[physical_irq].store(guest_vector + 1, Ordering::Release); - somehal::irq::irq_set_enable(physical_irq.into(), true); - debug!( - "LoongArch dynamic guest IRQ route: physical_irq={}, target=VM[{}] VCpu[{}], \ - guest_vector={}", - physical_irq, vm_id, vcpu_id, guest_vector - ); - } - - fn unregister_guest_irq_routes(vm_id: usize) { - for physical_irq in 0..LOONGARCH_MAX_IRQ_COUNT { - let target = LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); - if target == IRQ_TARGET_NONE || (target >> IRQ_TARGET_VM_SHIFT) != vm_id { - continue; - } - - LOONGARCH_GUEST_IRQ_ROUTES[physical_irq].store(IRQ_ROUTE_NONE, Ordering::Release); - LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].store(IRQ_TARGET_NONE, Ordering::Release); - somehal::irq::irq_set_enable(physical_irq.into(), false); - debug!("LoongArch dynamic guest IRQ route removed: physical_irq={physical_irq}"); - } - } -} - #[cfg(all(target_arch = "riscv64", feature = "hv"))] fn inject_virtual_irq(irq: usize) -> bool { let injector = VIRTUAL_IRQ_INJECTOR.load(Ordering::Acquire); @@ -165,63 +87,3 @@ fn inject_virtual_irq(irq: usize) -> bool { } unsafe { core::mem::transmute::<*mut (), fn(usize) -> bool>(injector)(irq) } } - -#[cfg(all(target_arch = "loongarch64", feature = "hv"))] -fn inject_loongarch_virtual_irq(physical_irq: usize) -> bool { - if physical_irq >= LOONGARCH_MAX_IRQ_COUNT { - if LOONGARCH_IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { - trace!( - "LoongArch guest IRQ route miss: physical_irq={} out of range", - physical_irq - ); - } - return false; - } - - let encoded_vector = LOONGARCH_GUEST_IRQ_ROUTES[physical_irq].load(Ordering::Acquire); - if encoded_vector == IRQ_ROUTE_NONE { - if LOONGARCH_IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { - trace!( - "LoongArch guest IRQ route miss: physical_irq={} has no route", - physical_irq - ); - } - return false; - } - - let encoded_target = LOONGARCH_GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); - if encoded_target == IRQ_TARGET_NONE { - if LOONGARCH_IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { - trace!( - "LoongArch guest IRQ route miss: physical_irq={} has no target", - physical_irq - ); - } - return false; - } - - let injector = LOONGARCH_VIRTUAL_IRQ_INJECTOR.load(Ordering::Acquire); - if injector.is_null() { - warn!("LoongArch virtual IRQ injector is not registered"); - return false; - } - - let guest_vector = encoded_vector - 1; - let vm_id = encoded_target >> IRQ_TARGET_VM_SHIFT; - let vcpu_id = encoded_target & ((1usize << IRQ_TARGET_VM_SHIFT) - 1); - if LOONGARCH_IRQ_INJECT_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { - trace!( - "LoongArch guest IRQ inject: physical_irq={} -> VM[{}] VCpu[{}] guest_vector={}", - physical_irq, vm_id, vcpu_id, guest_vector - ); - } - unsafe { - core::mem::transmute::<*mut (), fn(usize, usize, usize, usize)>(injector)( - vm_id, - vcpu_id, - guest_vector, - physical_irq, - ); - } - true -} diff --git a/platforms/axplat-dyn/src/irq/loongarch64_hv.rs b/platforms/axplat-dyn/src/irq/loongarch64_hv.rs new file mode 100644 index 0000000000..eb4c7169c1 --- /dev/null +++ b/platforms/axplat-dyn/src/irq/loongarch64_hv.rs @@ -0,0 +1,132 @@ +use core::sync::atomic::{AtomicPtr, AtomicUsize, Ordering}; + +use ax_plat::irq::LoongArchHvIrqIf; + +use super::IrqIfImpl; + +const LOONGARCH_MAX_IRQ_COUNT: usize = 256; +const IRQ_ROUTE_NONE: usize = 0; +const IRQ_TARGET_NONE: usize = usize::MAX; +const IRQ_TARGET_VM_SHIFT: usize = 32; +const LOONGARCH_IRQ_TRACE_LIMIT: usize = 80; + +static VIRTUAL_IRQ_INJECTOR: AtomicPtr<()> = AtomicPtr::new(core::ptr::null_mut()); +static GUEST_IRQ_ROUTES: [AtomicUsize; LOONGARCH_MAX_IRQ_COUNT] = + [const { AtomicUsize::new(IRQ_ROUTE_NONE) }; LOONGARCH_MAX_IRQ_COUNT]; +static GUEST_IRQ_TARGETS: [AtomicUsize; LOONGARCH_MAX_IRQ_COUNT] = + [const { AtomicUsize::new(IRQ_TARGET_NONE) }; LOONGARCH_MAX_IRQ_COUNT]; +static IRQ_MISS_LOGS: AtomicUsize = AtomicUsize::new(0); +static IRQ_INJECT_LOGS: AtomicUsize = AtomicUsize::new(0); + +#[impl_plat_interface] +impl LoongArchHvIrqIf for IrqIfImpl { + fn register_virtual_irq_injector(injector: fn(usize, usize, usize, usize)) { + VIRTUAL_IRQ_INJECTOR.store(injector as *mut (), Ordering::Release); + debug!("LoongArch dynamic platform virtual IRQ injector registered"); + } + + fn register_guest_irq_route( + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, + ) { + if physical_irq >= LOONGARCH_MAX_IRQ_COUNT { + warn!("LoongArch guest IRQ route ignored: physical IRQ {physical_irq} out of range"); + return; + } + + let target = (vm_id << IRQ_TARGET_VM_SHIFT) | vcpu_id; + let previous_target = GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); + if previous_target != IRQ_TARGET_NONE && previous_target != target { + warn!( + "LoongArch guest IRQ route conflict: physical_irq={} is already routed to encoded \ + target {:#x}, ignoring VM[{}] VCpu[{}]", + physical_irq, previous_target, vm_id, vcpu_id + ); + return; + } + + GUEST_IRQ_TARGETS[physical_irq].store(target, Ordering::Release); + GUEST_IRQ_ROUTES[physical_irq].store(guest_vector + 1, Ordering::Release); + somehal::irq::irq_set_enable(physical_irq.into(), true); + debug!( + "LoongArch dynamic guest IRQ route: physical_irq={}, target=VM[{}] VCpu[{}], \ + guest_vector={}", + physical_irq, vm_id, vcpu_id, guest_vector + ); + } + + fn unregister_guest_irq_routes(vm_id: usize) { + for physical_irq in 0..LOONGARCH_MAX_IRQ_COUNT { + let target = GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); + if target == IRQ_TARGET_NONE || (target >> IRQ_TARGET_VM_SHIFT) != vm_id { + continue; + } + + GUEST_IRQ_ROUTES[physical_irq].store(IRQ_ROUTE_NONE, Ordering::Release); + GUEST_IRQ_TARGETS[physical_irq].store(IRQ_TARGET_NONE, Ordering::Release); + somehal::irq::irq_set_enable(physical_irq.into(), false); + debug!("LoongArch dynamic guest IRQ route removed: physical_irq={physical_irq}"); + } + } +} + +pub(super) fn inject_virtual_irq(physical_irq: usize) -> bool { + if physical_irq >= LOONGARCH_MAX_IRQ_COUNT { + if IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { + trace!( + "LoongArch guest IRQ route miss: physical_irq={} out of range", + physical_irq + ); + } + return false; + } + + let encoded_vector = GUEST_IRQ_ROUTES[physical_irq].load(Ordering::Acquire); + if encoded_vector == IRQ_ROUTE_NONE { + if IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { + trace!( + "LoongArch guest IRQ route miss: physical_irq={} has no route", + physical_irq + ); + } + return false; + } + + let encoded_target = GUEST_IRQ_TARGETS[physical_irq].load(Ordering::Acquire); + if encoded_target == IRQ_TARGET_NONE { + if IRQ_MISS_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { + trace!( + "LoongArch guest IRQ route miss: physical_irq={} has no target", + physical_irq + ); + } + return false; + } + + let injector = VIRTUAL_IRQ_INJECTOR.load(Ordering::Acquire); + if injector.is_null() { + warn!("LoongArch virtual IRQ injector is not registered"); + return false; + } + + let guest_vector = encoded_vector - 1; + let vm_id = encoded_target >> IRQ_TARGET_VM_SHIFT; + let vcpu_id = encoded_target & ((1usize << IRQ_TARGET_VM_SHIFT) - 1); + if IRQ_INJECT_LOGS.fetch_add(1, Ordering::Relaxed) < LOONGARCH_IRQ_TRACE_LIMIT { + trace!( + "LoongArch guest IRQ inject: physical_irq={} -> VM[{}] VCpu[{}] guest_vector={}", + physical_irq, vm_id, vcpu_id, guest_vector + ); + } + unsafe { + core::mem::transmute::<*mut (), fn(usize, usize, usize, usize)>(injector)( + vm_id, + vcpu_id, + guest_vector, + physical_irq, + ); + } + true +} diff --git a/virtualization/axvm/Cargo.toml b/virtualization/axvm/Cargo.toml index 033cc8acec..3daf4fe308 100644 --- a/virtualization/axvm/Cargo.toml +++ b/virtualization/axvm/Cargo.toml @@ -62,6 +62,7 @@ axplat-dyn = { workspace = true, optional = true, default-features = false } riscv_vcpu = { workspace = true } riscv_vplic = { workspace = true } [target.'cfg(target_arch = "loongarch64")'.dependencies] +ax-plat = { workspace = true } loongarch_vcpu = { workspace = true } [target.'cfg(target_arch = "aarch64")'.dependencies] aarch64-cpu-ext = "0.1" diff --git a/virtualization/axvm/src/arch.rs b/virtualization/axvm/src/arch.rs index 741280ebf6..b6991ea9d4 100644 --- a/virtualization/axvm/src/arch.rs +++ b/virtualization/axvm/src/arch.rs @@ -179,14 +179,6 @@ mod riscv64 { } } -#[cfg(target_arch = "riscv64")] -pub(crate) fn register_platform_irq_injector() { - riscv64::register_platform_irq_injector(); -} - -#[cfg(not(target_arch = "riscv64"))] -pub(crate) fn register_platform_irq_injector() {} - #[cfg(target_arch = "loongarch64")] mod loongarch64 { use alloc::boxed::Box; @@ -253,8 +245,25 @@ mod loongarch64 { } } } + + pub(crate) fn register_platform_irq_injector() { + crate::runtime::loongarch_irq::register_platform_irq_injector(); + } } +#[cfg(target_arch = "riscv64")] +pub(crate) fn register_platform_irq_injector() { + riscv64::register_platform_irq_injector(); +} + +#[cfg(target_arch = "loongarch64")] +pub(crate) fn register_platform_irq_injector() { + loongarch64::register_platform_irq_injector(); +} + +#[cfg(not(any(target_arch = "riscv64", target_arch = "loongarch64")))] +pub(crate) fn register_platform_irq_injector() {} + #[cfg(target_arch = "aarch64")] mod aarch64 { use alloc::boxed::Box; diff --git a/virtualization/axvm/src/host/arceos.rs b/virtualization/axvm/src/host/arceos.rs index 8b56192b0b..e9766db161 100644 --- a/virtualization/axvm/src/host/arceos.rs +++ b/virtualization/axvm/src/host/arceos.rs @@ -127,6 +127,11 @@ pub(crate) fn dispatch_host_irq(vector: usize) { modules::ax_hal::irq::handle_irq(vector); } +#[cfg(target_arch = "loongarch64")] +pub(crate) fn set_irq_enabled(irq: usize, enabled: bool) { + modules::ax_hal::irq::set_enable(irq, enabled); +} + impl HostCpu for ArceOsHost { type CpuMask = api::task::AxCpuMask; diff --git a/virtualization/axvm/src/lib.rs b/virtualization/axvm/src/lib.rs index ebfbf6279a..10f79a8206 100644 --- a/virtualization/axvm/src/lib.rs +++ b/virtualization/axvm/src/lib.rs @@ -53,6 +53,11 @@ pub use manager::{ }; #[cfg(target_arch = "loongarch64")] pub use manager::{inject_vm_vcpu_external_interrupt, inject_vm_vcpu_interrupt}; +#[cfg(target_arch = "loongarch64")] +pub use runtime::loongarch_irq::{ + register_guest_irq_route as register_loongarch_guest_irq_route, + unregister_guest_irq_routes as unregister_loongarch_guest_irq_routes, +}; pub use task::{AsVCpuTask, VCpuTask}; pub use vm::{AxVCpuRef, AxVM, AxVMRef, FwCfgDeviceConfig, VMMemoryRegion, VMStatus}; diff --git a/virtualization/axvm/src/runtime/loongarch_irq.rs b/virtualization/axvm/src/runtime/loongarch_irq.rs new file mode 100644 index 0000000000..2040e974e8 --- /dev/null +++ b/virtualization/axvm/src/runtime/loongarch_irq.rs @@ -0,0 +1,40 @@ +//! LoongArch platform IRQ routing used by AxVM. + +const EIOINTC_IRQ: usize = 3; + +/// Register the platform IRQ injector for LoongArch dynamic hypervisor builds. +pub(crate) fn register_platform_irq_injector() { + ax_plat::irq::loongarch64_hv::register_virtual_irq_injector(inject_platform_irq); + crate::host::arceos::set_irq_enabled(EIOINTC_IRQ, true); +} + +/// Route a host physical IRQ to a LoongArch guest interrupt vector. +pub fn register_guest_irq_route( + physical_irq: usize, + vm_id: usize, + vcpu_id: usize, + guest_vector: usize, +) { + ax_plat::irq::loongarch64_hv::register_guest_irq_route( + physical_irq, + vm_id, + vcpu_id, + guest_vector, + ); +} + +/// Remove all routed LoongArch guest IRQs owned by one VM. +pub fn unregister_guest_irq_routes(vm_id: usize) { + ax_plat::irq::loongarch64_hv::unregister_guest_irq_routes(vm_id); +} + +fn inject_platform_irq(vm_id: usize, vcpu_id: usize, vector: usize, physical_irq: usize) { + if let Err(err) = + crate::runtime::vcpus::queue_external_interrupt(vm_id, vcpu_id, vector, physical_irq) + { + warn!( + "failed to queue LoongArch platform IRQ {vector:#x}/physical {physical_irq:#x} for \ + VM[{vm_id}] VCpu[{vcpu_id}]: {err:?}" + ); + } +} diff --git a/virtualization/axvm/src/runtime/mod.rs b/virtualization/axvm/src/runtime/mod.rs index e39d8c0cb7..2de93d28b4 100644 --- a/virtualization/axvm/src/runtime/mod.rs +++ b/virtualization/axvm/src/runtime/mod.rs @@ -15,6 +15,8 @@ mod hvc; mod ivc; +#[cfg(target_arch = "loongarch64")] +pub mod loongarch_irq; pub(crate) mod vcpus; #[cfg(target_arch = "x86_64")] mod x86_irq; From b354b66d05b17ce4613b796a032eb4af72010bbe Mon Sep 17 00:00:00 2001 From: szy Date: Fri, 26 Jun 2026 16:35:02 +0800 Subject: [PATCH 48/50] opt fdt --- .claude/skills/arch-platform-porting/SKILL.md | 1 - os/arceos/modules/axhal/build.rs | 4 - os/axvisor/scripts/qemu-lvz.version | 1 - os/axvisor/src/fdt/create.rs | 16 - .../loongarch64/guest_firmware_dtb.rs} | 2 +- .../fdt/loongarch64/guest_irq_route_dtb.rs | 354 +++++++++++++++++ os/axvisor/src/fdt/loongarch64/mod.rs | 2 + os/axvisor/src/fdt/mod.rs | 4 +- os/axvisor/src/fdt/parser.rs | 367 ------------------ .../src/guest_platform/loongarch64/mod.rs | 3 +- 10 files changed, 361 insertions(+), 393 deletions(-) rename os/axvisor/src/{guest_platform/loongarch64/firmware_fdt.rs => fdt/loongarch64/guest_firmware_dtb.rs} (99%) create mode 100644 os/axvisor/src/fdt/loongarch64/guest_irq_route_dtb.rs create mode 100644 os/axvisor/src/fdt/loongarch64/mod.rs diff --git a/.claude/skills/arch-platform-porting/SKILL.md b/.claude/skills/arch-platform-porting/SKILL.md index 86e1e418d5..25ccac9daf 100644 --- a/.claude/skills/arch-platform-porting/SKILL.md +++ b/.claude/skills/arch-platform-porting/SKILL.md @@ -29,7 +29,6 @@ Current Axvisor LoongArch QEMU bring-up uses the dynamic UEFI platform path. The - **Platform bridge**: update `platforms/axplat-dyn`, `platforms/somehal`, platform config, memory regions, IRQ routing, timer source, power operations, and CPU boot operations. - **Runtime platform identity**: dynamic platform names should be discovered in `someboot`/`somehal` from firmware data, then exposed through `axplat-dyn` and `ax_plat::platform::platform_name()`. Keep `ax-hal` as a forwarding layer for platform identity, and keep static platforms returning `config::PLATFORM`. - **Runtime IRQ ownership**: ArceOS runtime IRQ traps are owned by `ax-cpu` and dispatched through `ax_hal::irq::handle_irq`. `somehal` must stay OS-free and expose controller transactions through `somehal::irq::begin_irq(raw) -> ActiveIrq`; `ActiveIrq` is held while `axplat-dyn` dispatches the IRQ and its `Drop` performs the architecture-specific EOI/complete. Do not reintroduce `_someboot_handle_irq` or `#[somehal::irq_handler]` as runtime dispatch glue. -- **LoongArch HV IRQ routing**: LoongArch guest passthrough IRQ routing is owned by AxVM, not by the generic `axhal` facade. Keep VM route registration/removal in the AxVM runtime lifecycle, keep the dynamic platform side limited to the `ax_plat::irq` LoongArch HV interface implementation, and avoid adding LoongArch guest IRQ policy helpers to public cross-arch `axhal` modules. - **Runtime console selection**: Dynamic platforms expose the firmware-selected hardware console through `somehal::console_device_id()` and `ax_hal::console::device_id()`. The value is `Result` derived from bootargs `console=`, ACPI SPCR, or FDT `stdout-path`; static platforms return `Err(NotSpecified)`. OS code such as Starry should match `Ok(id)` against probed serial devices, use `ttyS0` as the Linux-style hardware-console fallback only for `Err(NotSpecified)`, and leave `/dev/console` unbound (`ENODEV`) for non-hardware console selections, unmatched selected hardware devices, or when no serial console TTY exists. Do not reparse FDT or bootargs in the tty layer. - **Runtime console ownership**: once Starry or another OS runtime binds the firmware-selected UART to an interrupt-driven tty/serial driver, call `ax_hal::console::claim_runtime_output()` and stop the low-level boot/platform console path from writing the same UART registers directly. The hardware console must have one runtime register owner; otherwise kernel log output and tty output can interleave at the UART register level and corrupt test markers or user input/output. - **Dynamic firmware devices**: for `rdrive` ACPI probes, real non-empty ACPI ID lists enumerate namespace `Device` nodes and expose `_CRS` memory, I/O port, and IRQ resources through `AcpiInfo`; empty ID lists or synthetic root IDs are reserved for root-table style callbacks. diff --git a/os/arceos/modules/axhal/build.rs b/os/arceos/modules/axhal/build.rs index 0052c2393d..4411c54baf 100644 --- a/os/arceos/modules/axhal/build.rs +++ b/os/arceos/modules/axhal/build.rs @@ -36,7 +36,6 @@ const DEFAULT_PLATFORMS: &[(&str, &str)] = &[("loongarch64", "ax_plat_loongarch6 fn main() { println!("cargo:rustc-check-cfg=cfg(plat_dyn)"); - println!("cargo:rustc-check-cfg=cfg(ax_hal_any_platform_feature)"); println!("cargo:rerun-if-changed={LINKER_TEMPLATE_NAME}"); println!("cargo:rerun-if-env-changed=AX_CONFIG_PATH"); println!("cargo:rerun-if-env-changed={}", feature_env("host-test")); @@ -134,9 +133,6 @@ fn gen_selected_platform(arch: &str, platform: Option<&PlatformFeature>) -> Resu if crate_name == Some("axplat_dyn") { println!("cargo:rustc-cfg=plat_dyn"); } - if crate_name.is_some() { - println!("cargo:rustc-cfg=ax_hal_any_platform_feature"); - } let content = crate_name .map(|crate_name| format!("extern crate {crate_name} as _;\n")) diff --git a/os/axvisor/scripts/qemu-lvz.version b/os/axvisor/scripts/qemu-lvz.version index f9b23d5cf6..4b69ad8368 100644 --- a/os/axvisor/scripts/qemu-lvz.version +++ b/os/axvisor/scripts/qemu-lvz.version @@ -1,3 +1,2 @@ QEMU_LVZ_REPO=https://github.com/Hengyu-Yu/QEMU-LVZ.git -QEMU_LVZ_VERSION=9.0.50 QEMU_LVZ_TARGET_LIST=loongarch64-softmmu diff --git a/os/axvisor/src/fdt/create.rs b/os/axvisor/src/fdt/create.rs index 434a629c6b..d41933dad9 100644 --- a/os/axvisor/src/fdt/create.rs +++ b/os/axvisor/src/fdt/create.rs @@ -590,11 +590,6 @@ pub fn update_fdt( vm: AxVMRef, crate_config: &AxVMCrateConfig, ) -> AxResult { - info!( - "Updating guest FDT for VM[{}], input size={:#x}", - vm.id(), - dtb_size - ); // Fix up the cached DTB against the runtime layout before boot. let fdt_bytes = unsafe { core::slice::from_raw_parts(fdt_src.as_ptr(), dtb_size) }; let fdt = Fdt::from_bytes(fdt_bytes).map_err(|e| { @@ -615,21 +610,10 @@ pub fn update_fdt( }) }) .transpose()?; - info!("Patching guest FDT runtime layout for VM[{}]", vm.id()); let new_fdt_bytes = patch_guest_fdt_for_runtime(&fdt, &vm.memory_regions(), crate_config, host_fdt.as_ref())?; // Recompute the DTB load address from the runtime memory layout. - info!( - "Patched guest FDT for VM[{}], output size={:#x}", - vm.id(), - new_fdt_bytes.len() - ); let dest_addr = calculate_dtb_load_addr(vm.clone(), new_fdt_bytes.len())?; - info!( - "Loading guest FDT for VM[{}] at {:#x}", - vm.id(), - dest_addr.as_usize() - ); load_vm_image_from_memory(&new_fdt_bytes, dest_addr, vm) } diff --git a/os/axvisor/src/guest_platform/loongarch64/firmware_fdt.rs b/os/axvisor/src/fdt/loongarch64/guest_firmware_dtb.rs similarity index 99% rename from os/axvisor/src/guest_platform/loongarch64/firmware_fdt.rs rename to os/axvisor/src/fdt/loongarch64/guest_firmware_dtb.rs index c3569348df..0fb2c5c72a 100644 --- a/os/axvisor/src/guest_platform/loongarch64/firmware_fdt.rs +++ b/os/axvisor/src/fdt/loongarch64/guest_firmware_dtb.rs @@ -2,8 +2,8 @@ use alloc::{format, vec}; use ax_errno::{AxError, AxResult, ax_err_type}; -use super::GuestPlatform; use crate::fdt::vm_fdt::FdtWriter; +use crate::guest_platform::loongarch64::GuestPlatform; const PHANDLE_CPU0: u32 = 0x8000; const PHANDLE_CPUIC: u32 = 0x8001; diff --git a/os/axvisor/src/fdt/loongarch64/guest_irq_route_dtb.rs b/os/axvisor/src/fdt/loongarch64/guest_irq_route_dtb.rs new file mode 100644 index 0000000000..6632159970 --- /dev/null +++ b/os/axvisor/src/fdt/loongarch64/guest_irq_route_dtb.rs @@ -0,0 +1,354 @@ +use alloc::{ + collections::{BTreeMap, BTreeSet}, + format, + vec::Vec, +}; + +use ax_errno::{AxResult, ax_err_type}; +use axvm::config::AxVMConfig; +use fdt_parser::{Fdt, Node, Status}; + +use crate::guest_platform::loongarch64::{ + LoongArchGuestIrqRoute, store_guest_irq_routes as store_loongarch_guest_irq_routes, +}; + +fn property_u32_list(node: &Node<'_>, name: &str) -> Vec { + node.find_property(name) + .map(|prop| prop.u32_list().collect()) + .unwrap_or_default() +} + +fn property_u32(node: &Node<'_>, name: &str) -> Option { + node.find_property(name) + .and_then(|prop| prop.u32_list().next()) +} + +fn node_phandle(node: &Node<'_>) -> Option { + node.phandle().map(|phandle| phandle.as_usize()) +} + +fn interrupt_parent_phandle(node: &Node<'_>) -> Option { + node.interrupt_parent() + .and_then(|parent| node_phandle(&parent.node)) +} + +fn node_interrupt_cells(node: &Node<'_>) -> usize { + property_u32(node, "#interrupt-cells").unwrap_or(1) as usize +} + +fn node_address_cells(node: &Node<'_>) -> usize { + property_u32(node, "#address-cells").unwrap_or(2) as usize +} + +fn has_compatible(node: &Node<'_>, needle: &str) -> bool { + node.compatibles().any(|compatible| compatible == needle) +} + +fn has_compatible_part(node: &Node<'_>, needle: &str) -> bool { + node.compatibles() + .any(|compatible| compatible.contains(needle)) +} + +fn is_interrupt_controller(node: &Node<'_>) -> bool { + node.find_property("interrupt-controller").is_some() +} + +fn is_enabled_node(node: &Node<'_>) -> bool { + !matches!(node.status(), Some(Status::Disabled)) +} + +fn interrupt_ids_for_parent(node: &Node<'_>, parent_phandle: usize) -> Vec { + if interrupt_parent_phandle(node) != Some(parent_phandle) { + return Vec::new(); + } + + node.interrupts() + .map(|interrupts| { + interrupts + .filter_map(|mut interrupt| interrupt.next().map(|id| id as usize)) + .collect() + }) + .unwrap_or_default() +} + +fn interrupts_extended_for_parent( + node: &Node<'_>, + phandle_nodes: &BTreeMap>, + parent_phandle: usize, +) -> Vec { + let cells = property_u32_list(node, "interrupts-extended"); + if cells.is_empty() { + return Vec::new(); + } + + let mut result = Vec::new(); + let mut index = 0usize; + while index < cells.len() { + let phandle = cells[index] as usize; + index += 1; + + let interrupt_cells = phandle_nodes + .get(&phandle) + .map(node_interrupt_cells) + .unwrap_or(1); + + if index + interrupt_cells > cells.len() { + warn!( + "LoongArch interrupts-extended in node {} has truncated tuple at cell {}", + node.name(), + index - 1 + ); + break; + } + + if phandle == parent_phandle && interrupt_cells > 0 { + result.push(cells[index] as usize); + } + index += interrupt_cells; + } + + result +} + +fn direct_interrupt_ids_for_parent( + node: &Node<'_>, + phandle_nodes: &BTreeMap>, + parent_phandle: usize, +) -> Vec { + let mut ids = interrupt_ids_for_parent(node, parent_phandle); + ids.extend(interrupts_extended_for_parent( + node, + phandle_nodes, + parent_phandle, + )); + ids +} + +fn first_direct_interrupt_id_for_parent( + node: &Node<'_>, + phandle_nodes: &BTreeMap>, + parent_phandle: usize, +) -> Option { + direct_interrupt_ids_for_parent(node, phandle_nodes, parent_phandle) + .into_iter() + .next() +} + +fn add_loongarch_irq_route( + routes: &mut BTreeSet, + physical_irq: usize, + guest_vector: usize, + source: &str, +) { + let route = LoongArchGuestIrqRoute { + physical_irq, + guest_vector, + }; + if routes.insert(route) { + debug!( + "LoongArch guest IRQ route from DTB: physical_irq={}, guest_vector={}, source={}", + physical_irq, guest_vector, source + ); + } +} + +fn parse_loongarch_pci_interrupt_map( + node: &Node<'_>, + phandle_nodes: &BTreeMap>, + pch_pic_phandle: usize, + pch_pic_base_vec: usize, + eiointc_guest_vector: usize, + routes: &mut BTreeSet, +) { + let interrupt_map = property_u32_list(node, "interrupt-map"); + if interrupt_map.is_empty() { + return; + } + + let child_address_cells = node_address_cells(node); + let child_interrupt_cells = node_interrupt_cells(node); + let child_cells = child_address_cells + child_interrupt_cells; + if child_cells == 0 { + warn!( + "LoongArch PCI interrupt-map in node {} has invalid child cell count", + node.name() + ); + return; + } + let mut index = 0usize; + + while index + child_cells < interrupt_map.len() { + let parent_phandle = interrupt_map[index + child_cells] as usize; + let Some(parent_node) = phandle_nodes.get(&parent_phandle) else { + warn!( + "LoongArch PCI interrupt-map parent phandle {:#x} not found in node {}", + parent_phandle, + node.name() + ); + break; + }; + let parent_interrupt_cells = + pci_interrupt_map_parent_cells(&interrupt_map, child_cells, parent_node); + let entry_cells = child_cells + 1 + parent_interrupt_cells; + if index + entry_cells > interrupt_map.len() { + warn!( + "LoongArch PCI interrupt-map in node {} has truncated entry at cell {}", + node.name(), + index + ); + break; + } + + if parent_phandle == pch_pic_phandle && parent_interrupt_cells > 0 { + let parent_irq = interrupt_map[index + child_cells + 1] as usize; + add_loongarch_irq_route( + routes, + pch_pic_base_vec + parent_irq, + eiointc_guest_vector, + node.name(), + ); + } + index += entry_cells; + } +} + +fn pci_interrupt_map_parent_cells( + interrupt_map: &[u32], + child_cells: usize, + parent_node: &Node<'_>, +) -> usize { + let default_parent_cells = node_interrupt_cells(parent_node); + let default_entry_cells = child_cells + 1 + default_parent_cells; + let one_cell_entry_cells = child_cells + 2; + + if default_parent_cells > 1 + && interrupt_map.len() % default_entry_cells != 0 + && interrupt_map.len() % one_cell_entry_cells == 0 + { + 1 + } else { + default_parent_cells + } +} + +pub fn parse_guest_irq_routes(vm_cfg: &AxVMConfig, dtb: &[u8]) -> AxResult { + let fdt = Fdt::from_bytes(dtb).map_err(|e| { + ax_err_type!( + InvalidData, + format!("Failed to parse DTB image while reading LoongArch IRQ routes: {e:#?}") + ) + })?; + let all_nodes: Vec<_> = fdt.all_nodes().collect(); + let mut phandle_nodes = BTreeMap::new(); + let mut eiointc = None; + let mut pch_pic = None; + let mut pch_msi_nodes = Vec::new(); + + for node in &all_nodes { + if let Some(phandle) = node_phandle(node) { + phandle_nodes.insert(phandle, node.clone()); + } + if has_compatible(node, "loongson,ls2k2000-eiointc") { + eiointc = Some(node.clone()); + } + if has_compatible_part(node, "pch-pic") { + pch_pic = Some(node.clone()); + } + if has_compatible(node, "loongson,pch-msi-1.0") { + pch_msi_nodes.push(node.clone()); + } + } + + let Some(eiointc) = eiointc else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC node not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + let Some(pch_pic) = pch_pic else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: PCH-PIC node not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + + let Some(pch_pic_phandle) = node_phandle(&pch_pic) else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: PCH-PIC phandle not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + let Some(eiointc_parent_phandle) = interrupt_parent_phandle(&eiointc) else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC interrupt parent not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + let Some(eiointc_guest_vector) = + first_direct_interrupt_id_for_parent(&eiointc, &phandle_nodes, eiointc_parent_phandle) + else { + warn!( + "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC CPU vector not found", + vm_cfg.id() + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); + return Ok(()); + }; + + let pch_pic_base_vec = property_u32(&pch_pic, "loongson,pic-base-vec").unwrap_or(0) as usize; + let mut routes = BTreeSet::new(); + + for node in &all_nodes { + if !is_enabled_node(node) || is_interrupt_controller(node) { + continue; + } + + for physical_irq in direct_interrupt_ids_for_parent(node, &phandle_nodes, pch_pic_phandle) { + add_loongarch_irq_route( + &mut routes, + pch_pic_base_vec + physical_irq, + eiointc_guest_vector, + node.name(), + ); + } + + parse_loongarch_pci_interrupt_map( + node, + &phandle_nodes, + pch_pic_phandle, + pch_pic_base_vec, + eiointc_guest_vector, + &mut routes, + ); + } + + for node in pch_msi_nodes { + let base_vec = property_u32(&node, "loongson,msi-base-vec").unwrap_or(0) as usize; + let num_vecs = property_u32(&node, "loongson,msi-num-vecs").unwrap_or(0) as usize; + for physical_irq in base_vec..base_vec.saturating_add(num_vecs) { + add_loongarch_irq_route(&mut routes, physical_irq, eiointc_guest_vector, node.name()); + } + } + + let routes = routes.into_iter().collect::>(); + info!( + "VM[{}] parsed {} LoongArch guest IRQ route(s) from DTB", + vm_cfg.id(), + routes.len() + ); + debug!( + "VM[{}] LoongArch guest IRQ routes: {:?}", + vm_cfg.id(), + routes + ); + store_loongarch_guest_irq_routes(vm_cfg.id(), routes); + Ok(()) +} diff --git a/os/axvisor/src/fdt/loongarch64/mod.rs b/os/axvisor/src/fdt/loongarch64/mod.rs new file mode 100644 index 0000000000..35e4672797 --- /dev/null +++ b/os/axvisor/src/fdt/loongarch64/mod.rs @@ -0,0 +1,2 @@ +pub(crate) mod guest_firmware_dtb; +pub(crate) mod guest_irq_route_dtb; diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index 5238d4a00d..6caa006ba6 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -19,6 +19,8 @@ mod create; mod device; +#[cfg(target_arch = "loongarch64")] +pub(crate) mod loongarch64; mod parser; mod print; pub(crate) mod vm_fdt; @@ -143,7 +145,7 @@ pub fn handle_fdt_operations( parse_reserved_memory_regions(vm_create_config, dtb)?; parse_passthrough_devices_address(vm_config, vm_create_config, dtb)?; #[cfg(target_arch = "loongarch64")] - parse_loongarch_guest_irq_routes(vm_config, dtb)?; + loongarch64::guest_irq_route_dtb::parse_guest_irq_routes(vm_config, dtb)?; #[cfg(target_arch = "aarch64")] parse_vm_interrupt(vm_config, dtb)?; } else { diff --git a/os/axvisor/src/fdt/parser.rs b/os/axvisor/src/fdt/parser.rs index e26495e165..e780479886 100644 --- a/os/axvisor/src/fdt/parser.rs +++ b/os/axvisor/src/fdt/parser.rs @@ -14,21 +14,13 @@ //! FDT parsing and processing functionality. -#[cfg(target_arch = "loongarch64")] -use alloc::collections::{BTreeMap, BTreeSet}; use alloc::{format, string::ToString, vec, vec::Vec}; use ax_errno::{AxResult, ax_err_type}; use fdt_parser::{Fdt, FdtHeader, PciRange, PciSpace}; -#[cfg(target_arch = "loongarch64")] -use fdt_parser::{Node, Status}; #[cfg(target_arch = "aarch64")] use crate::fdt::create::update_cpu_node; -#[cfg(target_arch = "loongarch64")] -use crate::guest_platform::loongarch64::{ - LoongArchGuestIrqRoute, store_guest_irq_routes as store_loongarch_guest_irq_routes, -}; use axvm::{MappingFlags, config::AxVMConfig}; use axvmconfig::{AxVMCrateConfig, PassThroughDeviceConfig, VmMemConfig, VmMemMappingType}; @@ -314,365 +306,6 @@ pub fn parse_reserved_memory_regions(crate_cfg: &mut AxVMCrateConfig, dtb: &[u8] Ok(()) } -#[cfg(target_arch = "loongarch64")] -fn property_u32_list(node: &Node<'_>, name: &str) -> Vec { - node.find_property(name) - .map(|prop| prop.u32_list().collect()) - .unwrap_or_default() -} - -#[cfg(target_arch = "loongarch64")] -fn property_u32(node: &Node<'_>, name: &str) -> Option { - node.find_property(name) - .and_then(|prop| prop.u32_list().next()) -} - -#[cfg(target_arch = "loongarch64")] -fn node_phandle(node: &Node<'_>) -> Option { - node.phandle().map(|phandle| phandle.as_usize()) -} - -#[cfg(target_arch = "loongarch64")] -fn interrupt_parent_phandle(node: &Node<'_>) -> Option { - node.interrupt_parent() - .and_then(|parent| node_phandle(&parent.node)) -} - -#[cfg(target_arch = "loongarch64")] -fn node_interrupt_cells(node: &Node<'_>) -> usize { - property_u32(node, "#interrupt-cells").unwrap_or(1) as usize -} - -#[cfg(target_arch = "loongarch64")] -fn node_address_cells(node: &Node<'_>) -> usize { - property_u32(node, "#address-cells").unwrap_or(2) as usize -} - -#[cfg(target_arch = "loongarch64")] -fn has_compatible(node: &Node<'_>, needle: &str) -> bool { - node.compatibles().any(|compatible| compatible == needle) -} - -#[cfg(target_arch = "loongarch64")] -fn has_compatible_part(node: &Node<'_>, needle: &str) -> bool { - node.compatibles() - .any(|compatible| compatible.contains(needle)) -} - -#[cfg(target_arch = "loongarch64")] -fn is_interrupt_controller(node: &Node<'_>) -> bool { - node.find_property("interrupt-controller").is_some() -} - -#[cfg(target_arch = "loongarch64")] -fn is_enabled_node(node: &Node<'_>) -> bool { - !matches!(node.status(), Some(Status::Disabled)) -} - -#[cfg(target_arch = "loongarch64")] -fn interrupt_ids_for_parent(node: &Node<'_>, parent_phandle: usize) -> Vec { - if interrupt_parent_phandle(node) != Some(parent_phandle) { - return Vec::new(); - } - - node.interrupts() - .map(|interrupts| { - interrupts - .filter_map(|mut interrupt| interrupt.next().map(|id| id as usize)) - .collect() - }) - .unwrap_or_default() -} - -#[cfg(target_arch = "loongarch64")] -fn interrupts_extended_for_parent( - node: &Node<'_>, - phandle_nodes: &BTreeMap>, - parent_phandle: usize, -) -> Vec { - let cells = property_u32_list(node, "interrupts-extended"); - if cells.is_empty() { - return Vec::new(); - } - - let mut result = Vec::new(); - let mut index = 0usize; - while index < cells.len() { - let phandle = cells[index] as usize; - index += 1; - - let interrupt_cells = phandle_nodes - .get(&phandle) - .map(node_interrupt_cells) - .unwrap_or(1); - - if index + interrupt_cells > cells.len() { - warn!( - "LoongArch interrupts-extended in node {} has truncated tuple at cell {}", - node.name(), - index - 1 - ); - break; - } - - if phandle == parent_phandle && interrupt_cells > 0 { - result.push(cells[index] as usize); - } - index += interrupt_cells; - } - - result -} - -#[cfg(target_arch = "loongarch64")] -fn direct_interrupt_ids_for_parent( - node: &Node<'_>, - phandle_nodes: &BTreeMap>, - parent_phandle: usize, -) -> Vec { - let mut ids = interrupt_ids_for_parent(node, parent_phandle); - ids.extend(interrupts_extended_for_parent( - node, - phandle_nodes, - parent_phandle, - )); - ids -} - -#[cfg(target_arch = "loongarch64")] -fn first_direct_interrupt_id_for_parent( - node: &Node<'_>, - phandle_nodes: &BTreeMap>, - parent_phandle: usize, -) -> Option { - direct_interrupt_ids_for_parent(node, phandle_nodes, parent_phandle) - .into_iter() - .next() -} - -#[cfg(target_arch = "loongarch64")] -fn add_loongarch_irq_route( - routes: &mut BTreeSet, - physical_irq: usize, - guest_vector: usize, - source: &str, -) { - let route = LoongArchGuestIrqRoute { - physical_irq, - guest_vector, - }; - if routes.insert(route) { - debug!( - "LoongArch guest IRQ route from DTB: physical_irq={}, guest_vector={}, source={}", - physical_irq, guest_vector, source - ); - } -} - -#[cfg(target_arch = "loongarch64")] -fn parse_loongarch_pci_interrupt_map( - node: &Node<'_>, - phandle_nodes: &BTreeMap>, - pch_pic_phandle: usize, - pch_pic_base_vec: usize, - eiointc_guest_vector: usize, - routes: &mut BTreeSet, -) { - let interrupt_map = property_u32_list(node, "interrupt-map"); - if interrupt_map.is_empty() { - return; - } - - let child_address_cells = node_address_cells(node); - let child_interrupt_cells = node_interrupt_cells(node); - let child_cells = child_address_cells + child_interrupt_cells; - if child_cells == 0 { - warn!( - "LoongArch PCI interrupt-map in node {} has invalid child cell count", - node.name() - ); - return; - } - let mut index = 0usize; - - while index + child_cells < interrupt_map.len() { - let parent_phandle = interrupt_map[index + child_cells] as usize; - let Some(parent_node) = phandle_nodes.get(&parent_phandle) else { - warn!( - "LoongArch PCI interrupt-map parent phandle {:#x} not found in node {}", - parent_phandle, - node.name() - ); - break; - }; - let parent_interrupt_cells = - pci_interrupt_map_parent_cells(&interrupt_map, child_cells, parent_node); - let entry_cells = child_cells + 1 + parent_interrupt_cells; - if index + entry_cells > interrupt_map.len() { - warn!( - "LoongArch PCI interrupt-map in node {} has truncated entry at cell {}", - node.name(), - index - ); - break; - } - - if parent_phandle == pch_pic_phandle && parent_interrupt_cells > 0 { - let parent_irq = interrupt_map[index + child_cells + 1] as usize; - add_loongarch_irq_route( - routes, - pch_pic_base_vec + parent_irq, - eiointc_guest_vector, - node.name(), - ); - } - index += entry_cells; - } -} - -#[cfg(target_arch = "loongarch64")] -fn pci_interrupt_map_parent_cells( - interrupt_map: &[u32], - child_cells: usize, - parent_node: &Node<'_>, -) -> usize { - let default_parent_cells = node_interrupt_cells(parent_node); - let default_entry_cells = child_cells + 1 + default_parent_cells; - let one_cell_entry_cells = child_cells + 2; - - if default_parent_cells > 1 - && interrupt_map.len() % default_entry_cells != 0 - && interrupt_map.len() % one_cell_entry_cells == 0 - { - 1 - } else { - default_parent_cells - } -} - -#[cfg(target_arch = "loongarch64")] -pub fn parse_loongarch_guest_irq_routes(vm_cfg: &AxVMConfig, dtb: &[u8]) -> AxResult { - let fdt = Fdt::from_bytes(dtb).map_err(|e| { - ax_err_type!( - InvalidData, - format!("Failed to parse DTB image while reading LoongArch IRQ routes: {e:#?}") - ) - })?; - let all_nodes: Vec<_> = fdt.all_nodes().collect(); - let mut phandle_nodes = BTreeMap::new(); - let mut eiointc = None; - let mut pch_pic = None; - let mut pch_msi_nodes = Vec::new(); - - for node in &all_nodes { - if let Some(phandle) = node_phandle(node) { - phandle_nodes.insert(phandle, node.clone()); - } - if has_compatible(node, "loongson,ls2k2000-eiointc") { - eiointc = Some(node.clone()); - } - if has_compatible_part(node, "pch-pic") { - pch_pic = Some(node.clone()); - } - if has_compatible(node, "loongson,pch-msi-1.0") { - pch_msi_nodes.push(node.clone()); - } - } - - let Some(eiointc) = eiointc else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC node not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - let Some(pch_pic) = pch_pic else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: PCH-PIC node not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - - let Some(pch_pic_phandle) = node_phandle(&pch_pic) else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: PCH-PIC phandle not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - let Some(eiointc_parent_phandle) = interrupt_parent_phandle(&eiointc) else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC interrupt parent not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - let Some(eiointc_guest_vector) = - first_direct_interrupt_id_for_parent(&eiointc, &phandle_nodes, eiointc_parent_phandle) - else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC CPU vector not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - - let pch_pic_base_vec = property_u32(&pch_pic, "loongson,pic-base-vec").unwrap_or(0) as usize; - let mut routes = BTreeSet::new(); - - for node in &all_nodes { - if !is_enabled_node(node) || is_interrupt_controller(node) { - continue; - } - - for physical_irq in direct_interrupt_ids_for_parent(node, &phandle_nodes, pch_pic_phandle) { - add_loongarch_irq_route( - &mut routes, - pch_pic_base_vec + physical_irq, - eiointc_guest_vector, - node.name(), - ); - } - - parse_loongarch_pci_interrupt_map( - node, - &phandle_nodes, - pch_pic_phandle, - pch_pic_base_vec, - eiointc_guest_vector, - &mut routes, - ); - } - - for node in pch_msi_nodes { - let base_vec = property_u32(&node, "loongson,msi-base-vec").unwrap_or(0) as usize; - let num_vecs = property_u32(&node, "loongson,msi-num-vecs").unwrap_or(0) as usize; - for physical_irq in base_vec..base_vec.saturating_add(num_vecs) { - add_loongarch_irq_route(&mut routes, physical_irq, eiointc_guest_vector, node.name()); - } - } - - let routes = routes.into_iter().collect::>(); - info!( - "VM[{}] parsed {} LoongArch guest IRQ route(s) from DTB", - vm_cfg.id(), - routes.len() - ); - debug!( - "VM[{}] LoongArch guest IRQ routes: {:?}", - vm_cfg.id(), - routes - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), routes); - Ok(()) -} - #[cfg(test)] mod tests { use super::align_reserved_region_4k; diff --git a/os/axvisor/src/guest_platform/loongarch64/mod.rs b/os/axvisor/src/guest_platform/loongarch64/mod.rs index 4899303593..e8fc47e47d 100644 --- a/os/axvisor/src/guest_platform/loongarch64/mod.rs +++ b/os/axvisor/src/guest_platform/loongarch64/mod.rs @@ -1,4 +1,3 @@ -mod firmware_fdt; mod probe; mod resources; @@ -148,7 +147,7 @@ impl GuestPlatform { pub fn load_firmware_fdt(vm: &AxVMRef, config: &AxVMCrateConfig) -> AxResult { let platform = GuestPlatform::discover(vm, config); - let fdt = firmware_fdt::build(&platform)?; + let fdt = crate::fdt::loongarch64::guest_firmware_dtb::build(&platform)?; debug!( "VM[{}] loading LoongArch UEFI firmware FDT: {} bytes at {:#x}", config.base.id, From c6bc62f0a31f3fb8ed1da721010210cbde869d8a Mon Sep 17 00:00:00 2001 From: szy Date: Fri, 26 Jun 2026 17:12:51 +0800 Subject: [PATCH 49/50] refactor(axvisor): trim LoongArch guest boot changes --- os/axvisor/src/config.rs | 57 +-- os/axvisor/src/fdt/create.rs | 81 +--- .../fdt/loongarch64/guest_irq_route_dtb.rs | 354 ------------------ os/axvisor/src/fdt/loongarch64/mod.rs | 1 - os/axvisor/src/fdt/mod.rs | 83 ++-- os/axvisor/src/fdt/vm_fdt/mod.rs | 4 +- .../src/guest_platform/loongarch64/mod.rs | 2 +- os/axvisor/src/images/mod.rs | 140 +++---- 8 files changed, 125 insertions(+), 597 deletions(-) delete mode 100644 os/axvisor/src/fdt/loongarch64/guest_irq_route_dtb.rs diff --git a/os/axvisor/src/config.rs b/os/axvisor/src/config.rs index a8b57f912e..4a8c70904e 100644 --- a/os/axvisor/src/config.rs +++ b/os/axvisor/src/config.rs @@ -85,11 +85,7 @@ pub mod vmcfg { } pub fn get_vm_dtb_arc(_vm_cfg: &AxVMConfig) -> Option> { - #[cfg(any( - target_arch = "aarch64", - target_arch = "loongarch64", - target_arch = "riscv64" - ))] + #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] { let cache_lock = dtb_cache().lock(); if let Some(dtb) = cache_lock.get(&_vm_cfg.id()) { @@ -144,19 +140,6 @@ pub fn init_guest_vm(raw_cfg: &str) -> AxResult { any(target_arch = "x86_64", target_arch = "loongarch64") ))] let release_host_filesystem = vm_config_needs_host_filesystem_release(&vm_create_config); - #[cfg(all( - feature = "fs", - any(target_arch = "x86_64", target_arch = "loongarch64") - ))] - debug!( - "VM[{}] host filesystem release check: image_location={:?}, passthrough_devices={}, \ - passthrough_addresses={}, required={}", - vm_create_config.base.id, - vm_create_config.kernel.image_location, - vm_create_config.devices.passthrough_devices.len(), - vm_create_config.devices.passthrough_addresses.len(), - release_host_filesystem - ); if let Some(linux) = super::images::get_image_header(&vm_create_config) { debug!( @@ -299,29 +282,7 @@ fn configured_bios_load_gpa(cfg: &AxVMCrateConfig) -> Option { fn vm_config_needs_host_filesystem_release(config: &AxVMCrateConfig) -> bool { let has_passthrough = !config.devices.passthrough_devices.is_empty() || !config.devices.passthrough_addresses.is_empty(); - if !has_passthrough { - return false; - } - - if config.kernel.image_location.as_deref() == Some("fs") { - return true; - } - - #[cfg(target_arch = "loongarch64")] - { - let loongarch_uefi_rootfs_guest = config.kernel.effective_boot_protocol() - == VMBootProtocol::Uefi - && config.kernel.cmdline.as_deref().is_some_and(|cmdline| { - cmdline - .split_ascii_whitespace() - .any(|arg| arg == "root=/dev/vda") - }); - if loongarch_uefi_rootfs_guest { - return true; - } - } - - false + has_passthrough && config.kernel.image_location.as_deref() == Some("fs") } #[cfg(all( @@ -367,13 +328,6 @@ fn vm_alloc_memory_regions(vm_create_config: &AxVMCrateConfig, vm: &AxVMRef) -> }; for memory in &vm_create_config.kernel.memory_regions { - debug!( - "VM[{}] allocating memory region: gpa={:#x}, size={:#x}, map_type={:?}", - vm.id(), - memory.gpa, - memory.size, - memory.map_type - ); match memory.map_type { VmMemMappingType::MapAlloc => { vm.alloc_memory_region(make_layout(memory)?, Some(GuestPhysAddr::from(memory.gpa))) @@ -407,13 +361,6 @@ fn vm_alloc_memory_regions(vm_create_config: &AxVMCrateConfig, vm: &AxVMRef) -> })?; } } - debug!( - "VM[{}] memory region allocated: gpa={:#x}, size={:#x}, map_type={:?}", - vm.id(), - memory.gpa, - memory.size, - memory.map_type - ); } Ok(()) } diff --git a/os/axvisor/src/fdt/create.rs b/os/axvisor/src/fdt/create.rs index d41933dad9..8ebbd38dc9 100644 --- a/os/axvisor/src/fdt/create.rs +++ b/os/axvisor/src/fdt/create.rs @@ -17,48 +17,22 @@ use alloc::{ string::{String, ToString}, vec::Vec, }; -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64" -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] use core::ptr::NonNull; use ax_errno::{AxError, AxResult, ax_err_type}; -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64" -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] use ax_memory_addr::MemoryAddr; use fdt_parser::{Fdt, Node}; use super::vm_fdt::{FdtWriter, FdtWriterNode}; -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64" -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] use crate::images::load_vm_image_from_memory; -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64" -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] use axvm::AxVMRef; -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64", - test -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64", test))] use axvm::GuestPhysAddr; -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64", - test -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64", test))] use axvm::VMMemoryRegion; use axvmconfig::AxVMCrateConfig; @@ -146,10 +120,6 @@ pub fn crate_guest_fdt( previous_node_level = node.level; - #[cfg(target_arch = "loongarch64")] - let add_pci_interrupt_cells = - is_loongarch_pci_host_node(node) && node.find_property("#interrupt-cells").is_none(); - // Copy all properties of the node for prop in node.propertys() { if node_path.starts_with("/cpus") && should_skip_guest_cpu_prop(prop.name) { @@ -159,13 +129,6 @@ pub fn crate_guest_fdt( .property(prop.name, prop.raw_value()) .map_err(fdt_write_err)?; } - - #[cfg(target_arch = "loongarch64")] - if add_pci_interrupt_cells { - fdt_writer - .property_u32("#interrupt-cells", 1) - .map_err(fdt_write_err)?; - } } // End all unclosed nodes @@ -182,14 +145,6 @@ pub fn crate_guest_fdt( fdt_writer.finish().map_err(fdt_write_err) } -#[cfg(target_arch = "loongarch64")] -fn is_loongarch_pci_host_node(node: &Node<'_>) -> bool { - node.name().starts_with("pcie@") - && node - .compatibles() - .any(|compatible| compatible == "pci-host-ecam-generic") -} - /// Node processing action enumeration enum NodeAction { /// Skip node, not included in guest FDT @@ -336,12 +291,7 @@ fn need_cpu_node(phys_cpu_ids: &[usize], node: &Node, node_path: &str) -> bool { } /// Add memory node -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64", - test -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64", test))] fn add_memory_node( new_memory: &[VMMemoryRegion], crate_config: &AxVMCrateConfig, @@ -375,10 +325,6 @@ fn add_memory_node( ) { let gpa = mem.gpa.as_usize() as u64; let size = mem.size() as u64; - #[cfg(target_arch = "loongarch64")] - if gpa >= 0x1000_0000 { - continue; - } new_value.push((gpa >> 32) as u32); new_value.push((gpa & 0xFFFFFFFF) as u32); new_value.push((size >> 32) as u32); @@ -583,7 +529,7 @@ pub fn update_fdt( Ok(()) } -#[cfg(any(target_arch = "riscv64", target_arch = "loongarch64"))] +#[cfg(target_arch = "riscv64")] pub fn update_fdt( fdt_src: NonNull, dtb_size: usize, @@ -707,11 +653,7 @@ mod tests { } } -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64" -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub(crate) fn calculate_dtb_load_addr(vm: AxVMRef, fdt_size: usize) -> AxResult { const MB: usize = 1024 * 1024; @@ -722,9 +664,6 @@ pub(crate) fn calculate_dtb_load_addr(vm: AxVMRef, fdt_size: usize) -> AxResult< })?; let dtb_addr = vm.with_config(|config| { - #[cfg(target_arch = "loongarch64")] - let use_configured_dtb_addr = config.image_config.dtb_load_gpa.is_some(); - #[cfg(not(target_arch = "loongarch64"))] let use_configured_dtb_addr = config.image_config.dtb_load_gpa.is_some() && !main_memory.is_identical(); @@ -747,7 +686,7 @@ pub(crate) fn calculate_dtb_load_addr(vm: AxVMRef, fdt_size: usize) -> AxResult< Ok(dtb_addr) } -#[cfg(any(target_arch = "riscv64", target_arch = "loongarch64"))] +#[cfg(target_arch = "riscv64")] pub(crate) fn patch_guest_fdt_for_runtime( fdt: &Fdt, memory_regions: &[VMMemoryRegion], diff --git a/os/axvisor/src/fdt/loongarch64/guest_irq_route_dtb.rs b/os/axvisor/src/fdt/loongarch64/guest_irq_route_dtb.rs deleted file mode 100644 index 6632159970..0000000000 --- a/os/axvisor/src/fdt/loongarch64/guest_irq_route_dtb.rs +++ /dev/null @@ -1,354 +0,0 @@ -use alloc::{ - collections::{BTreeMap, BTreeSet}, - format, - vec::Vec, -}; - -use ax_errno::{AxResult, ax_err_type}; -use axvm::config::AxVMConfig; -use fdt_parser::{Fdt, Node, Status}; - -use crate::guest_platform::loongarch64::{ - LoongArchGuestIrqRoute, store_guest_irq_routes as store_loongarch_guest_irq_routes, -}; - -fn property_u32_list(node: &Node<'_>, name: &str) -> Vec { - node.find_property(name) - .map(|prop| prop.u32_list().collect()) - .unwrap_or_default() -} - -fn property_u32(node: &Node<'_>, name: &str) -> Option { - node.find_property(name) - .and_then(|prop| prop.u32_list().next()) -} - -fn node_phandle(node: &Node<'_>) -> Option { - node.phandle().map(|phandle| phandle.as_usize()) -} - -fn interrupt_parent_phandle(node: &Node<'_>) -> Option { - node.interrupt_parent() - .and_then(|parent| node_phandle(&parent.node)) -} - -fn node_interrupt_cells(node: &Node<'_>) -> usize { - property_u32(node, "#interrupt-cells").unwrap_or(1) as usize -} - -fn node_address_cells(node: &Node<'_>) -> usize { - property_u32(node, "#address-cells").unwrap_or(2) as usize -} - -fn has_compatible(node: &Node<'_>, needle: &str) -> bool { - node.compatibles().any(|compatible| compatible == needle) -} - -fn has_compatible_part(node: &Node<'_>, needle: &str) -> bool { - node.compatibles() - .any(|compatible| compatible.contains(needle)) -} - -fn is_interrupt_controller(node: &Node<'_>) -> bool { - node.find_property("interrupt-controller").is_some() -} - -fn is_enabled_node(node: &Node<'_>) -> bool { - !matches!(node.status(), Some(Status::Disabled)) -} - -fn interrupt_ids_for_parent(node: &Node<'_>, parent_phandle: usize) -> Vec { - if interrupt_parent_phandle(node) != Some(parent_phandle) { - return Vec::new(); - } - - node.interrupts() - .map(|interrupts| { - interrupts - .filter_map(|mut interrupt| interrupt.next().map(|id| id as usize)) - .collect() - }) - .unwrap_or_default() -} - -fn interrupts_extended_for_parent( - node: &Node<'_>, - phandle_nodes: &BTreeMap>, - parent_phandle: usize, -) -> Vec { - let cells = property_u32_list(node, "interrupts-extended"); - if cells.is_empty() { - return Vec::new(); - } - - let mut result = Vec::new(); - let mut index = 0usize; - while index < cells.len() { - let phandle = cells[index] as usize; - index += 1; - - let interrupt_cells = phandle_nodes - .get(&phandle) - .map(node_interrupt_cells) - .unwrap_or(1); - - if index + interrupt_cells > cells.len() { - warn!( - "LoongArch interrupts-extended in node {} has truncated tuple at cell {}", - node.name(), - index - 1 - ); - break; - } - - if phandle == parent_phandle && interrupt_cells > 0 { - result.push(cells[index] as usize); - } - index += interrupt_cells; - } - - result -} - -fn direct_interrupt_ids_for_parent( - node: &Node<'_>, - phandle_nodes: &BTreeMap>, - parent_phandle: usize, -) -> Vec { - let mut ids = interrupt_ids_for_parent(node, parent_phandle); - ids.extend(interrupts_extended_for_parent( - node, - phandle_nodes, - parent_phandle, - )); - ids -} - -fn first_direct_interrupt_id_for_parent( - node: &Node<'_>, - phandle_nodes: &BTreeMap>, - parent_phandle: usize, -) -> Option { - direct_interrupt_ids_for_parent(node, phandle_nodes, parent_phandle) - .into_iter() - .next() -} - -fn add_loongarch_irq_route( - routes: &mut BTreeSet, - physical_irq: usize, - guest_vector: usize, - source: &str, -) { - let route = LoongArchGuestIrqRoute { - physical_irq, - guest_vector, - }; - if routes.insert(route) { - debug!( - "LoongArch guest IRQ route from DTB: physical_irq={}, guest_vector={}, source={}", - physical_irq, guest_vector, source - ); - } -} - -fn parse_loongarch_pci_interrupt_map( - node: &Node<'_>, - phandle_nodes: &BTreeMap>, - pch_pic_phandle: usize, - pch_pic_base_vec: usize, - eiointc_guest_vector: usize, - routes: &mut BTreeSet, -) { - let interrupt_map = property_u32_list(node, "interrupt-map"); - if interrupt_map.is_empty() { - return; - } - - let child_address_cells = node_address_cells(node); - let child_interrupt_cells = node_interrupt_cells(node); - let child_cells = child_address_cells + child_interrupt_cells; - if child_cells == 0 { - warn!( - "LoongArch PCI interrupt-map in node {} has invalid child cell count", - node.name() - ); - return; - } - let mut index = 0usize; - - while index + child_cells < interrupt_map.len() { - let parent_phandle = interrupt_map[index + child_cells] as usize; - let Some(parent_node) = phandle_nodes.get(&parent_phandle) else { - warn!( - "LoongArch PCI interrupt-map parent phandle {:#x} not found in node {}", - parent_phandle, - node.name() - ); - break; - }; - let parent_interrupt_cells = - pci_interrupt_map_parent_cells(&interrupt_map, child_cells, parent_node); - let entry_cells = child_cells + 1 + parent_interrupt_cells; - if index + entry_cells > interrupt_map.len() { - warn!( - "LoongArch PCI interrupt-map in node {} has truncated entry at cell {}", - node.name(), - index - ); - break; - } - - if parent_phandle == pch_pic_phandle && parent_interrupt_cells > 0 { - let parent_irq = interrupt_map[index + child_cells + 1] as usize; - add_loongarch_irq_route( - routes, - pch_pic_base_vec + parent_irq, - eiointc_guest_vector, - node.name(), - ); - } - index += entry_cells; - } -} - -fn pci_interrupt_map_parent_cells( - interrupt_map: &[u32], - child_cells: usize, - parent_node: &Node<'_>, -) -> usize { - let default_parent_cells = node_interrupt_cells(parent_node); - let default_entry_cells = child_cells + 1 + default_parent_cells; - let one_cell_entry_cells = child_cells + 2; - - if default_parent_cells > 1 - && interrupt_map.len() % default_entry_cells != 0 - && interrupt_map.len() % one_cell_entry_cells == 0 - { - 1 - } else { - default_parent_cells - } -} - -pub fn parse_guest_irq_routes(vm_cfg: &AxVMConfig, dtb: &[u8]) -> AxResult { - let fdt = Fdt::from_bytes(dtb).map_err(|e| { - ax_err_type!( - InvalidData, - format!("Failed to parse DTB image while reading LoongArch IRQ routes: {e:#?}") - ) - })?; - let all_nodes: Vec<_> = fdt.all_nodes().collect(); - let mut phandle_nodes = BTreeMap::new(); - let mut eiointc = None; - let mut pch_pic = None; - let mut pch_msi_nodes = Vec::new(); - - for node in &all_nodes { - if let Some(phandle) = node_phandle(node) { - phandle_nodes.insert(phandle, node.clone()); - } - if has_compatible(node, "loongson,ls2k2000-eiointc") { - eiointc = Some(node.clone()); - } - if has_compatible_part(node, "pch-pic") { - pch_pic = Some(node.clone()); - } - if has_compatible(node, "loongson,pch-msi-1.0") { - pch_msi_nodes.push(node.clone()); - } - } - - let Some(eiointc) = eiointc else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC node not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - let Some(pch_pic) = pch_pic else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: PCH-PIC node not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - - let Some(pch_pic_phandle) = node_phandle(&pch_pic) else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: PCH-PIC phandle not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - let Some(eiointc_parent_phandle) = interrupt_parent_phandle(&eiointc) else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC interrupt parent not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - let Some(eiointc_guest_vector) = - first_direct_interrupt_id_for_parent(&eiointc, &phandle_nodes, eiointc_parent_phandle) - else { - warn!( - "VM[{}] LoongArch guest IRQ route parsing skipped: EIOINTC CPU vector not found", - vm_cfg.id() - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), Vec::new()); - return Ok(()); - }; - - let pch_pic_base_vec = property_u32(&pch_pic, "loongson,pic-base-vec").unwrap_or(0) as usize; - let mut routes = BTreeSet::new(); - - for node in &all_nodes { - if !is_enabled_node(node) || is_interrupt_controller(node) { - continue; - } - - for physical_irq in direct_interrupt_ids_for_parent(node, &phandle_nodes, pch_pic_phandle) { - add_loongarch_irq_route( - &mut routes, - pch_pic_base_vec + physical_irq, - eiointc_guest_vector, - node.name(), - ); - } - - parse_loongarch_pci_interrupt_map( - node, - &phandle_nodes, - pch_pic_phandle, - pch_pic_base_vec, - eiointc_guest_vector, - &mut routes, - ); - } - - for node in pch_msi_nodes { - let base_vec = property_u32(&node, "loongson,msi-base-vec").unwrap_or(0) as usize; - let num_vecs = property_u32(&node, "loongson,msi-num-vecs").unwrap_or(0) as usize; - for physical_irq in base_vec..base_vec.saturating_add(num_vecs) { - add_loongarch_irq_route(&mut routes, physical_irq, eiointc_guest_vector, node.name()); - } - } - - let routes = routes.into_iter().collect::>(); - info!( - "VM[{}] parsed {} LoongArch guest IRQ route(s) from DTB", - vm_cfg.id(), - routes.len() - ); - debug!( - "VM[{}] LoongArch guest IRQ routes: {:?}", - vm_cfg.id(), - routes - ); - store_loongarch_guest_irq_routes(vm_cfg.id(), routes); - Ok(()) -} diff --git a/os/axvisor/src/fdt/loongarch64/mod.rs b/os/axvisor/src/fdt/loongarch64/mod.rs index 35e4672797..524f849b7b 100644 --- a/os/axvisor/src/fdt/loongarch64/mod.rs +++ b/os/axvisor/src/fdt/loongarch64/mod.rs @@ -1,2 +1 @@ pub(crate) mod guest_firmware_dtb; -pub(crate) mod guest_irq_route_dtb; diff --git a/os/axvisor/src/fdt/mod.rs b/os/axvisor/src/fdt/mod.rs index 6caa006ba6..9198255099 100644 --- a/os/axvisor/src/fdt/mod.rs +++ b/os/axvisor/src/fdt/mod.rs @@ -17,46 +17,63 @@ //! This module provides functionality for parsing and processing device tree blobs, //! including CPU configuration, passthrough device detection, and FDT generation. +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] mod create; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] mod device; #[cfg(target_arch = "loongarch64")] pub(crate) mod loongarch64; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] mod parser; mod print; pub(crate) mod vm_fdt; -use alloc::{collections::BTreeMap, format, vec::Vec}; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +use alloc::format; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +use alloc::{collections::BTreeMap, vec::Vec}; -use ax_errno::{AxResult, ax_err_type}; +use ax_errno::AxResult; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +use ax_errno::ax_err_type; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] use ax_kspin::SpinNoIrq as Mutex; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] use ax_lazyinit::LazyInit; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +use fdt_parser::Fdt; // pub use print::print_fdt; -#[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64" -))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub use create::update_fdt; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub use device::build_all_node_paths; -use fdt_parser::Fdt; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub use parser::*; use axvm::config::AxVMConfig; use axvmconfig::{AxVMCrateConfig, VMBootProtocol}; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] use crate::config::{get_vm_dtb_arc, vmcfg}; // DTB cache for generated device trees +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] static GENERATED_DTB_CACHE: LazyInit>>> = LazyInit::new(); /// Initialize the DTB cache +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub fn init_dtb_cache() { GENERATED_DTB_CACHE.init_once(Mutex::new(BTreeMap::new())); - #[cfg(target_arch = "loongarch64")] +} + +/// Initialize LoongArch guest firmware resource handling. +#[cfg(target_arch = "loongarch64")] +pub fn init_dtb_cache() { crate::guest_platform::loongarch64::init(); } /// Get reference to the DTB cache +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub fn dtb_cache() -> &'static Mutex>> { GENERATED_DTB_CACHE.get_or_init(|| Mutex::new(BTreeMap::new())) } @@ -64,6 +81,7 @@ pub fn dtb_cache() -> &'static Mutex>> { /// Generate guest FDT cache the result /// # Return Value /// Returns the generated DTB data and stores it in the global cache +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub fn crate_guest_fdt_with_cache(dtb_data: Vec, crate_config: &AxVMCrateConfig) { // Store data in global cache let mut cache_lock = dtb_cache().lock(); @@ -78,7 +96,7 @@ fn handle_uefi_fdt_operations( crate::guest_platform::loongarch64::prepare_uefi_fdt_config(vm_config, vm_create_config) } -#[cfg(not(target_arch = "loongarch64"))] +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] fn handle_uefi_fdt_operations( vm_config: &mut AxVMConfig, vm_create_config: &mut AxVMCrateConfig, @@ -93,6 +111,23 @@ fn handle_uefi_fdt_operations( } /// Handle all FDT-related operations for guest architectures that boot with DTB. +#[cfg(target_arch = "loongarch64")] +pub fn handle_fdt_operations( + vm_config: &mut AxVMConfig, + vm_create_config: &mut AxVMCrateConfig, +) -> AxResult { + if vm_create_config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { + return handle_uefi_fdt_operations(vm_config, vm_create_config); + } + + ax_errno::ax_err!( + Unsupported, + "LoongArch AxVisor guests currently require UEFI boot" + ) +} + +/// Handle all FDT-related operations for guest architectures that boot with DTB. +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub fn handle_fdt_operations( vm_config: &mut AxVMConfig, vm_create_config: &mut AxVMCrateConfig, @@ -118,25 +153,14 @@ pub fn handle_fdt_operations( ); setup_guest_fdt_from_vmm(host_fdt_bytes, vm_config, vm_create_config)?; } + } else if let Some(provided_dtb) = get_developer_provided_dtb(vm_config, vm_create_config)? { + info!("VM[{}] found DTB , parsing...", vm_config.id()); + update_provided_fdt(&provided_dtb, &[], vm_create_config)?; } else { - #[cfg(target_arch = "loongarch64")] - { - warn!( - "VM[{}] host FDT is unavailable on loongarch64 boot path; skipping \ - host-FDT-dependent guest DTB handling", - vm_config.id() - ); - } - - if let Some(provided_dtb) = get_developer_provided_dtb(vm_config, vm_create_config)? { - info!("VM[{}] found DTB , parsing...", vm_config.id()); - update_provided_fdt(&provided_dtb, &[], vm_create_config)?; - } else { - warn!( - "VM[{}] no guest DTB provided; continuing without generated DTB", - vm_config.id() - ); - } + warn!( + "VM[{}] no guest DTB provided; continuing without generated DTB", + vm_config.id() + ); } // Overlay VM config with the given DTB. @@ -144,8 +168,6 @@ pub fn handle_fdt_operations( let dtb = dtb_arc.as_ref(); parse_reserved_memory_regions(vm_create_config, dtb)?; parse_passthrough_devices_address(vm_config, vm_create_config, dtb)?; - #[cfg(target_arch = "loongarch64")] - loongarch64::guest_irq_route_dtb::parse_guest_irq_routes(vm_config, dtb)?; #[cfg(target_arch = "aarch64")] parse_vm_interrupt(vm_config, dtb)?; } else { @@ -175,6 +197,7 @@ pub fn handle_fdt_operations( Ok(()) } +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] pub fn get_developer_provided_dtb( vm_cfg: &AxVMConfig, crate_config: &AxVMCrateConfig, diff --git a/os/axvisor/src/fdt/vm_fdt/mod.rs b/os/axvisor/src/fdt/vm_fdt/mod.rs index b2ac856638..0464c5d193 100644 --- a/os/axvisor/src/fdt/vm_fdt/mod.rs +++ b/os/axvisor/src/fdt/vm_fdt/mod.rs @@ -1,6 +1,8 @@ mod writer; -pub use writer::{FdtWriter, FdtWriterNode}; +pub use writer::FdtWriter; +#[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] +pub use writer::FdtWriterNode; /// Magic number used in the FDT header. pub const FDT_MAGIC: u32 = 0xd00dfeed; diff --git a/os/axvisor/src/guest_platform/loongarch64/mod.rs b/os/axvisor/src/guest_platform/loongarch64/mod.rs index e8fc47e47d..f4d7c18b80 100644 --- a/os/axvisor/src/guest_platform/loongarch64/mod.rs +++ b/os/axvisor/src/guest_platform/loongarch64/mod.rs @@ -12,7 +12,7 @@ use axvmconfig::{AxVMCrateConfig, EmulatedDeviceType}; pub use resources::{ LoongArchGuestIrqRoute, get_guest_irq_routes, prepare_uefi_fdt_config, - prepare_uefi_runtime_config, store_guest_irq_routes, + prepare_uefi_runtime_config, }; use crate::images::load_vm_image_from_memory; diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index 28b73085bf..e053a1b4ce 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -13,15 +13,15 @@ // limitations under the License. use alloc::format; -#[cfg(target_arch = "x86_64")] -use alloc::vec::Vec; use ax_errno::{AxResult, ax_err, ax_err_type}; +use axvmconfig::AxVMCrateConfig; #[cfg(target_arch = "x86_64")] use axvmconfig::EmulatedDeviceType; +#[cfg(any(target_arch = "loongarch64", target_arch = "x86_64"))] +use axvmconfig::VMBootProtocol; #[cfg(target_arch = "x86_64")] use axvmconfig::VmMemMappingType; -use axvmconfig::{AxVMCrateConfig, VMBootProtocol}; use byte_unit::Byte; use axvm::{AxVMRef, GuestPhysAddr, VMMemoryRegion}; @@ -95,6 +95,7 @@ fn memory_images_for_vm(config: &AxVMCrateConfig) -> AxResult<&'static vmcfg::Me }) } +#[cfg(target_arch = "loongarch64")] fn firmware_image_for_vm(config: &AxVMCrateConfig) -> Option<&'static [u8]> { vmcfg::get_firmware_images() .iter() @@ -175,11 +176,11 @@ impl ImageLoader { if self.loongarch_uefi_boot() { self.load_loongarch_uefi_firmware_dtb()?; self.add_loongarch_uefi_fw_cfg_from_memory(vm_imags.kernel, vm_imags.ramdisk)?; - self.load_boot_image_from_memory(vm_imags.bios)?; + self.load_loongarch_uefi_firmware_from_memory(vm_imags.bios)?; return Ok(()); } - self.load_kernel_from_memory(vm_imags.kernel)?; + load_vm_image_from_memory(vm_imags.kernel, self.kernel_load_gpa, self.vm.clone())?; // Load Ramdisk image and record its size before regenerating the DTB. if let Some(buffer) = vm_imags.ramdisk { @@ -190,11 +191,7 @@ impl ImageLoader { if let Some(dtb_arc) = get_vm_dtb_arc(&vm_config) { let _dtb_slice: &[u8] = &dtb_arc; - #[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64" - ))] + #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] { if let Some(dtb_src) = core::ptr::NonNull::new(_dtb_slice.as_ptr() as *mut u8) { crate::fdt::update_fdt( @@ -208,7 +205,7 @@ impl ImageLoader { } } } else { - #[cfg(any(target_arch = "loongarch64", target_arch = "riscv64"))] + #[cfg(target_arch = "riscv64")] if let Some(buffer) = vm_imags.dtb { let dtb_load_gpa = self .dtb_load_gpa @@ -273,16 +270,6 @@ impl ImageLoader { let load_gpa = self .bios_load_gpa .ok_or_else(|| ax_err_type!(NotFound, "boot firmware load address is missing"))?; - if self.config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { - let flash_len = self - .config - .kernel - .memory_regions - .iter() - .find(|region| region.gpa == load_gpa.as_usize()) - .map_or(buffer.len(), |region| region.size); - fill_vm_region(load_gpa, flash_len, 0xff, self.vm.clone())?; - } load_vm_image_from_memory(buffer, load_gpa, self.vm.clone())?; #[cfg(target_arch = "x86_64")] if should_patch_x86_multiboot_info(&self.config) { @@ -291,6 +278,7 @@ impl ImageLoader { return Ok(()); } + #[cfg(target_arch = "x86_64")] if self.config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { let firmware_path = self.config.kernel.boot_firmware_path().ok_or_else(|| { ax_errno::ax_err_type!(NotFound, "UEFI firmware image path is missed") @@ -301,21 +289,6 @@ impl ImageLoader { #[cfg(feature = "fs")] { - if let Some(buffer) = firmware_image_for_vm(&self.config) { - info!( - "Loading UEFI firmware image from build-time buffer at GPA {:#x}", - load_gpa.as_usize() - ); - let flash_len = self - .config - .kernel - .memory_regions - .iter() - .find(|region| region.gpa == load_gpa.as_usize()) - .map_or(buffer.len(), |region| region.size); - fill_vm_region(load_gpa, flash_len, 0xff, self.vm.clone())?; - return load_vm_image_from_memory(buffer, load_gpa, self.vm.clone()); - } info!( "Loading UEFI firmware image {} at GPA {:#x}", firmware_path, @@ -396,19 +369,38 @@ impl ImageLoader { } #[cfg(target_arch = "loongarch64")] - fn load_loongarch_uefi_firmware_dtb(&self) -> AxResult { - crate::guest_platform::loongarch64::prepare_uefi_runtime_config(&self.vm, &self.config); - crate::guest_platform::loongarch64::load_firmware_fdt(&self.vm, &self.config) + fn load_loongarch_uefi_firmware_from_memory(&self, bios: Option<&[u8]>) -> AxResult { + let firmware = bios + .or_else(|| firmware_image_for_vm(&self.config)) + .ok_or_else(|| { + ax_err_type!( + NotFound, + "LoongArch UEFI boot requires a build-time firmware image" + ) + })?; + self.load_loongarch_uefi_firmware_image(firmware) } - fn load_kernel_from_memory(&self, kernel: &[u8]) -> AxResult { - load_vm_image_from_memory(kernel, self.kernel_load_gpa, self.vm.clone()) + #[cfg(target_arch = "loongarch64")] + fn load_loongarch_uefi_firmware_image(&self, firmware: &[u8]) -> AxResult { + let load_gpa = self + .bios_load_gpa + .ok_or_else(|| ax_err_type!(NotFound, "LoongArch UEFI firmware load addr is missed"))?; + let flash_len = self + .config + .kernel + .memory_regions + .iter() + .find(|region| region.gpa == load_gpa.as_usize()) + .map_or(firmware.len(), |region| region.size); + fill_vm_region(load_gpa, flash_len, 0xff, self.vm.clone())?; + load_vm_image_from_memory(firmware, load_gpa, self.vm.clone()) } - #[cfg(all(feature = "fs", target_arch = "loongarch64"))] - fn load_kernel_from_filesystem(&self, kernel_path: &str) -> AxResult { - let kernel = fs::read_full_image(kernel_path)?; - self.load_kernel_from_memory(&kernel) + #[cfg(target_arch = "loongarch64")] + fn load_loongarch_uefi_firmware_dtb(&self) -> AxResult { + crate::guest_platform::loongarch64::prepare_uefi_runtime_config(&self.vm, &self.config); + crate::guest_platform::loongarch64::load_firmware_fdt(&self.vm, &self.config) } #[cfg(target_arch = "x86_64")] @@ -777,8 +769,14 @@ pub mod fs { if loader.loongarch_uefi_boot() { loader.load_loongarch_uefi_firmware_dtb()?; loader.add_loongarch_uefi_fw_cfg_from_filesystem()?; + loader.load_loongarch_uefi_firmware_from_filesystem()?; + return Ok(()); } else { - loader.load_kernel_from_filesystem(&loader.config.kernel.kernel_path)?; + load_vm_image( + &loader.config.kernel.kernel_path, + loader.kernel_load_gpa, + loader.vm.clone(), + )?; } #[cfg(not(target_arch = "loongarch64"))] load_vm_image( @@ -803,34 +801,7 @@ pub mod fs { } } #[cfg(not(target_arch = "x86_64"))] - { - if loader.config.kernel.effective_boot_protocol() == VMBootProtocol::Uefi { - let flash_len = if let Some(buffer) = firmware_image_for_vm(&loader.config) - { - loader - .config - .kernel - .memory_regions - .iter() - .find(|region| region.gpa == bios_load_addr.as_usize()) - .map_or(buffer.len(), |region| region.size) - } else { - loader - .config - .kernel - .memory_regions - .iter() - .find(|region| region.gpa == bios_load_addr.as_usize()) - .map_or_else(|| image_size(bios_path), |region| Ok(region.size))? - }; - fill_vm_region(bios_load_addr, flash_len, 0xff, loader.vm.clone())?; - } - if let Some(buffer) = firmware_image_for_vm(&loader.config) { - load_vm_image_from_memory(buffer, bios_load_addr, loader.vm.clone())?; - } else { - load_vm_image(bios_path, bios_load_addr, loader.vm.clone())?; - } - } + load_vm_image(bios_path, bios_load_addr, loader.vm.clone())?; } else { return ax_err!(NotFound, "boot firmware load addr is missed"); } @@ -851,11 +822,6 @@ pub mod fs { loader.load_x86_multiboot_info(x86_boot::DEFAULT_BIOS_IMAGE, bios_load_gpa)?; } - #[cfg(target_arch = "loongarch64")] - if loader.loongarch_uefi_boot() { - return Ok(()); - } - // Load Ramdisk image if needed. if let Some(ramdisk_path) = &loader.config.kernel.ramdisk_path { loader.load_ramdisk_from_filesystem(ramdisk_path)?; @@ -864,11 +830,7 @@ pub mod fs { let vm_config = crate::config::build_axvm_config(&loader.config); if let Some(dtb_arc) = get_vm_dtb_arc(&vm_config) { let _dtb_slice: &[u8] = &dtb_arc; - #[cfg(any( - target_arch = "aarch64", - target_arch = "riscv64", - target_arch = "loongarch64" - ))] + #[cfg(any(target_arch = "aarch64", target_arch = "riscv64"))] { let dtb_src = core::ptr::NonNull::new(_dtb_slice.as_ptr() as *mut u8) .ok_or_else(|| ax_err_type!(InvalidData, "Guest DTB pointer is null"))?; @@ -905,6 +867,16 @@ pub mod fs { ); self.add_loongarch_uefi_fw_cfg(kernel, ramdisk) } + + fn load_loongarch_uefi_firmware_from_filesystem(&self) -> AxResult { + let firmware = firmware_image_for_vm(&self.config).ok_or_else(|| { + ax_err_type!( + NotFound, + "LoongArch UEFI boot requires a build-time firmware image" + ) + })?; + self.load_loongarch_uefi_firmware_image(firmware) + } } #[cfg(target_arch = "x86_64")] From 6b6db6cbfc87103f36e9ff6b70ff131807431182 Mon Sep 17 00:00:00 2001 From: szy Date: Mon, 29 Jun 2026 10:07:15 +0800 Subject: [PATCH 50/50] refactor(axvisor): minimize LoongArch guest boot changes --- os/StarryOS/kernel/src/syscall/task/ptrace.rs | 29 +- os/axvisor/src/images/mod.rs | 4 +- .../somehal/src/arch/loongarch64/pch_pic.rs | 5 - .../axaddrspace/src/npt/arch/loongarch64.rs | 11 +- virtualization/axvm/src/lib.rs | 2 - virtualization/axvm/src/manager.rs | 32 +- virtualization/axvm/src/runtime/mod.rs | 10 +- virtualization/axvm/src/runtime/vcpus.rs | 358 +++++++++--------- virtualization/axvm/src/vm.rs | 44 +-- 9 files changed, 201 insertions(+), 294 deletions(-) diff --git a/os/StarryOS/kernel/src/syscall/task/ptrace.rs b/os/StarryOS/kernel/src/syscall/task/ptrace.rs index 483caf5579..93494a460a 100644 --- a/os/StarryOS/kernel/src/syscall/task/ptrace.rs +++ b/os/StarryOS/kernel/src/syscall/task/ptrace.rs @@ -948,7 +948,7 @@ fn ptrace_write_word(tracee: &ProcessData, addr: usize, data: usize) -> AxResult let mut aspace = aspace.lock(); ptrace_populate_remote_range(&mut aspace, addr, size_of::(), MappingFlags::WRITE)?; aspace.write(VirtAddr::from_usize(addr), &data.to_ne_bytes())?; - sync_user_text_patch(addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); Ok(()) } @@ -1121,7 +1121,7 @@ fn remote_write(tracee: &ProcessData, addr: usize, data: &[u8]) -> AxResult { let mut aspace = aspace.lock(); ptrace_populate_remote_range(&mut aspace, addr, data.len(), MappingFlags::WRITE)?; aspace.write(VirtAddr::from_usize(addr), data)?; - sync_user_text_patch(addr, data.len()); + ax_runtime::hal::cpu::asm::flush_icache_all(); Ok(()) } @@ -1217,7 +1217,7 @@ pub fn ptrace_setup_singlestep( }; if orig_insn == EBREAK_INSN { tracee.set_ptrace_ss_saved_insn_for(tid, None); - sync_user_text_patch(next_insn_addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); return; } @@ -1226,7 +1226,7 @@ pub fn ptrace_setup_singlestep( return; } tracee.set_ptrace_ss_saved_insn_for(tid, Some((next_insn_addr, orig_insn as usize))); - sync_user_text_patch(next_insn_addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); } #[cfg(target_arch = "aarch64")] @@ -1261,7 +1261,7 @@ pub fn ptrace_setup_singlestep( }; if orig_insn == AARCH64_BRK_INSN { tracee.set_ptrace_ss_saved_insn_for(tid, None); - sync_user_text_patch(next_insn_addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); return; } @@ -1270,7 +1270,7 @@ pub fn ptrace_setup_singlestep( return; } tracee.set_ptrace_ss_saved_insn_for(tid, Some((next_insn_addr, orig_insn as usize))); - sync_user_text_patch(next_insn_addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); } #[cfg(target_arch = "loongarch64")] @@ -1305,7 +1305,7 @@ pub fn ptrace_setup_singlestep( }; if orig_insn == LOONGARCH_BREAK_INSN { tracee.set_ptrace_ss_saved_insn_for(tid, None); - sync_user_text_patch(next_insn_addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); return; } @@ -1314,7 +1314,7 @@ pub fn ptrace_setup_singlestep( return; } tracee.set_ptrace_ss_saved_insn_for(tid, Some((next_insn_addr, orig_insn as usize))); - sync_user_text_patch(next_insn_addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); } #[cfg(target_arch = "riscv64")] @@ -1327,7 +1327,7 @@ pub fn ptrace_restore_singlestep_insn( let aspace = tracee.aspace(); let mut aspace = aspace.lock(); let restored = ptrace_write_u16_unlocked(&mut aspace, addr, insn as u16).is_ok(); - sync_user_text_patch(addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); if !restored { tracee.set_ptrace_ss_saved_insn_for(tid, Some((addr, insn))); } @@ -1344,7 +1344,7 @@ pub fn ptrace_restore_singlestep_insn( let aspace = tracee.aspace(); let mut aspace = aspace.lock(); let restored = ptrace_write_u32_unlocked(&mut aspace, addr, insn as u32).is_ok(); - sync_user_text_patch(addr, size_of::()); + ax_runtime::hal::cpu::asm::flush_icache_all(); if !restored { tracee.set_ptrace_ss_saved_insn_for(tid, Some((addr, insn))); } @@ -1770,15 +1770,6 @@ fn ptrace_write_u32_unlocked(aspace: &mut AddrSpace, addr: usize, data: u32) -> Ok(()) } -fn sync_user_text_patch(addr: usize, len: usize) { - #[cfg(target_arch = "aarch64")] - ax_runtime::hal::cpu::asm::clean_dcache_range_to_pou(VirtAddr::from_usize(addr), len); - #[cfg(not(target_arch = "aarch64"))] - let _ = (addr, len); - - ax_runtime::hal::cpu::asm::flush_icache_all(); -} - pub fn ptrace_notify_clone(parent_pid: Pid, parent_tid: Pid, child_pid: Pid, event: u32) -> bool { let Ok(parent) = get_process_data(parent_pid) else { return false; diff --git a/os/axvisor/src/images/mod.rs b/os/axvisor/src/images/mod.rs index e053a1b4ce..0f6e12c1eb 100644 --- a/os/axvisor/src/images/mod.rs +++ b/os/axvisor/src/images/mod.rs @@ -345,10 +345,10 @@ impl ImageLoader { initrd: ramdisk, cmdline: self.config.kernel.cmdline.clone(), cpu_num: self.config.base.cpu_num as u16, - platform: Some(crate::guest_platform::loongarch64::fw_cfg_platform_config( + platform: crate::guest_platform::loongarch64::fw_cfg_platform_config( &self.vm, &self.config, - )), + ), }) } diff --git a/platforms/somehal/src/arch/loongarch64/pch_pic.rs b/platforms/somehal/src/arch/loongarch64/pch_pic.rs index 012f3b9c61..e0901d9d5f 100644 --- a/platforms/somehal/src/arch/loongarch64/pch_pic.rs +++ b/platforms/somehal/src/arch/loongarch64/pch_pic.rs @@ -279,11 +279,6 @@ impl Interface for PchPic { ); return self.base_vector.into(); }; - debug!( - "LoongArch ACPI PCH-PIC route: gsi={}, input={}, vector={}, trigger={:?}, \ - polarity={:?}", - route.gsi, route.controller_input, vector, route.trigger, route.polarity - ); self.configure_input(usize::from(route.controller_input), route); vector.into() } diff --git a/virtualization/axaddrspace/src/npt/arch/loongarch64.rs b/virtualization/axaddrspace/src/npt/arch/loongarch64.rs index 60feca181f..155f7441ac 100644 --- a/virtualization/axaddrspace/src/npt/arch/loongarch64.rs +++ b/virtualization/axaddrspace/src/npt/arch/loongarch64.rs @@ -12,7 +12,7 @@ // See the License for the specific language governing permissions and // limitations under the License. -use core::fmt; +use core::{arch::asm, fmt}; use ax_page_table_entry::{GenericPTE, MappingFlags}; use ax_page_table_multiarch::PagingMetaData; @@ -187,7 +187,14 @@ impl PagingMetaData for LoongArchPagingMetaDataL3 { type VirtAddr = GuestPhysAddr; fn flush_tlb(vaddr: Option) { - let _ = vaddr; + unsafe { + // `invtlb 0x6/0x7` may trap on current LVZ bring-up path before the + // guest TLB context is fully configured. Use a conservative global + // invalidation instead. VM creation/setup is not performance critical. + let _ = vaddr; + asm!("invtlb 0x0, $r0, $r0"); + asm!("dbar 0"); + } } } diff --git a/virtualization/axvm/src/lib.rs b/virtualization/axvm/src/lib.rs index 10f79a8206..c988279006 100644 --- a/virtualization/axvm/src/lib.rs +++ b/virtualization/axvm/src/lib.rs @@ -52,8 +52,6 @@ pub use manager::{ inject_current_vcpu_interrupt, register_vm, }; #[cfg(target_arch = "loongarch64")] -pub use manager::{inject_vm_vcpu_external_interrupt, inject_vm_vcpu_interrupt}; -#[cfg(target_arch = "loongarch64")] pub use runtime::loongarch_irq::{ register_guest_irq_route as register_loongarch_guest_irq_route, unregister_guest_irq_routes as unregister_loongarch_guest_irq_routes, diff --git a/virtualization/axvm/src/manager.rs b/virtualization/axvm/src/manager.rs index ba2b961c1d..7c46c57ca0 100644 --- a/virtualization/axvm/src/manager.rs +++ b/virtualization/axvm/src/manager.rs @@ -85,7 +85,7 @@ pub(crate) fn inject_interrupt(vm_id: VMId, vcpu_id: usize, vector: usize) -> Ax /// Inject a virtual interrupt into a VM's vCPU. #[cfg(target_arch = "loongarch64")] -pub fn inject_vm_vcpu_interrupt(vm_id: VMId, vcpu_id: usize, vector: usize) -> AxResult { +pub(crate) fn inject_vm_vcpu_interrupt(vm_id: VMId, vcpu_id: usize, vector: usize) -> AxResult { use crate::AsVCpuTask; let current = crate::host::task::current_task(); @@ -99,36 +99,6 @@ pub fn inject_vm_vcpu_interrupt(vm_id: VMId, vcpu_id: usize, vector: usize) -> A crate::runtime::vcpus::queue_interrupt(vm_id, vcpu_id, vector) } -/// Inject a routed external interrupt into a VM's vCPU. -#[cfg(target_arch = "loongarch64")] -pub fn inject_vm_vcpu_external_interrupt( - vm_id: VMId, - vcpu_id: usize, - vector: usize, - physical_irq: usize, -) -> AxResult { - use crate::AsVCpuTask; - - let current = crate::host::task::current_task(); - if let Some(task) = current.try_as_vcpu_task() - && task.vm().id() == vm_id - && task.vcpu.id() == vcpu_id - { - let Some(vector) = task - .vm() - .loongarch_external_irq_vector(vector, physical_irq) - else { - return Ok(()); - }; - return task - .vcpu - .get_arch_vcpu() - .inject_external_interrupt(vector, physical_irq); - } - - crate::runtime::vcpus::queue_external_interrupt(vm_id, vcpu_id, vector, physical_irq) -} - /// Return the current VM ID from the vCPU currently executing on this CPU. pub fn current_vm_id() -> Option { get_current_vcpu::().map(|vcpu| vcpu.vm_id()) diff --git a/virtualization/axvm/src/runtime/mod.rs b/virtualization/axvm/src/runtime/mod.rs index 2de93d28b4..13b61a93be 100644 --- a/virtualization/axvm/src/runtime/mod.rs +++ b/virtualization/axvm/src/runtime/mod.rs @@ -59,19 +59,11 @@ pub fn start() { } // Do not exit until all VMs are stopped. - info!( - "VMM wait enter, running VM count: {}", - RUNNING_VM_COUNT.load(Ordering::Acquire) - ); crate::host::task::wait_queue_wait_until(&VMM, || { let vm_count = RUNNING_VM_COUNT.load(Ordering::Acquire); - info!("VMM wait condition check, running VM count: {vm_count}"); + debug!("a VM exited, current running VM count: {vm_count}"); vm_count == 0 }); - info!( - "VMM wait leave, running VM count: {}", - RUNNING_VM_COUNT.load(Ordering::Acquire) - ); } pub fn add_running_vm_count(count: usize) { diff --git a/virtualization/axvm/src/runtime/vcpus.rs b/virtualization/axvm/src/runtime/vcpus.rs index 8f9ea3867c..78da5558fb 100644 --- a/virtualization/axvm/src/runtime/vcpus.rs +++ b/virtualization/axvm/src/runtime/vcpus.rs @@ -565,10 +565,10 @@ fn vcpu_run() { return; }; - debug!("VM[{}] VCpu[{}] waiting for running", vm.id(), vcpu.id()); + info!("VM[{}] VCpu[{}] waiting for running", vm.id(), vcpu.id()); wait_for(&vm_vcpus, || vm.running()); - debug!("VM[{}] VCpu[{}] running...", vm.id(), vcpu.id()); + info!("VM[{}] VCpu[{}] running...", vm.id(), vcpu.id()); #[cfg(target_arch = "x86_64")] super::x86_irq::enable_ioapic_irq_forwarding(&vm, &vcpu); mark_vcpu_running(vm_id); @@ -580,209 +580,201 @@ fn vcpu_run() { super::x86_irq::drain_pending_ioapic_irqs(&vm, &vcpu); match vm.run_vcpu(vcpu_id) { - Ok(exit_reason) => { - #[cfg(target_arch = "loongarch64")] - trace!("VM[{vm_id}] VCpu[{vcpu_id}] vm.run_vcpu returned: {exit_reason:?}"); - - match exit_reason { - AxVCpuExitReason::Hypercall { nr, args } => { - debug!("Hypercall [{nr}] args {args:x?}"); - use crate::runtime::hvc::HyperCall; - - match HyperCall::new(vm.clone(), nr, args) { - Ok(hypercall) => { - let ret_val = match hypercall.execute() { - Ok(ret_val) => ret_val as isize, - Err(err) => { - warn!("Hypercall [{nr:#x}] failed: {err:?}"); - -1 - } - }; - vcpu.set_return_value(ret_val as usize); - } - Err(err) => { - warn!("Hypercall [{nr:#x}] failed: {err:?}"); - } + Ok(exit_reason) => match exit_reason { + AxVCpuExitReason::Hypercall { nr, args } => { + debug!("Hypercall [{nr}] args {args:x?}"); + use crate::runtime::hvc::HyperCall; + + match HyperCall::new(vm.clone(), nr, args) { + Ok(hypercall) => { + let ret_val = match hypercall.execute() { + Ok(ret_val) => ret_val as isize, + Err(err) => { + warn!("Hypercall [{nr:#x}] failed: {err:?}"); + -1 + } + }; + vcpu.set_return_value(ret_val as usize); } - } - AxVCpuExitReason::FailEntry { - hardware_entry_failure_reason, - } => { - warn!( - "VM[{vm_id}] VCpu[{vcpu_id}] run failed with exit code \ - {hardware_entry_failure_reason}" - ); - } - AxVCpuExitReason::ExternalInterrupt { vector } => { - debug!("VM[{vm_id}] run VCpu[{vcpu_id}] get irq {vector}"); - - // TODO: maybe move this irq dispatcher to lower layer to accelerate the interrupt handling - #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv64")))] - crate::host::arceos::dispatch_host_irq(vector as usize); - #[cfg(target_arch = "riscv64")] - vcpu.with_current_cpu_set(|| { - crate::host::arceos::dispatch_host_irq(vector as usize); - vcpu.get_arch_vcpu().latch_hvip_from_hw(); - }); - crate::check_timer_events(); - #[cfg(target_arch = "x86_64")] - super::x86_irq::forward_passthrough_irq_from_vmexit( - &vm, - &vcpu, - vector as usize, - ); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); - } - AxVCpuExitReason::PreemptionTimer => { - crate::timer::check_events(); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_due_pit_irq0(&vm, &vcpu); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); - } - AxVCpuExitReason::InterruptEnd { vector: _vector } => { - #[cfg(target_arch = "x86_64")] - if let Some(vector) = _vector { - super::x86_irq::inject_pending_ioapic_irq_after_eoi(&vm, &vcpu, vector); + Err(err) => { + warn!("Hypercall [{nr:#x}] failed: {err:?}"); } } - AxVCpuExitReason::Halt => { - debug!("VM[{vm_id}] run VCpu[{vcpu_id}] Halt"); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_due_pit_irq0(&vm, &vcpu); - #[cfg(target_arch = "x86_64")] - super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); - #[cfg(target_arch = "x86_64")] - continue; - #[cfg(not(target_arch = "x86_64"))] - wait(&vm_vcpus) + } + AxVCpuExitReason::FailEntry { + hardware_entry_failure_reason, + } => { + warn!( + "VM[{vm_id}] VCpu[{vcpu_id}] run failed with exit code \ + {hardware_entry_failure_reason}" + ); + } + AxVCpuExitReason::ExternalInterrupt { vector } => { + debug!("VM[{vm_id}] run VCpu[{vcpu_id}] get irq {vector}"); + + // TODO: maybe move this irq dispatcher to lower layer to accelerate the interrupt handling + #[cfg(not(any(target_arch = "aarch64", target_arch = "riscv64")))] + crate::host::arceos::dispatch_host_irq(vector as usize); + #[cfg(target_arch = "riscv64")] + vcpu.with_current_cpu_set(|| { + crate::host::arceos::dispatch_host_irq(vector as usize); + vcpu.get_arch_vcpu().latch_hvip_from_hw(); + }); + crate::check_timer_events(); + #[cfg(target_arch = "x86_64")] + super::x86_irq::forward_passthrough_irq_from_vmexit( + &vm, + &vcpu, + vector as usize, + ); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); + } + AxVCpuExitReason::PreemptionTimer => { + crate::timer::check_events(); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_due_pit_irq0(&vm, &vcpu); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); + } + AxVCpuExitReason::InterruptEnd { vector: _vector } => { + #[cfg(target_arch = "x86_64")] + if let Some(vector) = _vector { + super::x86_irq::inject_pending_ioapic_irq_after_eoi(&vm, &vcpu, vector); } - AxVCpuExitReason::Idle => { - trace!("VM[{vm_id}] run VCpu[{vcpu_id}] Idle"); - #[cfg(target_arch = "loongarch64")] - { - crate::check_timer_events(); - if vcpu.get_arch_vcpu().has_enabled_pending_interrupt() { - trace!( - "VM[{vm_id}] VCpu[{vcpu_id}] skips idle wait because guest \ - has enabled pending interrupt" - ); - continue; - } - let idle_timeout = vcpu.get_arch_vcpu().idle_wait_timeout(); + } + AxVCpuExitReason::Halt => { + debug!("VM[{vm_id}] run VCpu[{vcpu_id}] Halt"); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_due_pit_irq0(&vm, &vcpu); + #[cfg(target_arch = "x86_64")] + super::x86_irq::inject_pending_serial_irq(&vm, &vcpu); + #[cfg(target_arch = "x86_64")] + continue; + #[cfg(not(target_arch = "x86_64"))] + wait(&vm_vcpus) + } + AxVCpuExitReason::Idle => { + trace!("VM[{vm_id}] run VCpu[{vcpu_id}] Idle"); + #[cfg(target_arch = "loongarch64")] + { + crate::check_timer_events(); + if vcpu.get_arch_vcpu().has_enabled_pending_interrupt() { trace!( - "VM[{vm_id}] VCpu[{vcpu_id}] host idle wait for {idle_timeout:?}" + "VM[{vm_id}] VCpu[{vcpu_id}] skips idle wait because guest has \ + enabled pending interrupt" ); - ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(true); - ax_std::os::arceos::modules::ax_hal::asm::enable_irqs(); - ax_std::os::arceos::modules::ax_hal::time::busy_wait(idle_timeout); - ax_std::os::arceos::modules::ax_hal::asm::disable_irqs(); - ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(false); - } - #[cfg(not(target_arch = "loongarch64"))] - { - crate::check_timer_events(); + continue; } + let idle_timeout = vcpu.get_arch_vcpu().idle_wait_timeout(); + trace!("VM[{vm_id}] VCpu[{vcpu_id}] host idle wait for {idle_timeout:?}"); + ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(true); + ax_std::os::arceos::modules::ax_hal::asm::enable_irqs(); + ax_std::os::arceos::modules::ax_hal::time::busy_wait(idle_timeout); + ax_std::os::arceos::modules::ax_hal::asm::disable_irqs(); + ax_std::os::arceos::modules::ax_hal::asm::set_timer_irq_enabled(false); } - AxVCpuExitReason::Nothing => {} - AxVCpuExitReason::CpuDown { _state } => { - warn!("VM[{vm_id}] run VCpu[{vcpu_id}] CpuDown state {_state:#x}"); - wait(&vm_vcpus) + #[cfg(not(target_arch = "loongarch64"))] + { + crate::check_timer_events(); } - AxVCpuExitReason::CpuUp { - target_cpu, - entry_point, - arg, - } => { - debug!( - "VM[{vm_id}]'s VCpu[{vcpu_id}] try to boot target_cpu [{target_cpu}] \ - entry_point={entry_point:x} arg={arg:#x}" - ); - - // Get the mapping relationship between all vCPUs and physical CPUs from the configuration - let vcpu_mappings = vm.get_vcpu_affinities_pcpu_ids(); + } + AxVCpuExitReason::Nothing => {} + AxVCpuExitReason::CpuDown { _state } => { + warn!("VM[{vm_id}] run VCpu[{vcpu_id}] CpuDown state {_state:#x}"); + wait(&vm_vcpus) + } + AxVCpuExitReason::CpuUp { + target_cpu, + entry_point, + arg, + } => { + info!( + "VM[{vm_id}]'s VCpu[{vcpu_id}] try to boot target_cpu [{target_cpu}] \ + entry_point={entry_point:x} arg={arg:#x}" + ); - // Find the vCPU ID corresponding to the physical ID - let Some(target_vcpu_id) = - vcpu_mappings.iter().find_map(|(vcpu_id, _, phys_id)| { - (*phys_id == target_cpu as usize).then_some(*vcpu_id) - }) - else { - warn!("Physical CPU ID {target_cpu} not found in VM configuration"); + // Get the mapping relationship between all vCPUs and physical CPUs from the configuration + let vcpu_mappings = vm.get_vcpu_affinities_pcpu_ids(); + + // Find the vCPU ID corresponding to the physical ID + let Some(target_vcpu_id) = + vcpu_mappings.iter().find_map(|(vcpu_id, _, phys_id)| { + (*phys_id == target_cpu as usize).then_some(*vcpu_id) + }) + else { + warn!("Physical CPU ID {target_cpu} not found in VM configuration"); + vcpu.set_return_value(usize::MAX); + continue; + }; + + match vcpu_on(vm.clone(), target_vcpu_id, entry_point, arg as _) { + Ok(()) => { + #[cfg(not(target_arch = "riscv64"))] + vcpu.set_gpr(0, 0); + #[cfg(target_arch = "riscv64")] + vcpu.set_gpr(RiscvGprIndex::A0 as usize, 0); + } + Err(err) => { + warn!("Failed to boot VM[{vm_id}] VCpu[{target_vcpu_id}]: {err:?}"); vcpu.set_return_value(usize::MAX); - continue; - }; - - match vcpu_on(vm.clone(), target_vcpu_id, entry_point, arg as _) { - Ok(()) => { - #[cfg(not(target_arch = "riscv64"))] - vcpu.set_gpr(0, 0); - #[cfg(target_arch = "riscv64")] - vcpu.set_gpr(RiscvGprIndex::A0 as usize, 0); - } - Err(err) => { - warn!("Failed to boot VM[{vm_id}] VCpu[{target_vcpu_id}]: {err:?}"); - vcpu.set_return_value(usize::MAX); - } } } - AxVCpuExitReason::SystemDown => { - warn!("VM[{vm_id}] run VCpu[{vcpu_id}] SystemDown"); - if let Err(err) = vm.shutdown() { - warn!("VM[{vm_id}] shutdown failed: {err:?}"); - } - // Notify all vCPUs to wake up to check the shutdown flag - notify_all_vcpus(vm_id); + } + AxVCpuExitReason::SystemDown => { + warn!("VM[{vm_id}] run VCpu[{vcpu_id}] SystemDown"); + if let Err(err) = vm.shutdown() { + warn!("VM[{vm_id}] shutdown failed: {err:?}"); } - AxVCpuExitReason::SendIPI { + // Notify all vCPUs to wake up to check the shutdown flag + notify_all_vcpus(vm_id); + } + AxVCpuExitReason::SendIPI { + target_cpu, + target_cpu_aux, + send_to_all, + send_to_self, + vector, + } => { + debug!( + "VM[{vm_id}] run VCpu[{vcpu_id}] SendIPI, target_cpu={target_cpu:#x}, \ + target_cpu_aux={target_cpu_aux:#x}, vector={vector}", + ); + let targets = ipi_targets( + &vm, + vcpu_id, target_cpu, target_cpu_aux, send_to_all, send_to_self, - vector, - } => { - debug!( - "VM[{vm_id}] run VCpu[{vcpu_id}] SendIPI, target_cpu={target_cpu:#x}, \ - target_cpu_aux={target_cpu_aux:#x}, vector={vector}", - ); - let targets = ipi_targets( - &vm, - vcpu_id, - target_cpu, - target_cpu_aux, - send_to_all, - send_to_self, + ); + if targets.is_empty() { + warn!( + "VM[{vm_id}] SendIPI has no target: target_cpu={target_cpu:#x}, \ + target_cpu_aux={target_cpu_aux:#x}" ); - if targets.is_empty() { - warn!( - "VM[{vm_id}] SendIPI has no target: target_cpu={target_cpu:#x}, \ - target_cpu_aux={target_cpu_aux:#x}" - ); - continue; - } + continue; + } - if targets.get(vcpu_id) { - crate::inject_current_vcpu_interrupt(vector as _) - .expect("failed to inject self IPI into current vCPU"); - } - let mut remote_targets = targets; - remote_targets.set(vcpu_id, false); - if !remote_targets.is_empty() - && let Err(err) = - vm.inject_interrupt_to_vcpu(remote_targets, vector as _) - { - warn!( - "Failed to inject interrupt {vector} to VM[{vm_id}] targets \ - {remote_targets:?}: {err:?}" - ); - } + if targets.get(vcpu_id) { + crate::inject_current_vcpu_interrupt(vector as _) + .expect("failed to inject self IPI into current vCPU"); } - e => { - warn!("VM[{vm_id}] run VCpu[{vcpu_id}] unhandled vmexit: {e:?}"); + let mut remote_targets = targets; + remote_targets.set(vcpu_id, false); + if !remote_targets.is_empty() + && let Err(err) = vm.inject_interrupt_to_vcpu(remote_targets, vector as _) + { + warn!( + "Failed to inject interrupt {vector} to VM[{vm_id}] targets \ + {remote_targets:?}: {err:?}" + ); } } - } + e => { + warn!("VM[{vm_id}] run VCpu[{vcpu_id}] unhandled vmexit: {e:?}"); + } + }, Err(err) => { error!("VM[{vm_id}] run VCpu[{vcpu_id}] get error {err:?}"); if let Err(err) = vm.shutdown() { @@ -800,7 +792,7 @@ fn vcpu_run() { vm_id, vcpu_id ); wait_for(&vm_vcpus, || !vm.suspending()); - debug!("VM[{}] VCpu[{}] resumed from suspend", vm_id, vcpu_id); + info!("VM[{}] VCpu[{}] resumed from suspend", vm_id, vcpu_id); continue; } diff --git a/virtualization/axvm/src/vm.rs b/virtualization/axvm/src/vm.rs index 6f8c8abe51..e8a41c3985 100644 --- a/virtualization/axvm/src/vm.rs +++ b/virtualization/axvm/src/vm.rs @@ -20,8 +20,6 @@ use ax_errno::{AxError, AxResult, ax_err, ax_err_type}; use ax_kspin::SpinNoIrq as Mutex; use ax_memory_addr::{align_down_4k, align_up_4k}; use axaddrspace::{AddrSpace, MappingFlags}; -#[cfg(target_arch = "loongarch64")] -use axdevice::FwCfgRamRegion; use axdevice::{ AxVmDeviceConfig, AxVmDevices, DeviceBuildContext, DeviceFactoryRegistry, FwCfg, FwCfgPlatformConfig, register_builtin_factories, @@ -101,7 +99,7 @@ pub struct FwCfgDeviceConfig { pub initrd: Option<&'static [u8]>, pub cmdline: Option, pub cpu_num: u16, - pub platform: Option, + pub platform: FwCfgPlatformConfig, } /// Represents a memory region in a virtual machine. @@ -675,9 +673,7 @@ impl AxVM { initrd: config.initrd, cmdline: config.cmdline, cpu_num: config.cpu_num, - platform: config - .platform - .unwrap_or_else(|| self.fw_cfg_platform_config()), + platform: config.platform, }); debug!( "VM[{}] queued fw_cfg device: base={:#x}, size={:#x}, kernel={} bytes, initrd={:?}", @@ -711,40 +707,6 @@ impl AxVM { Ok(()) } - fn fw_cfg_platform_config(&self) -> FwCfgPlatformConfig { - #[cfg(target_arch = "loongarch64")] - { - let inner = self.inner_mut.lock(); - let mut ram_regions = inner - .memory_regions - .iter() - .map(|region| FwCfgRamRegion { - base: region.gpa.as_usize() as u64, - size: region.size() as u64, - }) - .filter(|region| region.size != 0) - .collect::>(); - ram_regions.sort_by_key(|region| region.base); - - if !ram_regions.is_empty() { - let ram_regions: &'static [FwCfgRamRegion] = - Box::leak(ram_regions.into_boxed_slice()); - debug!( - "VM[{}] LoongArch fw_cfg RAM regions: {:?}", - self.id(), - ram_regions - ); - return FwCfgPlatformConfig { - ram_regions, - srat_regions: ram_regions, - ..FwCfgPlatformConfig::default() - }; - } - } - - FwCfgPlatformConfig::default() - } - /// Run a vCPU according to the given vcpu_id. /// /// ## Arguments @@ -909,7 +871,7 @@ impl AxVM { ); return; } - if let Err(err) = crate::inject_vm_vcpu_interrupt(self.id(), 0, event.vector) { + if let Err(err) = crate::manager::inject_vm_vcpu_interrupt(self.id(), 0, event.vector) { warn!( "failed to inject LoongArch VM[{}] PCH-PIC output vector {}: {err:?}", self.id(),