From 09ff9f4e3b6fc77e70b6e1f025d1af94a0cda615 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:37 +0530 Subject: [PATCH 01/37] FROMLIST: ARM: dts: qcom: sdx55: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-1-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts index 082f7ed1a01fb..302c88c479604 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom/qcom-sdx55-t55.dts @@ -251,7 +251,7 @@ &pcie_rc { perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default>; pinctrl-names = "default"; From 0fd853efea80de1d11fea2ac25f470917780453e Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:38 +0530 Subject: [PATCH 02/37] FROMLIST: arm64: dts: qcom: msm8996: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-2-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index d55e4075040ff..5b42c266557ab 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -192,7 +192,7 @@ &pcie0 { perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 77ad613590a3a..2abcc733dad88 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -280,7 +280,7 @@ vdda-supply = <&vreg_l28a_0p925>; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; &pcie_phy { From 37e69fc2c8bae514f0cea1748474f61bc98311d2 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:39 +0530 Subject: [PATCH 03/37] FROMLIST: arm64: dts: qcom: sdm845: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-3-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 02416812b6a7f..24c0e97bb122a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -619,7 +619,7 @@ &pcie0 { status = "okay"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pcie0_3p3v_dual>; From f9ec93522a4e575e2d4209d68e0df81fcf0b7db6 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:40 +0530 Subject: [PATCH 04/37] FROMLIST: arm64: dts: qcom: sc8180x: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-4-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 2 +- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index d86a31ddede29..44bf3db01d3ae 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -458,7 +458,7 @@ &pcie3 { perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 180 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie3_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index aff398390eba7..a4644ecca5361 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -559,7 +559,7 @@ &pcie1 { perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 177 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; From 3221397785ce4a7ac90f601ba0bb9061d06c516f Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:41 +0530 Subject: [PATCH 05/37] FROMLIST: arm64: dts: qcom: sm8150: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-5-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 0e101096209ab..8da494de4308a 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1905,7 +1905,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; From 2b4dcf3c7a0d4a534b6d0c8f91819e7324594752 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:42 +0530 Subject: [PATCH 06/37] FROMLIST: arm64: dts: qcom: sm8250: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-6-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 7076720413ab2..eca66d1c1c5b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2202,7 +2202,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -2329,7 +2329,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; @@ -2456,7 +2456,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; From 7e5131b34c53f71b6404e0c9ad07bf2bc033e992 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:43 +0530 Subject: [PATCH 07/37] FROMLIST: arm64: dts: qcom: sm8350: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-7-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 5f975d0094658..0897ed1bbc6fe 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -494,7 +494,7 @@ pinctrl-0 = <&pcie0_default_state>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -508,7 +508,7 @@ &pcie1 { perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From 4afed89b5c4f16db3468c249f338ac88fc872f33 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:44 +0530 Subject: [PATCH 08/37] FROMLIST: arm64: dts: qcom: sm8450: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-8-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 56cb6e959e4ee..bb0186ea42c8b 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2035,7 +2035,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -2200,7 +2200,7 @@ phy-names = "pciephy"; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From ef2ac82f7be1647b01f982669f9260cec336a401 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:45 +0530 Subject: [PATCH 09/37] FROMLIST: arm64: dts: qcom: sm8550: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-9-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 2 +- arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index e6ebb643203b6..5eb4626c61290 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -336,7 +336,7 @@ &pcie0 { perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -349,7 +349,7 @@ &pcie1 { perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index ee13e6136a825..4709eb34521d9 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1003,7 +1003,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -1037,7 +1037,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5769be83cfbd3..7703ebfc1b67d 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -739,7 +739,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; @@ -756,7 +756,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 2fb2e0be5e4c6..5ce81ac3ab4ca 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -903,7 +903,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index 81c02ee27fe99..cf4e4e9d9e26c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -510,7 +510,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index 0e6ed6fce6147..d23fe714bd27c 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -584,7 +584,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; From d167ec3c1a5ff41dc08baef87f9b8fba58134fcc Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:46 +0530 Subject: [PATCH 10/37] FROMLIST: arm64: dts: qcom: sm8650: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-10-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 4 ++-- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 0dc994f4e48d9..2123312d88f6b 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1074,7 +1074,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -1108,7 +1108,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index eabc828c05b4c..775ce9f2dba09 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -942,7 +942,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -976,7 +976,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index dd6e33d2dc5d7..8cc0d2cb35151 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -642,7 +642,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; @@ -659,7 +659,7 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index a3982ae229290..c302996a7857d 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -936,7 +936,7 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; From daba1f141f8067f82cf8ccb361050910a3243910 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:47 +0530 Subject: [PATCH 11/37] FROMLIST: arm64: dts: qcom: sm8750: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-11-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8750-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts index 3837f6785320d..2c2753683c69d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8750-mtp.dts @@ -1119,7 +1119,7 @@ }; &pcieport0 { - wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; wifi@0 { From 3f2307773d12423c5a7e79886fd81554cdb74b20 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:48 +0530 Subject: [PATCH 12/37] FROMLIST: arm64: dts: qcom: kaanapali: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-12-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/kaanapali-mtp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts index f9b5b5718b904..f006843d0eb6d 100644 --- a/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts +++ b/arch/arm64/boot/dts/qcom/kaanapali-mtp.dts @@ -933,7 +933,7 @@ }; &pcie_port0 { - wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>; reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; wifi@0 { From 9de6220e3d68b28000de177f46c966982febae53 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:49 +0530 Subject: [PATCH 13/37] FROMLIST: arm64: dts: qcom: sar2130p: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-13-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts index 74778a5b19ba6..71a09e76b3592 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -358,7 +358,7 @@ &pcie0 { perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 57 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; From cbe067ae72effcecac9529ce0d68a61c542486b1 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:50 +0530 Subject: [PATCH 14/37] FROMLIST: arm64: dts: qcom: monaco: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-14-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/monaco-evk.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcs8300-ride.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/monaco-evk.dts b/arch/arm64/boot/dts/qcom/monaco-evk.dts index 9d17ef7d2caf1..b30fc7ecdf32e 100644 --- a/arch/arm64/boot/dts/qcom/monaco-evk.dts +++ b/arch/arm64/boot/dts/qcom/monaco-evk.dts @@ -643,12 +643,12 @@ &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; }; &pcieport1 { reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; }; &pmm8620au_0_gpios { diff --git a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts index e9a8553a8d821..f9891fbcca90c 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs8300-ride.dts @@ -615,7 +615,7 @@ &pcieport0 { reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; wifi@0 { compatible = "pci17cb,1103"; @@ -651,7 +651,7 @@ &pcieport1 { reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; }; &pcie1_phy { From a247be9a624e3a033bcc9d8bb39ff2eeae8f5f47 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:51 +0530 Subject: [PATCH 15/37] FROMLIST: arm64: dts: qcom: lemans: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-15-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 4 ++-- arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 34dfc8d22b6a5..953afca63bc29 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -710,7 +710,7 @@ &pcie0 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -727,7 +727,7 @@ &pcie1 { perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index 40f88498999bd..b5e0e1600fe0e 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -962,7 +962,7 @@ &pcie0 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -972,7 +972,7 @@ &pcie1 { perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; From 279f1a624de66c423d36a57463c64d392d41d7fd Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:52 +0530 Subject: [PATCH 16/37] FROMLIST: arm64: dts: qcom: sa8540p-ride: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-16-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 44177e9b64b52..702ae4cd3d0c1 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -367,7 +367,7 @@ <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; @@ -388,7 +388,7 @@ <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; From 4ea69aa01bcc8de8b456bb80273ad95738907272 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:53 +0530 Subject: [PATCH 17/37] FROMLIST: arm64: dts: qcom: kodiak: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-17-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts | 2 +- arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index bf18c48520813..b1ad1d7c346a2 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -546,7 +546,7 @@ &pcie0 { perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index bb5a42b038f19..3a9fbef89aff4 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -523,7 +523,7 @@ &pcie0 { perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; pinctrl-names = "default"; @@ -540,7 +540,7 @@ &pcie1 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index a5ad796cb65d0..e0275430ef826 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -685,7 +685,7 @@ &pcie0 { perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, @@ -704,7 +704,7 @@ &pcie1 { perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index f47efca42d48d..681a9ff5ef773 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -813,7 +813,7 @@ &pcie0 { perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, From 4144935f1238ae043b4935c4c2c400caa6c5ade9 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:54 +0530 Subject: [PATCH 18/37] FROMLIST: arm64: dts: qcom: talos: Fix PCIe wake GPIO polarity The PCIe WAKE# signal is active-low as defined in the PCIe Base Specification. Fix the wake-gpios polarity by using GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH. Link: https://lore.kernel.org/r/20260611-wake-v2-18-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 2 +- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 51b13b492472f..11231d484cdfd 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -445,7 +445,7 @@ &pcie { perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 294354c034c37..6eca3791e2b98 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -359,7 +359,7 @@ &pcie { perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; From cb8299862496f3077dbca7c7720a48005098b2c6 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:56 +0530 Subject: [PATCH 19/37] FROMLIST: arm64: dts: qcom: msm8998: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst GPIO property are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, and perst-gpios from the controller to pcie0_port0, adding a label to this node to allow board-level overrides, and renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-20-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 3477060116372..0de0eca00d71d 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -928,8 +928,6 @@ #address-cells = <3>; #size-cells = <2>; num-lanes = <1>; - phys = <&pcie_phy>; - phy-names = "pciephy"; status = "disabled"; ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, @@ -969,9 +967,8 @@ power-domains = <&gcc PCIE_0_GDSC>; iommu-map = <0x100 &anoc1_smmu 0x1480 1>; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -979,6 +976,9 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie_phy>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; }; }; From 5e9b70041d39559bf33af6302fc6cf3ef88a73cf Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:57 +0530 Subject: [PATCH 20/37] FROMLIST: arm64: dts: qcom: qcs404: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst GPIO property are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, adding a label to this node to allow board-level overrides. Move perst-gpios from the &pcie controller override to &pcie0_port0 in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-21-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 6 ++++-- arch/arm64/boot/dts/qcom/qcs404.dtsi | 7 +++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi index a22b4501ce1ef..a035546a1b97d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi @@ -101,12 +101,14 @@ &pcie { status = "okay"; - perst-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&perst_state>; }; +&pcie0_port0 { + reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 4328c1dda898c..8166ab4bf01cf 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -1517,12 +1517,9 @@ "pwr", "ahb"; - phys = <&pcie_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1530,6 +1527,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie_phy>; }; }; }; From f8d9f225bbf93f2bcf7667e75cad8bdaf25b5a19 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:58 +0530 Subject: [PATCH 21/37] FROMLIST: arm64: dts: qcom: qcs8550: Move PCIe GPIOs to root port node The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/&pcie1_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-22-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi index 5eb4626c61290..579b0a4f34ebc 100644 --- a/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi @@ -335,26 +335,30 @@ }; &pcie0 { - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; }; &pcie1 { - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3c_0p9>; vdda-pll-supply = <&vreg_l3e_1p2>; From b7f937baf6b823108bd2da0b2720e2617811ec89 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:59 +0530 Subject: [PATCH 22/37] FROMLIST: arm64: dts: qcom: sa8295p: Move PCIe GPIOs to root port node The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie2a, &pcie3a, &pcie3b, and &pcie4 controller overrides to the respective &pcie2a_port0, &pcie3a_port0, &pcie3b_port0, and &pcie4_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-23-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 32 +++++++++++++++--------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index d28d691624279..512de3597581b 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -453,15 +453,17 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -472,15 +474,17 @@ &pcie3a { num-lanes = <2>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -489,15 +493,17 @@ }; &pcie3b { - perst-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3b_default>; status = "okay"; }; +&pcie3b_port0 { + reset-gpios = <&tlmm 153 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; +}; + &pcie3b_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -506,15 +512,17 @@ }; &pcie4 { - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie4_default>; status = "okay"; }; +&pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; +}; + &pcie4_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; From 095a17b411d89050c5ba3afc39faf923b6dc0dab Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:00 +0530 Subject: [PATCH 23/37] FROMLIST: arm64: dts: qcom: sa8540p: Move PCIe GPIOs to root port node The perst/wake GPIO properties are per root port and belong in the root port node, not in the RC controller node. Move perst-gpios/ wake-gpios from the &pcie2a and &pcie3a controller overrides to the respective &pcie2a_port0 and &pcie3a_port0 nodes, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-24-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index 702ae4cd3d0c1..6e73fca4e1bfc 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -366,15 +366,17 @@ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>, <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>; - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2a_default>; status = "disabled"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; @@ -387,15 +389,17 @@ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>, <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>; - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie3a_default>; status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 56 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l11a>; vdda-pll-supply = <&vreg_l3a>; From 98dfe136b176e115c65a6039f36dc50acac5f039 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:01 +0530 Subject: [PATCH 24/37] FROMLIST: arm64: dts: qcom: sar2130p: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the &pcie0 controller override to &pcieport0 in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-25-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts | 6 +++--- arch/arm64/boot/dts/qcom/sar2130p.dtsi | 12 +++++------- 2 files changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts index 71a09e76b3592..6e0557f1c14b9 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts +++ b/arch/arm64/boot/dts/qcom/sar2130p-qar2130p.dts @@ -357,9 +357,6 @@ }; &pcie0 { - perst-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -367,6 +364,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 55 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sar2130p.dtsi b/arch/arm64/boot/dts/qcom/sar2130p.dtsi index 3c9529bb2f76f..346b771407dc9 100644 --- a/arch/arm64/boot/dts/qcom/sar2130p.dtsi +++ b/arch/arm64/boot/dts/qcom/sar2130p.dtsi @@ -1337,9 +1337,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - status = "disabled"; pcieport0: pcie@0 { @@ -1350,6 +1347,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -1464,12 +1463,9 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1477,6 +1473,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From 384ffb541b04729b420e83f2ffcb9d50bc3592f0 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:02 +0530 Subject: [PATCH 25/37] FROMLIST: arm64: dts: qcom: sc8180x: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, pcie2_port0, and pcie3_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-26-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- .../boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 7 ++++-- arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 7 ++++-- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 24 +++++++++---------- 3 files changed, 22 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts index 44bf3db01d3ae..c2d9dcf8ed648 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts @@ -457,14 +457,17 @@ }; &pcie3 { - perst-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie3_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie3_port0 { + reset-gpios = <&tlmm 178 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 180 GPIO_ACTIVE_LOW>; +}; + &pcie3_phy { vdda-phy-supply = <&vreg_l5e_0p88>; vdda-pll-supply = <&vreg_l3c_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts index a4644ecca5361..1b50baf0271bf 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts +++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts @@ -558,14 +558,17 @@ }; &pcie1 { - perst-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 177 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l5e_0p88>; vdda-pll-supply = <&vreg_l3c_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index 45391768e2458..c74ac1b30581d 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1779,13 +1779,11 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_0 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie0_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1793,6 +1791,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -1898,13 +1898,11 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_3 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie3_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie3_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1912,6 +1910,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie3_phy>; }; }; @@ -2018,13 +2018,11 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_1 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie1_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2032,6 +2030,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; @@ -2138,13 +2138,11 @@ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_PCIE_2 0>; interconnect-names = "pcie-mem", "cpu-pcie"; - phys = <&pcie2_phy>; - phy-names = "pciephy"; dma-coherent; status = "disabled"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2152,6 +2150,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2_phy>; }; }; From 91d6a60d128e628a42a98f0d1dea5959498b4f73 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:03 +0530 Subject: [PATCH 26/37] FROMLIST: arm64: dts: qcom: sc8280xp: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcie2a_port0, pcie2b_port0, pcie3a_port0, pcie3b_port0, and pcie4_port0 nodes. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-27-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 24 +++++++++++------- .../boot/dts/qcom/sc8280xp-huawei-gaokun3.dts | 14 ++++++----- .../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 22 +++++++++------- .../dts/qcom/sc8280xp-microsoft-arcata.dts | 22 +++++++++------- .../dts/qcom/sc8280xp-microsoft-blackrock.dts | 14 ++++++----- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 25 ++++++++----------- 6 files changed, 67 insertions(+), 54 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index dcdeefd287283..8961475cdb650 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -628,9 +628,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -639,6 +636,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -647,9 +649,6 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wwan>; pinctrl-names = "default"; @@ -658,6 +657,11 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -668,9 +672,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-names = "default"; @@ -679,6 +680,11 @@ status = "okay"; }; +&pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; +}; + &pcie4_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts index f3c00be67081a..07906ce6cd4e3 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-huawei-gaokun3.dts @@ -739,9 +739,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -750,6 +747,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -760,9 +762,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -772,6 +771,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index abd9c5a67b9ff..b73296e7b26c1 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -933,9 +933,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-names = "default"; @@ -944,6 +941,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -952,9 +954,6 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wwan>; pinctrl-names = "default"; @@ -963,6 +962,11 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -973,9 +977,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-names = "default"; @@ -985,6 +986,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts index f2b4470d4407f..4dd287e6fb951 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts @@ -486,9 +486,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -497,6 +494,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -505,9 +507,6 @@ }; &pcie3a { - perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wwan>; pinctrl-0 = <&pcie3a_default>; @@ -516,6 +515,11 @@ status = "okay"; }; +&pcie3a_port0 { + reset-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>; +}; + &pcie3a_phy { vdda-phy-supply = <&vreg_l6d>; vdda-pll-supply = <&vreg_l4d>; @@ -526,9 +530,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -538,6 +539,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts index 125af356e24b9..c7b5074d06eb4 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-blackrock.dts @@ -624,9 +624,6 @@ }; &pcie2a { - perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_nvme>; pinctrl-0 = <&pcie2a_default>; @@ -635,6 +632,11 @@ status = "okay"; }; +&pcie2a_port0 { + reset-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>; +}; + &pcie2a_phy { vdda-phy-supply = <&vreg_l4d>; vdda-pll-supply = <&vreg_l6d>; @@ -645,9 +647,6 @@ &pcie4 { max-link-speed = <2>; - perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&vreg_wlan>; pinctrl-0 = <&pcie4_default>; @@ -657,6 +656,9 @@ }; &pcie4_port0 { + reset-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1103"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index a2bd6b10e4752..4f8afe6403b65 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2220,9 +2220,6 @@ power-domains = <&gcc PCIE_4_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie4_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie4_port0: pcie@0 { @@ -2233,6 +2230,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie4_phy>; }; }; @@ -2331,9 +2330,6 @@ power-domains = <&gcc PCIE_3B_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie3b_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie3b_port0: pcie@0 { @@ -2344,6 +2340,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie3b_phy>; }; }; @@ -2442,9 +2440,6 @@ power-domains = <&gcc PCIE_3A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie3a_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie3a_port0: pcie@0 { @@ -2455,6 +2450,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie3a_phy>; }; }; @@ -2556,9 +2553,6 @@ power-domains = <&gcc PCIE_2B_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie2b_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie2b_port0: pcie@0 { @@ -2569,6 +2563,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2b_phy>; }; }; @@ -2667,9 +2663,6 @@ power-domains = <&gcc PCIE_2A_GDSC>; required-opps = <&rpmhpd_opp_nom>; - phys = <&pcie2a_phy>; - phy-names = "pciephy"; - status = "disabled"; pcie2a_port0: pcie@0 { @@ -2680,6 +2673,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2a_phy>; }; }; From 7a9fec7d490002400e033e4235fe3759478b3d1b Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:04 +0530 Subject: [PATCH 27/37] FROMLIST: arm64: dts: qcom: sdm845: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-28-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 13 +++++++++---- arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 12 ++++++++---- arch/arm64/boot/dts/qcom/sdm845.dtsi | 14 ++++++-------- 3 files changed, 23 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 24c0e97bb122a..ad00f436800df 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -618,15 +618,17 @@ &pcie0 { status = "okay"; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>; - vddpe-3v3-supply = <&pcie0_3p3v_dual>; pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 134 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { status = "okay"; @@ -636,12 +638,15 @@ &pcie1 { status = "okay"; - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index 091568642faa7..c173b870c943a 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -510,14 +510,16 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1a_0p875>; vdda-pll-supply = <&vreg_l26a_1p2>; @@ -526,14 +528,16 @@ }; &pcie1 { - perst-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 4ae8627d6dbc3..efaa71a1d13ca 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2394,12 +2394,9 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2407,6 +2404,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -2524,12 +2523,9 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2537,6 +2533,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From 9c361769c8e4896d936c6d71c48df46870269800 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:05 +0530 Subject: [PATCH 28/37] FROMLIST: arm64: dts: qcom: sm8150: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides, and renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-29-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 8da494de4308a..f13c67e93db30 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1901,18 +1901,12 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1920,6 +1914,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; + reset-gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; }; @@ -2019,10 +2017,6 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; @@ -2030,7 +2024,7 @@ status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2038,6 +2032,9 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; + reset-gpios = <&tlmm 102 GPIO_ACTIVE_HIGH>; }; }; From bbbf70de622a45eedbc4c1eeefccc3d3d4c1b077 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:06 +0530 Subject: [PATCH 29/37] FROMLIST: arm64: dts: qcom: sm8250: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0 and pcie2_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-30-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 ++++++++++++---------------- 1 file changed, 14 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index eca66d1c1c5b7..a5e2a16f6213e 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2198,12 +2198,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; dma-coherent; @@ -2218,6 +2212,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; + reset-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 81 GPIO_ACTIVE_LOW>; }; }; @@ -2325,19 +2323,13 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; dma-coherent; status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2345,6 +2337,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; + reset-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 84 GPIO_ACTIVE_LOW>; }; }; @@ -2452,19 +2448,13 @@ power-domains = <&gcc PCIE_2_GDSC>; - phys = <&pcie2_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie2_default_state>; dma-coherent; status = "disabled"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2472,6 +2462,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie2_phy>; + reset-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; }; }; From f3c2471c2d5d4c71c9274ca57b98f6e636b55e78 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:07 +0530 Subject: [PATCH 30/37] FROMLIST: arm64: dts: qcom: sm8350: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0 and pcie1_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board file, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-31-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sm8350.dtsi | 14 ++++++-------- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 0897ed1bbc6fe..9a14973fd9725 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -493,12 +493,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5b_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -507,15 +509,17 @@ }; &pcie1 { - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index c830953156ec6..4515a1ccb930b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1583,12 +1583,9 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1596,6 +1593,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -1692,12 +1691,9 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - status = "disabled"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1705,6 +1701,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From b2252b2de10e78f7f56c8fa935dcd307919d5dc5 Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:08 +0530 Subject: [PATCH 31/37] FROMLIST: arm64: dts: qcom: sm8450: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys, phy-names, perst-gpios, and wake-gpios from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Rename perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-32-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index bb0186ea42c8b..fb60ca86ab5b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2031,12 +2031,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; @@ -2080,6 +2074,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; }; }; @@ -2196,12 +2194,6 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; @@ -2277,7 +2269,7 @@ }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2285,6 +2277,10 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; }; }; From 19ef06297f60a0738afdb113493c024ca5351cfa Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:09 +0530 Subject: [PATCH 32/37] FROMLIST: arm64: dts: qcom: sm8550: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and newly labeled pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-33-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 14 ++++++++------ arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts | 7 +++++-- .../dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts | 8 +++++--- arch/arm64/boot/dts/qcom/sm8550.dtsi | 12 +++++------- 6 files changed, 36 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts index 4709eb34521d9..1488ff8b7bed8 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts @@ -1003,9 +1003,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -1013,6 +1010,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1037,15 +1037,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3c_0p9>; vdda-pll-supply = <&vreg_l3e_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 7703ebfc1b67d..e44f6a8877bd2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -739,15 +739,17 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; @@ -756,15 +758,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3c_0p91>; vdda-pll-supply = <&vreg_l3e_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index 5ce81ac3ab4ca..1fe6a8bf0fbcb 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -903,9 +903,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -913,6 +910,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts index cf4e4e9d9e26c..0ff9f3850b0c7 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-samsung-q5q.dts @@ -510,13 +510,16 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1e_0p88>; vdda-pll-supply = <&vreg_l3e_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts index d23fe714bd27c..678e58694b8aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-sony-xperia-yodo-pdx234.dts @@ -584,15 +584,17 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&pm8550vs_2_l1>; vdda-pll-supply = <&pm8550vs_2_l3>; diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 396201905ef25..b08fd5d95852a 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2390,9 +2390,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - operating-points-v2 = <&pcie0_opp_table>; status = "disabled"; @@ -2457,6 +2454,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -2570,9 +2569,6 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - operating-points-v2 = <&pcie1_opp_table>; status = "disabled"; @@ -2645,7 +2641,7 @@ }; }; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2653,6 +2649,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From 922bb6d9dd9f62b20223ebfb65efa236a804c4eb Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:10 +0530 Subject: [PATCH 33/37] FROMLIST: arm64: dts: qcom: talos: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcie_port0, and move perst-gpios/wake-gpios from the &pcie controller overrides to the &pcie_port0 node in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-34-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/qcs615-ride.dts | 8 +++++--- arch/arm64/boot/dts/qcom/talos-evk-som.dtsi | 8 +++++--- arch/arm64/boot/dts/qcom/talos.dtsi | 5 ++--- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts index 11231d484cdfd..91a6414beb593 100644 --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts @@ -444,15 +444,17 @@ }; &pcie { - perst-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; diff --git a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi index 6eca3791e2b98..619880b0ddc6d 100644 --- a/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-evk-som.dtsi @@ -358,15 +358,17 @@ }; &pcie { - perst-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 100 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l12a>; diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index fb1bbc51bb8a4..6efd880b6cd7d 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1357,9 +1357,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie_phy>; - phy-names = "pciephy"; - max-link-speed = <2>; operating-points-v2 = <&pcie_opp_table>; @@ -1391,6 +1388,8 @@ #size-cells = <2>; ranges; bus-range = <0x01 0xff>; + + phys = <&pcie_phy>; }; }; From 65cbf3e0f82d8d256c109a3311bd22eb3df9f0fd Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:11 +0530 Subject: [PATCH 34/37] FROMLIST: arm64: dts: qcom: sm8650: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to the existing pcieport0 and pcie1_port0, allowing board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-35-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- .../boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts | 14 ++++++++------ arch/arm64/boot/dts/qcom/sm8650-hdk.dts | 14 ++++++++------ arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sm8650.dtsi | 10 ++++------ 5 files changed, 33 insertions(+), 27 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts index 2123312d88f6b..74a286bf76960 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-ayaneo-pocket-s2.dts @@ -1074,9 +1074,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -1084,6 +1081,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -1108,15 +1108,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_port0 { /* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */ usb-controller@0 { diff --git a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts index 775ce9f2dba09..02f8760212a9f 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-hdk.dts @@ -942,9 +942,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -952,6 +949,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; @@ -976,15 +976,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3e_0p9>; vdda-pll-supply = <&vreg_l3i_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 8cc0d2cb35151..08107a5592926 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -642,15 +642,17 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l1i_0p88>; vdda-pll-supply = <&vreg_l3i_1p2>; @@ -659,15 +661,17 @@ }; &pcie1 { - wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l3e_0p9>; vdda-pll-supply = <&vreg_l3i_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index c302996a7857d..a18c01a48e4f7 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -936,9 +936,6 @@ }; &pcie0 { - wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; - perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; @@ -946,6 +943,9 @@ }; &pcieport0 { + reset-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_LOW>; + wifi@0 { compatible = "pci17cb,1107"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 160ead25ecf74..c06e306dd3808 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3644,9 +3644,6 @@ num-lanes = <2>; bus-range = <0 0xff>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, @@ -3716,6 +3713,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie0_phy>; }; }; @@ -3837,9 +3836,6 @@ num-lanes = <2>; bus-range = <0 0xff>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - dma-coherent; #address-cells = <3>; @@ -3925,6 +3921,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pcie1_phy>; }; }; From 329c923155f5ed95e1bd07b2e29d71de9d07069a Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:12 +0530 Subject: [PATCH 35/37] FROMLIST: arm64: dts: qcom: kodiak: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per-root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcie0_port and pcie1_port0, and move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcie0_port/&pcie1_port0 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-36-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 10 ++++------ .../boot/dts/qcom/qcm6490-particle-tachyon.dts | 15 ++++++++++----- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 16 ++++++++++------ .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 4 ++-- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- .../qcom/qcs6490-thundercomm-minipc-g1iot.dts | 14 ++++++++------ .../dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++- 9 files changed, 54 insertions(+), 35 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index fa540d8c2615d..aae1774cb99ef 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2286,9 +2286,6 @@ power-domains = <&gcc GCC_PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_clkreq_n>; dma-coherent; @@ -2300,6 +2297,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2416,9 +2415,6 @@ power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; @@ -2434,6 +2430,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index b1ad1d7c346a2..92023aac967d7 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -545,15 +545,17 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -562,8 +564,6 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -572,6 +572,11 @@ status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 3a9fbef89aff4..d0639eea398ee 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -522,15 +522,17 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; pinctrl-names = "default"; status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -539,9 +541,6 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; pinctrl-names = "default"; @@ -559,6 +558,11 @@ status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso index 83908db335afa..8e65a63a533fc 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso @@ -49,8 +49,6 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; @@ -75,6 +73,8 @@ }; &pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + #address-cells = <3>; #size-cells = <2>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 37a3b51323ce5..4274d01c612f3 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -841,8 +841,6 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -867,6 +865,8 @@ }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index e0275430ef826..65687a6aeb6f1 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -684,9 +684,6 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; @@ -695,6 +692,11 @@ status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -703,9 +705,6 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; @@ -732,6 +731,9 @@ }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index 681a9ff5ef773..e5c549c794a9a 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -812,9 +812,6 @@ }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; @@ -823,6 +820,11 @@ status = "okay"; }; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; @@ -831,9 +833,6 @@ }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; @@ -842,6 +841,11 @@ status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5c5e4f1dd2217..9198377c2a8c1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -472,10 +472,13 @@ ap_i2c_tpm: &i2c14 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>, <&ssd_rst_l>, <&pe_wake_odl>; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&pp3300_ssd>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pm8350c_pwm { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 8cac4ce9c8515..655192adbd5d9 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -418,7 +418,6 @@ &pcie1 { status = "okay"; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&nvme_3v3_regulator>; @@ -426,6 +425,10 @@ pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { status = "okay"; From de1e7b022ee08851e8126779ad6de613be6d865f Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:29:13 +0530 Subject: [PATCH 36/37] FROMLIST: arm64: dts: qcom: msm8996: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys and phy-names from the controller to pcie0_port0, pcie1_port0, and pcie2_port0, adding labels to these nodes to allow board-level overrides. Move perst-gpios/wake-gpios from the controller overrides to the respective port nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-37-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 15 ++++++++++--- .../boot/dts/qcom/msm8996-oneplus-common.dtsi | 5 ++++- .../dts/qcom/msm8996-sony-xperia-tone.dtsi | 7 +++++-- .../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 4 +++- arch/arm64/boot/dts/qcom/msm8996.dtsi | 21 ++++++++----------- 5 files changed, 33 insertions(+), 19 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 0c076852b4946..ad435a13ba24c 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -458,23 +458,32 @@ &pcie0 { status = "okay"; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +}; + &pcie1 { status = "okay"; - perst-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>; +}; + &pcie2 { status = "okay"; - perst-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; vdda-supply = <&vreg_l28a_0p925>; }; +&pcie2_port0 { + reset-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi index a4dcc88bb01f0..7a3f8afae22dd 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi @@ -210,12 +210,15 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 5b42c266557ab..20b5eeef46e47 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -191,13 +191,16 @@ }; &pcie0 { - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&pm8994_l28>; status = "okay"; }; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; +}; + &pcie_phy { vdda-phy-supply = <&pm8994_l28>; vdda-pll-supply = <&pm8994_l12>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 2abcc733dad88..3c70a9be45d2f 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -278,8 +278,10 @@ /* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */ vddpe-3v3-supply = <&wlan_en>; vdda-supply = <&vreg_l28a_0p925>; +}; - perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; +&pcie0_port0 { + reset-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 2f67e665996f3..8db1448e5e610 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1900,9 +1900,6 @@ <0x0c100000 0x100000>; reg-names = "parf", "dbi", "elbi","config"; - phys = <&pciephy_0>; - phy-names = "pciephy"; - #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>, @@ -1951,7 +1948,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie0_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -1959,6 +1956,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pciephy_0>; }; }; @@ -1977,9 +1976,6 @@ reg-names = "parf", "dbi", "elbi","config"; - phys = <&pciephy_1>; - phy-names = "pciephy"; - #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>, @@ -2028,7 +2024,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie1_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2036,6 +2032,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pciephy_1>; }; }; @@ -2052,9 +2050,6 @@ reg-names = "parf", "dbi", "elbi","config"; - phys = <&pciephy_2>; - phy-names = "pciephy"; - #address-cells = <3>; #size-cells = <2>; ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>, @@ -2102,7 +2097,7 @@ "bus_master", "bus_slave"; - pcie@0 { + pcie2_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; @@ -2110,6 +2105,8 @@ #address-cells = <3>; #size-cells = <2>; ranges; + + phys = <&pciephy_2>; }; }; }; From c253d0f7d733ebdd7bd97135ebe1293d1186971e Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Thu, 11 Jun 2026 10:28:55 +0530 Subject: [PATCH 37/37] FROMLIST: arm64: dts: qcom: lemans: Move PCIe phy and GPIOs to root port node The PCIe phy reference and the perst/wake GPIO properties are per root port and belong in the root port node (pcie@0), not in the RC controller node. Move phys from the controller to pcieport0 and pcieport1. Add the missing pcieport1 label to the pcie1 root port node to allow board-level overrides. Move perst-gpios/wake-gpios from the &pcie0/&pcie1 controller overrides to the respective &pcieport0/ &pcieport1 nodes in the board files, renaming perst-gpios to reset-gpios to match the binding used in the root port context. Link: https://lore.kernel.org/r/20260611-wake-v2-19-2744251b1181@oss.qualcomm.com Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Krishna Chaitanya Chundru Signed-off-by: Ziyue Zhang --- arch/arm64/boot/dts/qcom/lemans-evk.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi | 16 ++++++++++------ arch/arm64/boot/dts/qcom/lemans.dtsi | 10 +++++----- 3 files changed, 25 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/lemans-evk.dts b/arch/arm64/boot/dts/qcom/lemans-evk.dts index 953afca63bc29..0db0e8005a825 100644 --- a/arch/arm64/boot/dts/qcom/lemans-evk.dts +++ b/arch/arm64/boot/dts/qcom/lemans-evk.dts @@ -709,15 +709,17 @@ }; &pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie0_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; @@ -726,15 +728,17 @@ }; &pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_default_state>; pinctrl-names = "default"; status = "okay"; }; +&pcieport1 { + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; diff --git a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi index b5e0e1600fe0e..3e61417cab751 100644 --- a/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans-ride-common.dtsi @@ -961,25 +961,29 @@ }; &pcie0 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_default_state>; status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +&pcieport0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; +}; +&pcie1 { pinctrl-names = "default"; pinctrl-0 = <&pcie1_default_state>; status = "okay"; }; +&pcieport1 { + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; +}; + &pcie0_phy { vdda-phy-supply = <&vreg_l5a>; vdda-pll-supply = <&vreg_l1c>; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 353a6e6fd3acb..9c1b1cdf0eea3 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2770,8 +2770,6 @@ power-domains = <&gcc PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55>; @@ -2783,6 +2781,8 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2943,19 +2943,19 @@ power-domains = <&gcc PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; status = "disabled"; - pcie@0 { + pcieport1: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges;