Repositories list

• Cores-VeeR-EL2

  Public

  chipsalliance/Cores-VeeR-EL2’s past year of commit activity
  VeeR EL2 Core

  fpgaprocessorriscv+ 11

  fpgaprocessorriscvrtlrisc-vopen-source-hardwarefusesocverilatorriscv32western-digital+ 4

  SystemVerilog

  •

  Apache License 2.0

  •9999 forks•334334 stars•3333 issues•1111 pull requests•Updated Apr 21, 2026Apr 21, 2026

• caliptra-mcu-sw

  Public

  chipsalliance/caliptra-mcu-sw’s past year of commit activity
  Caliptra MCU Software

  Rust

  •

  Apache License 2.0

  •6161 forks•2727 stars•148148 issues•3737 pull requests•Updated Apr 21, 2026Apr 21, 2026

• verilator

  Public

  chipsalliance/verilator’s past year of commit activity
  Verilator open-source SystemVerilog simulator and lint system

  SystemVerilog

  •

  Other

  •795795 forks•4343 stars•00 issues•00 pull requests•Updated Apr 21, 2026Apr 21, 2026

• t1

  Public

  chipsalliance/t1’s past year of commit activity
  Scala

  •

  Apache License 2.0

  •4343 forks•312312 stars•1919 issues•2929 pull requests•Updated Apr 21, 2026Apr 21, 2026

• i3c-core

  Public

  chipsalliance/i3c-core’s past year of commit activity
  SystemVerilog

  •

  Apache License 2.0

  •2626 forks•4747 stars•1212 issues•44 pull requests•Updated Apr 21, 2026Apr 21, 2026

• sv-tests-results

  Public

  chipsalliance/sv-tests-results’s past year of commit activity
  Output of the sv-tests runs.

  HTML

  •66 forks•99 stars•00 issues•00 pull requests•Updated Apr 21, 2026Apr 21, 2026

• sv-tests

  Public

  chipsalliance/sv-tests’s past year of commit activity
  Test suite designed to check compliance with the SystemVerilog standard.

  rtlverilogsystemverilog+ 3

  rtlverilogsystemveriloghdlcompliance-testingsymbiflow

  SystemVerilog

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  ISC License

  •8888 forks•372372 stars•4444 issues•1919 pull requests•Updated Apr 21, 2026Apr 21, 2026

• chisel

  Public

  chipsalliance/chisel’s past year of commit activity
  Chisel: A Modern Hardware Design Language

  scalachip-generatorchisel+ 4

  scalachip-generatorchiselrtlchisel3firrtlverilog

  Scala

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  Apache License 2.0

  •650650 forks•4.6k4.6k stars•352352 issues•148148 pull requests•Updated Apr 20, 2026Apr 20, 2026

• caliptra-sw

  Public

  chipsalliance/caliptra-sw’s past year of commit activity
  Caliptra software (ROM, FMC, runtime firmware), and libraries/tools needed to build and test

  Rust

  •

  Apache License 2.0

  •9797 forks•148148 stars•222222 issues•8181 pull requests•Updated Apr 20, 2026Apr 20, 2026

• caliptra-ureg

  Public

  chipsalliance/caliptra-ureg’s past year of commit activity
  Rust

  •

  Apache License 2.0

  •66 forks•88 stars•00 issues•22 pull requests•Updated Apr 20, 2026Apr 20, 2026

• Caliptra

  Public

  chipsalliance/Caliptra’s past year of commit activity
  Caliptra IP and firmware for integrated Root of Trust block

  Apache License 2.0

  •6565 forks•398398 stars•8888 issues•99 pull requests•Updated Apr 20, 2026Apr 20, 2026

• caliptra-rtl

  Public

  chipsalliance/caliptra-rtl’s past year of commit activity
  HW Design Collateral for Caliptra RoT IP

  SystemVerilog

  •

  Apache License 2.0

  •8484 forks•134134 stars•8686 issues•2626 pull requests•Updated Apr 20, 2026Apr 20, 2026

• caliptra-lwip

  Public
  C

  •

  Other

  •00 forks•00 stars•00 issues•00 pull requests•Updated Apr 20, 2026Apr 20, 2026

• sv-tools

  Public
  A SystemVerilog toolchain / suite, encompassing a number of open source tools for working with SystemVerilog and UVM

  Apache License 2.0

  •00 forks•99 stars•00 issues•00 pull requests•Updated Apr 20, 2026Apr 20, 2026

• caliptra-infra

  Public
  Various tools used for Caliptra's Continuous Integration flows

  SystemVerilog

  •

  Apache License 2.0

  •55 forks•22 stars•66 issues•33 pull requests•Updated Apr 17, 2026Apr 17, 2026

• firtool-resolver

  Public

  chipsalliance/firtool-resolver’s past year of commit activity
  Shell

  •22 forks•55 stars•00 issues•33 pull requests•Updated Apr 16, 2026Apr 16, 2026

• caliptra-dpe

  Public

  chipsalliance/caliptra-dpe’s past year of commit activity
  High level module that implements DPE and defines high-level traits that are used to communicate with the crypto peripherals and PCRs

  Rust

  •

  Apache License 2.0

  •3333 forks•2121 stars•1717 issues•99 pull requests•Updated Apr 16, 2026Apr 16, 2026

• caliptra-ss

  Public

  chipsalliance/caliptra-ss’s past year of commit activity
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

  securityrotocp+ 3

  securityrotocproot-of-trustcaliptraopencomputeproject

  SystemVerilog

  •

  Apache License 2.0

  •4040 forks•4040 stars•5555 issues•1515 pull requests•Updated Apr 16, 2026Apr 16, 2026

• chips-alliance-website

  Public
  SCSS

  •

  MIT License

  •77 forks•55 stars•88 issues•22 pull requests•Updated Apr 16, 2026Apr 16, 2026

• adams-bridge

  Public

  chipsalliance/adams-bridge’s past year of commit activity
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)

  cryptographydigital-signaturelattice+ 2

  cryptographydigital-signaturelatticepqcml-dsa-87

  SystemVerilog

  •

  Apache License 2.0

  •1313 forks•4949 stars•1919 issues•44 pull requests•Updated Apr 14, 2026Apr 14, 2026

• tac

  Public
  CHIPS Alliance Technical Advisory Council

  Apache License 2.0

  •2525 forks•88 stars•3636 issues•11 pull request•Updated Apr 7, 2026Apr 7, 2026

• caliptra-cfi

  Public

  chipsalliance/caliptra-cfi’s past year of commit activity
  Code-flow Integrity module to mitigate glitches and fault injections

  Rust

  •

  Apache License 2.0

  •44 forks•33 stars•22 issues•00 pull requests•Updated Apr 6, 2026Apr 6, 2026

• rocket-pcb

  Public

  chipsalliance/rocket-pcb’s past year of commit activity
  PCB libraries and templates for rocket-chip based FPGA/ASIC designs

  Verilog

  •

  Apache License 2.0

  •44 forks•1616 stars•00 issues•11 pull request•Updated Apr 6, 2026Apr 6, 2026

• rocket-pcblib

  Public

  chipsalliance/rocket-pcblib’s past year of commit activity
  Apache License 2.0

  •11 fork•22 stars•00 issues•00 pull requests•Updated Apr 6, 2026Apr 6, 2026

• Surelog

  Public
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Window…

  parserlinterpreprocessor+ 11

  parserlinterpreprocessorantlrverilogpython-apisystemveriloguvmelaborationvpi+ 4

  C++

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  Apache License 2.0

  •7979 forks•457457 stars•4747 issues•00 pull requests•Updated Apr 5, 2026Apr 5, 2026

• riscv-dv

  Public
  Random instruction generator for RISC-V processor verification

  Python

  •

  Apache License 2.0

  •378378 forks•1.3k1.3k stars•132132 issues•2626 pull requests•Updated Apr 3, 2026Apr 3, 2026

• guineveer

  Public

  chipsalliance/guineveer’s past year of commit activity
  https://chipsalliance.github.io/guineveer/

  C

  •

  Apache License 2.0

  •44 forks•88 stars•00 issues•00 pull requests•Updated Apr 3, 2026Apr 3, 2026

• firrtl-spec

  Public

  chipsalliance/firrtl-spec’s past year of commit activity
  The specification for the FIRRTL language

  TeX

  •3131 forks•6565 stars•2525 issues•1919 pull requests•Updated Apr 1, 2026Apr 1, 2026

• caliptra-web

  Public

  chipsalliance/caliptra-web’s past year of commit activity
  Python

  •

  Apache License 2.0

  •77 forks•11 star•00 issues•11 pull request•Updated Apr 1, 2026Apr 1, 2026

• caliptra-SPDM-Responder-Validator

  Public
  C

  •

  BSD 3-Clause "New" or "Revised" License

  •00 forks•00 stars•00 issues•00 pull requests•Updated Mar 27, 2026Mar 27, 2026