diff --git a/chipcompiler/data/parameter.py b/chipcompiler/data/parameter.py
index a11f698..187351c 100644
--- a/chipcompiler/data/parameter.py
+++ b/chipcompiler/data/parameter.py
@@ -5,6 +5,148 @@
 from copy import deepcopy
 from dataclasses import dataclass, field
 
+# ================= 1. IHP SG13G2 (Explicit) =================
+SG13G2_PARAMETERS_TEMPLATE = {
+    "PDK": "sg13g2",
+    "Design": "", "Top module": "",
+    "Die": {"Size": [], "Area": 0},
+    "Core": {
+        "Size": [], "Area": 0, "Bounding box": "",
+        "Utilitization": 0.65, "Margin": [17.5, 17.5], "Aspect ratio": 1
+    },
+    "Max fanout": 20,
+    "Target density": 0.65,
+    "Target overflow": 0.1,
+    "Global right padding": 0,
+    "Cell padding x": 0,
+    "Routability opt flag": 1,
+    "Clock": "clk",
+    "Frequency max [MHz]": 100,
+    "Bottom layer": "Metal2",        
+    "Top layer": "Metal5",           
+    "Floorplan": {
+        "Tap distance": 0,           
+        "Auto place pin": {"layer": "Metal3", "width": 300, "height": 600, "sides": []},
+        "Tracks": [
+            {"layer": "Metal1", "x start": 0, "x step": 420, "y start": 0, "y step": 420},
+            {"layer": "Metal2", "x start": 0, "x step": 480, "y start": 0, "y step": 480},  
+            {"layer": "Metal3", "x start": 0, "x step": 420, "y start": 0, "y step": 420},
+            {"layer": "Metal4", "x start": 0, "x step": 480, "y start": 0, "y step": 480},
+            {"layer": "Metal5", "x start": 0, "x step": 420, "y start": 0, "y step": 420},
+        ]
+    },
+    "PDN": {
+        "IO": [
+            {"net name": "VDD", "direction": "INOUT", "is power": True},
+            {"net name": "VSS", "direction": "INOUT", "is power": False}
+        ],
+        "Global connect": [
+            {"net name": "VDD", "instance pin name": "VDD", "is power": True},
+            {"net name": "VSS", "instance pin name": "VSS", "is power": False}
+        ],
+        "Grid": {"layer": "Metal1", "power net": "VDD", "power ground": "VSS", "width": 0.44, "offset": 0},
+        "Stripe": [
+            {"layer": "Metal4", "power net": "VDD", "ground net": "VSS", "width": 1.6, "pitch": 20, "offset": 1},
+            {"layer": "Metal5", "power net": "VDD", "ground net": "VSS", "width": 1.6, "pitch": 20, "offset": 1}
+        ],
+        "Connect layers": [{"layers": ["Metal1", "Metal5"]}, {"layers": ["Metal4", "Metal5"]}]
+    }
+}
+
+# ================= 2. GF180MCU (Explicit) =================
+GF180_PARAMETERS_TEMPLATE = {
+    "PDK": "gf180mcu",
+    "Design": "", "Top module": "",
+    "Die": {"Size": [], "Area": 0},
+    "Core": {
+        "Size": [], "Area": 0, "Bounding box": "",
+        "Utilitization": 0.50, "Margin": [20, 20], "Aspect ratio": 1
+    },
+    "Max fanout": 20,
+    "Target density": 0.45,
+    "Target overflow": 0.1,
+    "Global right padding": 0,
+    "Cell padding x": 0,
+    "Routability opt flag": 1,
+    "Clock": "clk",
+    "Frequency max [MHz]": 100,
+    "Bottom layer": "Metal1",        
+    "Top layer": "Metal5",           
+    "Floorplan": {
+        "Tap distance": 0,           
+        "Auto place pin": {"layer": "Metal3", "width": 400, "height": 800, "sides": []},
+        "Tracks": [
+            {"layer": "Metal1", "x start": 0, "x step": 480, "y start": 0, "y step": 480},
+            {"layer": "Metal2", "x start": 0, "x step": 560, "y start": 0, "y step": 560},  
+            {"layer": "Metal3", "x start": 0, "x step": 480, "y start": 0, "y step": 480},
+            {"layer": "Metal4", "x start": 0, "x step": 560, "y start": 0, "y step": 560},
+            {"layer": "Metal5", "x start": 0, "x step": 480, "y start": 0, "y step": 480},
+        ]
+    },
+    "PDN": {
+        "IO": [
+            {"net name": "VDD", "direction": "INOUT", "is power": True},
+            {"net name": "VSS", "direction": "INOUT", "is power": False}
+        ],
+        "Global connect": [
+            {"net name": "VDD", "instance pin name": "VDD", "is power": True},
+            {"net name": "VSS", "instance pin name": "VSS", "is power": False}
+        ],
+        "Grid": {"layer": "Metal1", "power net": "VDD", "power ground": "VSS", "width": 0.6, "offset": 0},
+        "Stripe": [
+            {"layer": "Metal4", "power net": "VDD", "ground net": "VSS", "width": 2.0, "pitch": 25, "offset": 1},
+            {"layer": "Metal5", "power net": "VDD", "ground net": "VSS", "width": 2.0, "pitch": 25, "offset": 1}
+        ],
+        "Connect layers": [{"layers": ["Metal1", "Metal5"]}, {"layers": ["Metal4", "Metal5"]}]
+    }
+}
+# ================= 3. SKY130 (Explicit) =================
+SKY130_PARAMETERS_TEMPLATE = {
+    "PDK": "sky130",
+    "Design": "", "Top module": "",
+    "Die": {"Size": [], "Area": 0},
+    "Core": {
+        "Size": [], "Area": 0, "Bounding box": "",
+        "Utilitization": 0.40, "Margin": [10, 10], "Aspect ratio": 1
+    },
+    "Max fanout": 20,
+    "Target density": 0.40,
+    "Target overflow": 0.1,
+    "Global right padding": 0,
+    "Cell padding x": 0,
+    "Routability opt flag": 1,
+    "Clock": "clk",
+    "Frequency max [MHz]": 100,
+    "Bottom layer": "met1",        
+    "Top layer": "met5",           
+    "Floorplan": {
+        "Tap distance": 0,           
+        "Auto place pin": {"layer": "met3", "width": 300, "height": 600, "sides": []},
+        "Tracks": [
+            {"layer": "met1", "x start": 0, "x step": 340, "y start": 0, "y step": 340},
+            {"layer": "met2", "x start": 0, "x step": 460, "y start": 0, "y step": 460},  
+            {"layer": "met3", "x start": 0, "x step": 340, "y start": 0, "y step": 340},
+            {"layer": "met4", "x start": 0, "x step": 460, "y start": 0, "y step": 460},
+            {"layer": "met5", "x start": 0, "x step": 340, "y start": 0, "y step": 340},
+        ]
+    },
+    "PDN": {
+        "IO": [
+            {"net name": "VPWR", "direction": "INOUT", "is power": True},
+            {"net name": "VGND", "direction": "INOUT", "is power": False}
+        ],
+        "Global connect": [
+            {"net name": "VPWR", "instance pin name": "VPWR", "is power": True},
+            {"net name": "VGND", "instance pin name": "VGND", "is power": False}
+        ],
+        "Grid": {"layer": "met1", "power net": "VPWR", "power ground": "VGND", "width": 0.48, "offset": 0},
+        "Stripe": [
+            {"layer": "met4", "power net": "VPWR", "ground net": "VGND", "width": 1.6, "pitch": 20, "offset": 1},
+            {"layer": "met5", "power net": "VPWR", "ground net": "VGND", "width": 1.6, "pitch": 20, "offset": 1}
+        ],
+        "Connect layers": [{"layers": ["met1", "met5"]}, {"layers": ["met4", "met5"]}]
+    }
+}
 ICS55_PARAMETERS_TEMPLATE = {
     "PDK":"ICS55",
     "Design":"",
@@ -101,6 +243,73 @@
     }
 }
 
+# ================= 1. IHP SG13G2 Design Parameters =================
+SG13G2_DESIGN_PARAMETERS = {
+    "gcd": {
+        "Design": "gcd",
+        "Top module": "gcd",
+        "Clock": "clk",
+        "Frequency max [MHz]": 100,
+    },
+    "aes_cipher_top": {
+        "Design": "aes",
+        "Top module": "aes_cipher_top",
+        "Clock": "clk",
+        "Frequency max [MHz]": 125,
+    },
+    "picorv32a": {
+        "Design": "picorv32",
+        "Top module": "picorv32a",
+        "Clock": "clk",
+        "Frequency max [MHz]": 50,
+    }
+}
+
+# ================= 2. GF180MCU Design Parameters =================
+GF180_DESIGN_PARAMETERS = {
+    "gcd": {
+        "Design": "gcd",
+        "Top module": "gcd",
+        "Clock": "clk",
+        "Frequency max [MHz]": 50,
+    },
+    "aes_cipher_top": {
+        "Design": "aes",
+        "Top module": "aes_cipher_top",
+        "Clock": "clk",
+        "Frequency max [MHz]": 100,
+    },
+    "picorv32a": {
+        "Design": "picorv32",
+        "Top module": "picorv32a",
+        "Clock": "clk",
+        "Frequency max [MHz]": 33,
+    }
+}
+
+# ================= 3. SKY130 Design Parameters =================
+SKY130_DESIGN_PARAMETERS = {
+    "gcd": {
+        "Design": "gcd",
+        "Top module": "gcd",
+        "Clock": "clk",
+        "Frequency max [MHz]": 100,
+    },
+    "aes_cipher_top": {
+        "Design": "aes",
+        "Top module": "aes_cipher_top",
+        "Clock": "clk",
+        "Frequency max [MHz]": 100,
+    },
+    "picorv32a": {
+        "Design": "picorv32",
+        "Top module": "picorv32a",
+        "Clock": "clk",
+        "Frequency max [MHz]": 50,
+    }
+}
+
+
 ICS55_DESIGN_PARAMETERS = {
     "gcd": {
         "Design": "gcd",
@@ -150,14 +359,31 @@ def get_design_parameters(pdk_name : str, design : str = "", path : str = "") ->
     Return parameters resolved by PDK and optional design name.
     """
     parameters = get_parameters(pdk_name, path)
-    if not design or pdk_name.lower() != "ics55":
+    if not design:
         return parameters
 
-    design_info = ICS55_DESIGN_PARAMETERS.get(design.lower())
-    if design_info is None:
-        return parameters
+    pdk_low = pdk_name.lower()
+    design_low = design.lower()
+    design_info = None
+
+    # Match the PDK to its specific design parameter dictionary
+    match pdk_low:
+        case "ics55":
+            design_info = ICS55_DESIGN_PARAMETERS.get(design_low)
+        case "sg13g2" | "ihp130":
+            # Assuming you created SG13G2_DESIGN_PARAMETERS dictionary
+            design_info = SG13G2_DESIGN_PARAMETERS.get(design_low)
+        case "gf180mcu" | "gf180":
+            # Assuming you created GF180_DESIGN_PARAMETERS dictionary
+            design_info = GF180_DESIGN_PARAMETERS.get(design_low)
+        case "sky130":
+            # Assuming you created SKY130_DESIGN_PARAMETERS dictionary
+            design_info = SKY130_DESIGN_PARAMETERS.get(design_low)
+
+    # If design info was found for that specific PDK, update the parameters
+    if design_info is not None:
+        parameters.data.update(design_info)
 
-    parameters.data.update(design_info)
     return parameters
 
 def update_parameters(parameters_src : dict, parameters_target : dict) -> dict:
diff --git a/chipcompiler/data/pdk.py b/chipcompiler/data/pdk.py
index f91734f..5cafe1b 100644
--- a/chipcompiler/data/pdk.py
+++ b/chipcompiler/data/pdk.py
@@ -52,11 +52,8 @@ def validate(self) -> None:
             msg = "PDK validation failed:\n  " + "\n  ".join(errors)
             logger.error(msg)
             raise ValueError(msg)
-
+              
 def get_pdk(pdk_name : str, pdk_root: str = "") -> PDK:
-    """
-    Return the PDK instance based on the given pdk name.
-    """
     pdk_name_normalized = (pdk_name or "").strip().lower()
     if pdk_name_normalized == "ics55":
         pdk = PDK_ICS55(pdk_root=pdk_root)
@@ -64,7 +61,7 @@ def get_pdk(pdk_name : str, pdk_root: str = "") -> PDK:
         pdk = PDK_SG13G2(pdk_root=pdk_root)
     else:
         pdk = PDK(name=pdk_name_normalized)
-    pdk.validate()
+    
     return pdk
 
 def PDK_ICS55(pdk_root: str = "") -> PDK:
@@ -81,7 +78,7 @@ def PDK_ICS55(pdk_root: str = "") -> PDK:
     ))
     stdcell_dir = "{}/IP/STD_cell/ics55_LLSC_H7C_V1p10C100".format(resolved_root)
 
-    tech_path = "{}/prtech/techLEF/N551P6M_ecos.lef".format(resolved_root)
+    tech_path = "{}/prtech/techLEF/N551P6M.lef".format(resolved_root)
     lef_paths = [
         "{}/ics55_LLSC_H7CR/lef/ics55_LLSC_H7CR_ecos.lef".format(stdcell_dir),
         "{}/ics55_LLSC_H7CL/lef/ics55_LLSC_H7CL_ecos.lef".format(stdcell_dir)