[Feature request] adding FHDL module to synthesizable VHDL support

[ohault]

In the current version of Migen, any FHDL module can be converted into synthesizable Verilog HDL.
This is accomplished by using the convert function in the migen.fhdl.verilog module.

The goal of this ticket is to develop a module for Migen to provide conversion into synthesizable VHDL.

migen.fhdl.vhdl