Adjacent-Partial-Writes.yaml

#--- source.hlsl

StructuredBuffer<int64_t4> InInt : register(t0);
RWStructuredBuffer<uint4> OutInt : register(u1);

[numthreads(1,1,1)]
void main() {
  // Int
  OutInt[0] = countbits(InInt[0]);
  OutInt[1].xyz = countbits(InInt[0].xyz);
  OutInt[1].w = countbits(InInt[0].w);
  OutInt[2].xy = countbits(InInt[0].xy);
}

//--- pipeline.yaml

---
Shaders:
  - Stage: Compute
    Entry: main
    DispatchSize: [1, 1, 1]
Buffers:
  - Name: InInt
    Format: Int64
    Stride: 32
    Data: [0x2A, 0, 0x0f0f0f0f0f0f0f0f, -1]
  - Name: OutInt
    Format: UInt32
    Stride: 16
    Data: [101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112]
  - Name: ExpectedOut # The result we expect
    Format: UInt32
    Stride: 16
    Data: [3, 0, 32, 64, 3, 0, 32, 64, 3, 0, 111, 112]
Results:
  - Result: Test1
    Rule: BufferExact
    Actual: OutInt
    Expected: ExpectedOut
DescriptorSets:
  - Resources:
    - Name: InInt
      Kind: StructuredBuffer
      DirectXBinding:
        Register: 0
        Space: 0
      VulkanBinding:
        Binding: 0
    - Name: OutInt
      Kind: RWStructuredBuffer
      DirectXBinding:
        Register: 1
        Space: 0
      VulkanBinding:
        Binding: 1
...
#--- end

# REQUIRES: Int64

# When compiled with DXC this test encounters a memory coherence issue on Intel
# UHD drivers. This issue does not reproduce when compiled with Clang because
# LLVM's load-store optimization performs correct optimizations that hide the
# problem.
# Bug https://github.com/llvm/offload-test-suite/issues/226


# https://github.com/microsoft/DirectXShaderCompiler/issues/7494
# https://github.com/llvm/llvm-project/issues/142677
# UNSUPPORTED: Vulkan

# RUN: split-file %s %t
# RUN: %dxc_target -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o