Initial QoS support - #1616

Per-interface transmission selection is rendered as tc mqprio when the
driver offloads it and tc ets otherwise.

Signed-off-by: Joachim Wiberg <troglobit@gmail.com>

A 4xx or 5xx from rousette carries the offending node and reason in the
response body, which the exception message drops.  Print it before
raising.

Signed-off-by: Joachim Wiberg <troglobit@gmail.com>

The QoS model has no test coverage.  The tests run on any target: the
software rendering is verified where mqprio and DCB are not offloaded,
the hardware tables where they are, and DSCP classification end to end
through a routed VLAN interface.

Signed-off-by: Joachim Wiberg <troglobit@gmail.com>

Update QoS page, which so far has covered only the Marvell hardware
defaults and the hard-coded VLAN PCP mapping.  Rewrite it around the new
infix-if-qos.yang model, with the IEEE 802.1Q Table 8-5 factory default,
the Table 34-1 layout for reserved streams and what offload capabilities
mean on hardware with and without DCB support.

Signed-off-by: Joachim Wiberg <troglobit@gmail.com>

Figures are centered on the page, tables were left-aligned.  The old
.center-table class was never used; a rule on Material's table wrapper
centers every table without markup.

Material also gives every header cell a 5rem minimum width, so a nine
column table of single digits overflows the page.  Let headers size to
their content.

Signed-off-by: Joachim Wiberg <troglobit@gmail.com>

Material's 1.4 line height leaves visible gaps between box-drawing
characters in CLI output and diagrams.

Signed-off-by: Joachim Wiberg <troglobit@gmail.com>

The mv88e6xxx driver has no DCB ops, so on 88E6390 and 88E6393X boards
the trust order, priority maps and remarking only reached frames that
passed the CPU.  Frames the switch forwarded port to port were
classified by the chip defaults and never remarked.

Add DSA support for the PCP APP selector and the DCB rewrite table, and
mv88e6xxx ops for the per-port PCP and DSCP tables, InitialPri/TagIfBoth
as trust order, the default priority, and the egress PCP and DSCP
tables.  The mqprio map is pushed into the tables as queue priority, so
the traffic class table applies to forwarded frames too.  The scheduler
stays at the chip default WRR.

Frames the CPU sends bypass the switch tables, so their DSCP is still
remarked by the kernel on DSA ports.  Frames the CPU receives carried a
stale priority: tag_dsa read the DSA tag after stripping it, picking up
a byte of the source MAC address instead, which only showed once the
software classifier no longer overwrote it.

The renderer and the operational datastore now treat the driver as DCB
capable with all four trust orders:

    dcb apptrust set dev e1 order dscp pcp
    dcb app add dev e1 pcp-prio 5nd:5 dscp-prio 46:5 default-prio 2
    dcb rewr add dev e2 prio-pcp 5:5nd prio-dscp 5:40

Signed-off-by: Joachim Wiberg <troglobit@gmail.com>

Bridge two ports and send frames through the switch, so on a switch chip
they never pass the CPU and only the hardware tables can classify and
remark them.  The DSCP and PCP on the wire at the egress port reveal the
priority the ingress port assigned, with trust dscp on untagged frames,
trust pcp with a custom map on tagged frames, and remarking off.

PCP is only checked where the driver offloads remarking, there is no
software path for it.  Skipped on a switch port without DCB support,
since forwarded frames never see the kernel's rules there.

Signed-off-by: Joachim Wiberg <troglobit@gmail.com>