Scale
+The same three chips, wired four ways. Watch the links change as you zoom out — and notice the moment the network stops being plumbing and becomes the computer.
+WebGL isn't available, so the scale diagram can't render.
The captions still explain each topology.
AMD EPYC 9654 “Genoa”
NVIDIA H100 SXM5 “GH100”
NVIDIA BlueField-3
AMD EPYC 9654 “Genoa”
NVIDIA H100 SXM5 “GH100”
NVIDIA BlueField-3
The same seven component classes, one row each. The pattern: every chip spends its transistor budget on the thing its job demands most.
| Component class | CPU — EPYC 9654 | GPU — H100 | DPU — BlueField-3 |
|---|---|---|---|
| Component class | CPU — EPYC 9654 | GPU — H100 | DPU — BlueField-3 |
| ⚙ Compute cores | -96× Zen 4general-purpose, branchy code | -132 SMs · 16,896 CUDAmassively parallel math | -16× Arm A78 + 16 DPAcontrol plane + packet I/O | 96× Zen 4general-purpose, branchy code | +132 SMs · 16,896 CUDAmassively parallel math | +16× Arm A78 + 16 DPAcontrol plane + packet I/O |
| 🗄 Cache hierarchy | -96 MB L2 + 384 MB L3hide DRAM latency for random access | -50 MB shared L2rendezvous for 132 SMs, streaming data | -modest L2/L3 on meshpackets stream through, not cached | 96 MB L2 + 384 MB L3hide DRAM latency for random access | +50 MB shared L2rendezvous for 132 SMs, streaming data | +modest L2/L3 on meshpackets stream through, not cached |
| 🧠 Memory system | -12-ch DDR5, 461 GB/shuge capacity (TBs), moderate speed | -5× HBM3, 3.35 TB/sbandwidth at all costs; 80 GB is enough | -1 DDR5 ctrl, 16–32 GBjust a control plane; packets bypass RAM | 12-ch DDR5, 461 GB/shuge capacity (TBs), moderate speed | +5× HBM3, 3.35 TB/sbandwidth at all costs; 80 GB is enough | +1 DDR5 ctrl, 16–32 GBjust a control plane; packets bypass RAM |
| 🔗 Interconnect | -Infinity Fabric via sIODglue 12 chiplets into one CPU | -CoWoS interposer + NVLink 900 GB/sfeed SMs; scale to 256 GPUs | -PCIe Gen5 switch (32 lanes)own devices on the bus, bypass host | Infinity Fabric via sIODglue 12 chiplets into one CPU | +CoWoS interposer + NVLink 900 GB/sfeed SMs; scale to 256 GPUs | +PCIe Gen5 switch (32 lanes)own devices on the bus, bypass host |
| 🌐 Network I/O | -— none on diethat's the DPU's job | -— none on dieNVLink is GPU-to-GPU, not network | -ConnectX-7 · 400 GbEthe whole point of the chip | — none on diethat's the DPU's job | +— none on dieNVLink is GPU-to-GPU, not network | +ConnectX-7 · 400 GbEthe whole point of the chip |
| 🚀 Accelerators | -AVX-512 in-corevector math, no extra blocks | -528 4th-gen Tensor Coresthe chip IS the accelerator | -crypto · RegEx · NVMe-oFinfrastructure tax, in fixed logic | AVX-512 in-corevector math, no extra blocks | +528 4th-gen Tensor Coresthe chip IS the accelerator | +crypto · RegEx · NVMe-oFinfrastructure tax, in fixed logic |
| 📦 Package | -LGA-6096, socketedfield-replaceable server CPU | -SXM5 mezzanine, 700 Wpower + NVLink no slot can carry | -BGA card, air-cooledcheap, permanent, one per server | LGA-6096, socketedfield-replaceable server CPU | +SXM5 mezzanine, 700 Wpower + NVLink no slot can carry | +BGA card, air-cooledcheap, permanent, one per server |