arch-amdgpu: support ACC-selected DS data operands - #7
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Decode the CDNA DS ACC bit and map DS data operands, but not address operands, through the AGPR window of the unified vector register file. Apply the same accumulator offset during operand mapping and instruction execution for 32-, 64-, 96-, and 128-bit DS reads and writes. Also accept all DS primary-encoding variants used by the ACC form and check that mapped AGPR operands remain inside the wavefront's reserved vector register allocation.
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Add support for the CDNA DS ACC encoding, which selects accumulator registers for DS instruction data operands.
Before, DS instructions emitted with ACC=1 are either rejected by the decoder or incorrectly read and write ordinary VGPRs instead of the wavefront’s AGPR allocation.
The DS encoding now decodes the former reserved bit as ACC.
When ACC=1:
Applying the offset in both paths ensures that dependency tracking and the instruction data path refer to the same physical registers.
The change covers 32-, 64-, 96-, and 128-bit DS reads and writes, including multi-data-register instructions.