[codegen] Track thumbv7m-none-eabi, riscv32imc-unknown-none-elf

gherrit-pr-id: Gendq4lo5ioqhx5sfxgkq7iza57vwhm6e

Author: joshlf

.github/workflows/ci.yml

@@ -624,6 +624,11 @@ jobs:
         run: |
           set -eo pipefail
           sudo apt install -qq llvm
+          # The codegen tests evaluate assembly for multiple target architectures.
+          # These tests assume that `rustup` is installed on the host. We must
+          # explicitly add the targets before compilation, because `rustc` aborts
+          # when commanded to emit assembly for a target that has not been added.
+          rustup target add --toolchain $(./cargo.sh --version nightly) thumbv7m-none-eabi riscv32imc-unknown-none-elf
           ./cargo.sh +nightly install --quiet cargo-show-asm
           RUSTFLAGS="$RUSTFLAGS -Awarnings" ./cargo.sh +nightly test \
             --package zerocopy \

benches/formats/coco_dynamic_padding.rs

@@ -1,4 +1,4 @@
-use zerocopy_derive::*;
+use zerocopy::*;
 
 // The only valid value of this type are the bytes `0xC0C0`.
 #[derive(TryFromBytes, KnownLayout, Immutable)]

benches/formats/coco_dynamic_size.rs

@@ -1,4 +1,4 @@
-use zerocopy_derive::*;
+use zerocopy::*;
 
 // The only valid value of this type are the bytes `0xC0C0`.
 #[derive(TryFromBytes, KnownLayout, Immutable)]

benches/formats/coco_static_size.rs

@@ -1,4 +1,4 @@
-use zerocopy_derive::*;
+use zerocopy::*;
 
 // The only valid value of this type are the bytes `0xC0C0`.
 #[derive(TryFromBytes, KnownLayout, Immutable)]

benches/read_from_bytes.cortex-m3

@@ -0,0 +1,16 @@
+bench_read_from_bytes_static_size:
+	push {r7, lr}
+	mov r7, sp
+	cmp r2, #6
+	bne .LBB0_2
+	ldrh r2, [r1]
+	ldr.w r1, [r1, #2]
+	strh r2, [r0, #2]
+	str r1, [r0, #4]
+	movs r1, #1
+	strh r1, [r0]
+	pop {r7, pc}
+.LBB0_2:
+	movs r1, #0
+	strh r1, [r0]
+	pop {r7, pc}

benches/read_from_bytes.generic-rv32

@@ -0,0 +1,26 @@
+bench_read_from_bytes_static_size:
+	li a3, 6
+	bne a2, a3, .LBB0_2
+	lbu a6, 4(a1)
+	lbu a3, 5(a1)
+	lbu a4, 1(a1)
+	lbu a5, 0(a1)
+	lbu a2, 2(a1)
+	lbu a1, 3(a1)
+	slli a4, a4, 8
+	or a4, a4, a5
+	slli a6, a6, 16
+	slli a3, a3, 24
+	or a3, a3, a6
+	slli a1, a1, 8
+	or a1, a1, a2
+	srli a3, a3, 16
+	sh a4, 2(a0)
+	sh a1, 4(a0)
+	sh a3, 6(a0)
+	li a1, 1
+	sh a1, 0(a0)
+	ret
+.LBB0_2:
+	sh zero, 0(a0)
+	ret

benches/read_from_bytes.x86-64

@@ -1,12 +1,12 @@
 bench_read_from_bytes_static_size:
 	mov rcx, rsi
 	cmp rsi, 6
-	jne .LBB5_2
+	jne .LBB0_2
 	mov eax, dword ptr [rdi]
 	movzx ecx, word ptr [rdi + 4]
 	shl rcx, 32
 	or rcx, rax
-.LBB5_2:
+.LBB0_2:
 	shl rcx, 16
 	inc rcx
 	xor eax, eax

benches/read_from_bytes.x86-64.mca

@@ -20,7 +20,7 @@ Instruction Info:
 [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  1      1     0.33                        mov	rcx, rsi
  1      1     0.33                        cmp	rsi, 6
- 1      1     1.00                        jne	.LBB5_2
+ 1      1     1.00                        jne	.LBB0_2
  1      5     0.50    *                   mov	eax, dword ptr [rdi]
  1      5     0.50    *                   movzx	ecx, word ptr [rdi + 4]
  1      1     0.50                        shl	rcx, 32
@@ -52,7 +52,7 @@ Resource pressure by instruction:
 [0]    [1]    [2]    [3]    [4]    [5]    [6.0]  [6.1]  Instructions:
  -      -     0.63   0.36    -     0.01    -      -     mov	rcx, rsi
  -      -     0.05   0.05    -     0.90    -      -     cmp	rsi, 6
- -      -      -      -      -     1.00    -      -     jne	.LBB5_2
+ -      -      -      -      -     1.00    -      -     jne	.LBB0_2
  -      -      -      -      -      -      -     1.00   mov	eax, dword ptr [rdi]
  -      -      -      -      -      -     1.00    -     movzx	ecx, word ptr [rdi + 4]
  -      -     0.97    -      -     0.03    -      -     shl	rcx, 32

benches/read_from_prefix.cortex-m3

@@ -0,0 +1,16 @@
+bench_read_from_prefix_static_size:
+	push {r7, lr}
+	mov r7, sp
+	cmp r2, #6
+	bhs .LBB1_2
+	movs r1, #0
+	strh r1, [r0]
+	pop {r7, pc}
+.LBB1_2:
+	ldr r2, [r1]
+	ldrh r1, [r1, #4]
+	str.w r2, [r0, #2]
+	strh r1, [r0, #6]
+	movs r1, #1
+	strh r1, [r0]
+	pop {r7, pc}

benches/read_from_prefix.generic-rv32

@@ -0,0 +1,26 @@
+bench_read_from_prefix_static_size:
+	li a3, 6
+	bgeu a2, a3, .LBB1_2
+	sh zero, 0(a0)
+	ret
+.LBB1_2:
+	lbu a6, 4(a1)
+	lbu a3, 5(a1)
+	lbu a4, 0(a1)
+	lbu a5, 1(a1)
+	lbu a2, 2(a1)
+	lbu a1, 3(a1)
+	slli a3, a3, 8
+	or a3, a3, a6
+	slli a2, a2, 16
+	slli a1, a1, 24
+	or a1, a1, a2
+	slli a5, a5, 8
+	or a4, a4, a5
+	srli a1, a1, 16
+	sh a4, 2(a0)
+	sh a1, 4(a0)
+	sh a3, 6(a0)
+	li a1, 1
+	sh a1, 0(a0)
+	ret