From 28908e1ccd73d856bbb487b9636f0a4d368dee7a Mon Sep 17 00:00:00 2001 From: Andrew Chen Date: Mon, 13 Apr 2026 22:35:00 +0800 Subject: [PATCH] fix rocc write back --- src/main/scala/rocket/RocketCore.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index 02f3147253..11cca5f425 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -796,7 +796,7 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) if (usingRoCC) { io.rocc.resp.ready := ll_arb.io.in(1).ready - ll_arb.io.in(1).valid := io.rocc.resp.valid + ll_arb.io.in(1).valid := io.rocc.resp.valid && rocc_write_waiting ll_arb.io.in(1).bits.data := io.rocc.resp.bits.data ll_arb.io.in(1).bits.tag := io.rocc.resp.bits.rd } else { @@ -1056,7 +1056,9 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) blocked && !io.dmem.perf.grant } val rocc_blocked = Reg(Bool()) + val rocc_write_waiting = RegInit(false.B) rocc_blocked := !wb_xcpt && !io.rocc.cmd.ready && (io.rocc.cmd.valid || rocc_blocked) + rocc_write_waiting := Mux(io.rocc.cmd.fire, !wb_xcpt && wb_ctrl.rocc && wb_ctrl.wxd, Mux(io.rocc.resp.fire, false.B, rocc_write_waiting)) val ctrl_stalld = id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||