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arch/arm/src/stm32h5: Add support for USB host
Added stm32_usbdrdhost.c which adds USB FS host mode support using the embedded PHY. Added Kconfig to select Device or Host. Example config nucleo-h563zi:usbmsc added to test functionality Signed-off-by: daniellizewski <[email protected]>
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15 files changed

Lines changed: 3468 additions & 11 deletions

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‎Documentation/platforms/arm/stm32h5/index.rst‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ OCTOSPI Yes Implemented as QSPI.
4949
PWR Yes Partial.
5050
SPI Yes
5151
TIM Yes
52-
USB_FS Yes USB Device Support.
52+
USB_FS Yes USB Device and Host Support.
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AES No
5555
CEC No
@@ -86,6 +86,26 @@ WWDG No
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========== ======= =====
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89+
USB FS Host
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-----------
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STM32 USB FS Host Driver Support. The STM32H5 is equipped with a Dual Role USB device
93+
capable of operating as a device or host.
94+
95+
Pre-requisites:
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97+
- CONFIG_USBHOST - Enable USB host support
98+
- CONFIG_STM32H5_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode
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USB host requires a stable 48MHz clock. This should come from a PLL driven by the HSE.
101+
HSI48 cannot be reliably used in host mode due to drift. It can only be used in device mode.
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Options:
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- STM32H5_USBDRD_NCHANNELS - Number of host channels. Default 8
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- STM32H5_USBDRD_DESCSIZE - Maximum size of a descriptor. Default: 128
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89109
References
90110
=================
91111
[RM0481] Reference Manual: STM32H523/33xx, STM32H562/63xx, and STM32H573xx Arm® -based 32-bit MCUs

‎arch/arm/src/stm32h5/CMakeLists.txt‎

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Original file line numberDiff line numberDiff line change
@@ -96,6 +96,10 @@ if(CONFIG_STM32H5_USBFS)
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list(APPEND SRCS stm32_usbfs.c)
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endif()
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if(CONFIG_STM32H5_USBFS_HOST)
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list(APPEND SRCS stm32_usbdrdhost.c)
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endif()
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99103
if(CONFIG_STM32H5_ETHMAC)
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list(APPEND SRCS stm32_ethernet.c)
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endif()

‎arch/arm/src/stm32h5/Kconfig‎

Lines changed: 43 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -651,12 +651,30 @@ config STM32H5_TIM17
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652652
endmenu # STM32H5 Timer Selection
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choice STM32H5_USBFS_MODE
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prompt "USB FS Mode"
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depends on STM32H5_HAVE_USBFS
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default STM32H5_USBFS_NONE
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---help---
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Select the operating mode for the USB_DRD_FS peripheral.
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The hardware supports Device or Host, but not simultaneously.
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config STM32H5_USBFS_NONE
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bool "Disabled"
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config STM32H5_USBFS
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bool "USB Device"
656-
default n
657-
depends on STM32H5_HAVE_USBFS
658667
select USBDEV
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669+
config STM32H5_USBFS_HOST
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bool "USB Host"
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select USBHOST_HAVE_ASYNCH
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select USBHOST
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---help---
674+
Enable USB host mode for USB_DRD_FS peripheral.
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endchoice
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660678
endmenu # STM32H5 Peripheral Selection
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menu "DTS Configuration"
@@ -4473,7 +4491,7 @@ endmenu # Timer Configuration
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comment "USB Device Configuration"
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menu "USB Full Speed Debug Configuration"
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menu "USB Full Speed Device Configuration"
44774495
depends on STM32H5_USBFS
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config STM32H5_USBFS_REGDEBUG
@@ -4485,6 +4503,28 @@ config STM32H5_USBFS_REGDEBUG
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44864504
endmenu
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comment "USB Host Configuration"
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menu "USB Full Speed Host Configuration"
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depends on STM32H5_USBFS_HOST
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4511+
config STM32H5_USBDRD_NCHANNELS
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int "Number of host channels"
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default 8
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range 1 8
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depends on STM32H5_USBFS_HOST
4516+
---help---
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Number of USB host channels to use.
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4519+
config STM32H5_USBDRD_DESCSIZE
4520+
int "Descriptor buffer size"
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default 128
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depends on STM32H5_USBFS_HOST
4523+
---help---
4524+
Size of descriptor/request buffers.
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4526+
endmenu
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44884528
config STM32H5_SERIALDRIVER
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bool
44904530

‎arch/arm/src/stm32h5/Make.defs‎

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Original file line numberDiff line numberDiff line change
@@ -92,6 +92,10 @@ ifeq ($(CONFIG_STM32H5_USBFS),y)
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CHIP_CSRCS += stm32_usbfs.c
9393
endif
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ifeq ($(CONFIG_STM32H5_USBFS_HOST),y)
96+
CHIP_CSRCS += stm32_usbdrdhost.c
97+
endif
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9599
ifeq ($(CONFIG_STM32H5_ETHMAC),y)
96100
CHIP_CSRCS += stm32_ethernet.c
97101
endif

‎arch/arm/src/stm32h5/hardware/stm32_usbfs.h‎

Lines changed: 112 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,9 @@
151151
#define USB_CNTR_ERRM (1 << 13) /* Bit 13: Error Interrupt Mask */
152152
#define USB_CNTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun Interrupt Mask */
153153
#define USB_CNTR_CTRM (1 << 15) /* Bit 15: Correct Transfer Interrupt Mask */
154+
#define USB_CNTR_THR512M (1 << 16) /* Bit 16: 512byte Threshold interrupt mask */
155+
#define USB_CNTR_DDISCM (1 << 17) /* Bit 17: Device disconnection mask */
156+
#define USB_CNTR_HOST (1 << 31) /* Bit 31: Host Mode */
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155158
#define USB_CNTR_ALLINTS (USB_CNTR_L1REQ|USB_CNTR_ESOFM|USB_CNTR_SOFM|USB_CNTR_RESETM|\
156159
USB_CNTR_SUSPM|USB_CNTR_WKUPM|USB_CNTR_ERRM|USB_CNTR_PMAOVRN|\
@@ -164,12 +167,16 @@
164167
#define USB_ISTR_L1REQ (1 << 7) /* Bit 7: LPM L1 state request */
165168
#define USB_ISTR_ESOF (1 << 8) /* Bit 8: Expected Start Of Frame */
166169
#define USB_ISTR_SOF (1 << 9) /* Bit 9: Start Of Frame */
167-
#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request */
170+
#define USB_ISTR_RESET (1 << 10) /* Bit 10: USB RESET request. Device connection in Host mode */
168171
#define USB_ISTR_SUSP (1 << 11) /* Bit 11: Suspend mode request */
169172
#define USB_ISTR_WKUP (1 << 12) /* Bit 12: Wake up */
170173
#define USB_ISTR_ERR (1 << 13) /* Bit 13: Error */
171174
#define USB_ISTR_PMAOVRN (1 << 14) /* Bit 14: Packet Memory Area Over / Underrun */
172175
#define USB_ISTR_CTR (1 << 15) /* Bit 15: Correct Transfer */
176+
#define USB_ISTR_THR512 (1 << 16) /* Bit 16: 512byte threshold interrupt */
177+
#define USB_ISTR_DDISC (1 << 17) /* Bit 17: Device disconnection */
178+
#define USB_ISTR_DCON_STAT (1 << 29) /* Bit 29: Device connection status */
179+
#define USB_ISTR_LS_DCONN (1 << 30) /* Bit 30: Low-speed device connected */
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174181
#define USB_ISTR_ALLINTS (USB_ISTR_L1REQ|USB_ISTR_ESOF|USB_ISTR_SOF|USB_ISTR_RESET|\
175182
USB_ISTR_SUSP|USB_ISTR_WKUP|USB_ISTR_ERR|USB_ISTR_PMAOVRN|\
@@ -210,18 +217,118 @@
210217
#define USB_BCDR_SDET (1 << 6) /* Bit 6: Secondary detection (SD) status */
211218
#define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */
212219
#define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */
220+
#define USB_BCDR_DPPD (1 << 15) /* Bit 15: DP pull-down control (host mode) */
221+
222+
/****************************************************************************
223+
* USB DRD Host Mode Register Definitions
224+
****************************************************************************/
225+
226+
/* Channel/Endpoint register */
227+
228+
#define USB_CHEP_ADDR_SHIFT (0) /* Bits 3-0: Endpoint address */
229+
#define USB_CHEP_ADDR_MASK (0xf << USB_CHEP_ADDR_SHIFT)
230+
#define USB_CHEP_TX_STTX_SHIFT (4) /* Bits 5-4: Status TX */
231+
#define USB_CHEP_TX_STTX_MASK (3 << USB_CHEP_TX_STTX_SHIFT)
232+
# define USB_CHEP_TX_STTX_DIS (0 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX disabled */
233+
# define USB_CHEP_TX_STTX_STALL (1 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX stalled */
234+
# define USB_CHEP_TX_STTX_NAK (2 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX NAK */
235+
# define USB_CHEP_TX_STTX_VALID (3 << USB_CHEP_TX_STTX_SHIFT) /* Channel TX valid */
236+
# define USB_CHEP_TX_DTOG1 (1 << USB_CHEP_TX_STTX_SHIFT) /* TX Data Toggle bit 1 */
237+
# define USB_CHEP_TX_DTOG2 (2 << USB_CHEP_TX_STTX_SHIFT) /* TX Data Toggle bit 2 */
238+
239+
#define USB_CHEP_DTOG_TX (1 << 6) /* Bit 6: Data Toggle TX */
240+
#define USB_CHEP_VTTX (1 << 7) /* Bit 7: Valid transaction transmitted */
241+
#define USB_CHEP_KIND (1 << 8) /* Bit 8: Endpoint/Channel KIND */
242+
#define USB_CHEP_UTYPE_SHIFT (9) /* Bits 10-9: USB type of transaction */
243+
#define USB_CHEP_UTYPE_MASK (3 << USB_CHEP_UTYPE_SHIFT)
244+
# define USB_CHEP_UTYPE_BULK (0 << USB_CHEP_UTYPE_SHIFT) /* Bulk transfer */
245+
# define USB_CHEP_UTYPE_CTRL (1 << USB_CHEP_UTYPE_SHIFT) /* Control transfer */
246+
# define USB_CHEP_UTYPE_ISOC (2 << USB_CHEP_UTYPE_SHIFT) /* Isochronous transfer */
247+
# define USB_CHEP_UTYPE_INTR (3 << USB_CHEP_UTYPE_SHIFT) /* Interrupt transfer */
248+
249+
#define USB_CHEP_SETUP (1 << 11) /* Bit 11: Setup transaction completed */
250+
#define USB_CHEP_RX_STRX_SHIFT (12) /* Bits 13-12: Status RX */
251+
#define USB_CHEP_RX_STRX_MASK (3 << USB_CHEP_RX_STRX_SHIFT)
252+
# define USB_CHEP_RX_STRX_DIS (0 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX disabled */
253+
# define USB_CHEP_RX_STRX_STALL (1 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX stalled */
254+
# define USB_CHEP_RX_STRX_NAK (2 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX NAK */
255+
# define USB_CHEP_RX_STRX_VALID (3 << USB_CHEP_RX_STRX_SHIFT) /* Channel RX valid */
256+
# define USB_CHEP_RX_DTOG1 (1 << USB_CHEP_RX_STRX_SHIFT) /* RX Data Toggle bit 1 */
257+
# define USB_CHEP_RX_DTOG2 (2 << USB_CHEP_RX_STRX_SHIFT) /* RX Data Toggle bit 2 */
258+
259+
#define USB_CHEP_DTOG_RX (1 << 14) /* Bit 14: Data Toggle RX */
260+
#define USB_CHEP_VTRX (1 << 15) /* Bit 15: Valid transaction received */
261+
#define USB_CHEP_DEVADDR_SHIFT (16) /* Bits 22-16: Target device address */
262+
#define USB_CHEP_DEVADDR_MASK (0x7f << USB_CHEP_DEVADDR_SHIFT)
263+
#define USB_CHEP_NAK (1 << 23) /* Bit 23: Previous NAK detected */
264+
#define USB_CHEP_LSEP (1 << 24) /* Bit 24: Low Speed Endpoint */
265+
#define USB_CHEP_ERRTX (1 << 25) /* Bit 25: Transmit error */
266+
#define USB_CHEP_ERRRX (1 << 26) /* Bit 26: Receive error */
267+
268+
/* Register mask for preserving r/w bits when modifying toggle bits */
269+
270+
#define USB_CHEP_REG_MASK (USB_CHEP_ERRRX | USB_CHEP_ERRTX | \
271+
USB_CHEP_LSEP | USB_CHEP_DEVADDR_MASK | \
272+
USB_CHEP_VTRX | USB_CHEP_SETUP | \
273+
USB_CHEP_UTYPE_MASK | USB_CHEP_KIND | \
274+
USB_CHEP_VTTX | USB_CHEP_ADDR_MASK | \
275+
USB_CHEP_NAK)
276+
277+
#define USB_CHEP_TX_DTOGMASK (USB_CHEP_TX_STTX_MASK | USB_CHEP_REG_MASK)
278+
#define USB_CHEP_RX_DTOGMASK (USB_CHEP_RX_STRX_MASK | USB_CHEP_REG_MASK)
279+
#define USB_CH_T_MASK ((~USB_CHEP_UTYPE_MASK) & USB_CHEP_REG_MASK)
280+
#define USB_CHEP_DB_MSK (0xffff0f0f)
281+
282+
/* PMA (Packet Memory Area) definitions for host mode */
283+
284+
#define USB_DRD_PMA_SIZE (2048) /* 2KB PMA */
285+
#define USB_DRD_NCHANNELS (8) /* 8 host channels */
286+
287+
/* PMA buffer descriptor structure address calculation
288+
* Each channel has TX and RX buffer descriptors (8 bytes total per channel)
289+
*/
290+
291+
#define USB_PMA_TXBD_OFFSET(ch) ((ch) * 8)
292+
#define USB_PMA_RXBD_OFFSET(ch) ((ch) * 8 + 4)
293+
294+
/* PMA TX buffer descriptor bit definitions */
295+
296+
#define USB_PMA_TXBD_ADDR_SHIFT (2) /* Bits 15:2: TX buffer address */
297+
#define USB_PMA_TXBD_ADDR_MASK (0x3fff << USB_PMA_TXBD_ADDR_SHIFT)
298+
#define USB_PMA_TXBD_COUNT_SHIFT (16) /* Bits 25:16: TX byte count */
299+
#define USB_PMA_TXBD_COUNT_MASK (0x3ff << USB_PMA_TXBD_COUNT_SHIFT)
300+
#define USB_PMA_TXBD_ADDMSK (0xffff0000)
301+
#define USB_PMA_TXBD_COUNTMSK (0x0000ffff)
302+
303+
/* PMA RX buffer descriptor bit definitions */
304+
305+
#define USB_PMA_RXBD_ADDR_SHIFT (2) /* Bits 15-2: RX buffer address */
306+
#define USB_PMA_RXBD_ADDR_MASK (0x3fff << USB_PMA_RXBD_ADDR_SHIFT)
307+
#define USB_PMA_RXBD_COUNT_SHIFT (16) /* Bits 25-16: RX byte count */
308+
#define USB_PMA_RXBD_COUNT_MASK (0x3ff << USB_PMA_RXBD_COUNT_SHIFT)
309+
#define USB_PMA_RXBD_NUM_BLOCK_SHIFT (26) /* Bits 30-26: Number of blocks */
310+
#define USB_PMA_RXBD_NUM_BLOCK_MASK (0x1f << USB_PMA_RXBD_NUM_BLOCK_SHIFT)
311+
#define USB_PMA_RXBD_BLSIZE (1 << 31) /* Bit 31: Block size: 0=2bytes, 1=32bytes */
312+
#define USB_PMA_RXBD_ADDMSK (0xffff0000)
313+
314+
/* PMA start address (after buffer descriptor table)
315+
* BDT size = 8 channels * 8 bytes = 64 bytes, aligned to 64
316+
*/
317+
318+
#define USB_DRD_PMA_BDT_SIZE (USB_DRD_NCHANNELS * 8)
319+
#define USB_DRD_PMA_START_ADDR (USB_DRD_PMA_BDT_SIZE)
213320

214321
/* Reception buffer address */
215322

216-
#define USB_ADDR_RX_SHIFT (2) /* Bits 15:2 ADDRn_RX[15:2]: Reception Buffer Address */
323+
#define USB_ADDR_RX_SHIFT (2) /* Bits 15-2: Reception Buffer Address */
217324
#define USB_ADDR_RX_MASK (0x3fff << USB_ADDR_RX_SHIFT)
218325

219326
/* Reception byte count */
220327

221-
#define USB_COUNT_RX_BL_SIZE (1 << 31) /* Bit 15: BLock SIZE. */
222-
#define USB_COUNT_RX_NUM_BLOCK_SHIFT (26) /* Bits 14-10: Number of blocks */
328+
#define USB_COUNT_RX_BL_SIZE (1 << 31) /* Bit 31: Block size: 0=2bytes, 1=32bytes */
329+
#define USB_COUNT_RX_NUM_BLOCK_SHIFT (26) /* Bits 30-26: Number of blocks */
223330
#define USB_COUNT_RX_NUM_BLOCK_MASK (0x1f << USB_COUNT_RX_NUM_BLOCK_SHIFT)
224-
#define USB_COUNT_RX_SHIFT (16) /* Bits 9-0: Reception Byte Count */
331+
#define USB_COUNT_RX_SHIFT (16) /* Bits 25-16: Reception Byte Count */
225332
#define USB_COUNT_RX_MASK (0x3ff << USB_COUNT_RX_SHIFT)
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227334
#endif /* CONFIG_STM32H5_HAVE_USBFS */

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