diff --git a/adidt/__init__.py b/adidt/__init__.py index 32e9e721..43f517bd 100644 --- a/adidt/__init__.py +++ b/adidt/__init__.py @@ -9,3 +9,4 @@ from adidt.boards.ad9081_fmc import ad9081_fmc from adidt.boards.adrv9009_zu11eg import adrv9009_zu11eg from adidt.boards.adrv9009_pcbz import adrv9009_pcbz +from adidt.boards.adsy1100 import adsy1100_vu11p diff --git a/adidt/boards/__init__.py b/adidt/boards/__init__.py index 569e6bdf..0cb855d9 100644 --- a/adidt/boards/__init__.py +++ b/adidt/boards/__init__.py @@ -1,2 +1,5 @@ from adidt.boards.daq2 import daq2 from adidt.boards.ad9081_fmc import ad9081_fmc +from adidt.boards.adrv9009_zu11eg import adrv9009_zu11eg +from adidt.boards.adrv9009_pcbz import adrv9009_pcbz +from adidt.boards.adsy1100 import adsy1100_vu11p diff --git a/adidt/boards/adsy1100.py b/adidt/boards/adsy1100.py new file mode 100644 index 00000000..4d7eaa96 --- /dev/null +++ b/adidt/boards/adsy1100.py @@ -0,0 +1,77 @@ +from .layout import layout +import numpy as np + + +class adsy1100_vu11p(layout): + """ADSY1100 VU11P board layout map for clocks and DSP""" + + clock = "LTC6952" + + adc = "ad9081_rx" + dac = "ad9081_tx" + + template_filename = "adsy1100_vu11p.tmpl" + output_filename = "adsy1100_vu11p.dts" + + def make_ints(self, cfg, keys): + """Convert keys in a dict to integers. + + Args: + cfg (dict): Configuration. + keys (list): Keys to convert. + + Returns: + dict: Configuration with keys converted to integers. + """ + for key in keys: + if isinstance(cfg[key], float) and cfg[key].is_integer(): + cfg[key] = int(cfg[key]) + return cfg + + def map_clocks_to_board_layout(self, cfg): + """Map JIF configuration to board clock connection layout. + + Args: + cfg (dict): JIF configuration. + + Returns: + dict: Board clock connection layout. + """ + # Fix ups + for key in ["VCO", "vcxo"]: + cfg["clock"][key] = int(np.ceil(cfg["clock"][key])) + + map = {} + clk = cfg["clock"]["output_clocks"] + + # Common + map["sysref_divider"] = { + "source_port": 3, + "divider": clk["AD9084_RX_sysref"]["divider"], + } + + # AD9084 ext PLL + map["converter_clock_rate"] = np.ceil(cfg["clock_ext_pll_adf4382"]["rf_out_frequency"]) + map["converter_clock_rate"] = int(map["converter_clock_rate"]) + + # FPGA side + map["ref_clk_divider"] = { + "source_port": 3, + "divider": clk["adsy1100_AD9084_RX_ref_clk"]["divider"], + } + + map["core_clk_divider"] = { + "source_port": 0, + "divider": clk["adsy1100_AD9084_RX_device_clk"]["divider"], + } + + ccfg = {"map": map, "clock": cfg["clock"]} + + fpga = {} + fpga['fpga'] = cfg["fpga_AD9084_RX"] + if fpga['fpga']['sys_clk_select'] == 'XCVR_QPLL0': + fpga['fpga']['sys_clk_select'] = 'XCVR_QPLL' + # fpga['fpga_dac'] = cfg["fpga_dac"] + + + return ccfg, fpga diff --git a/adidt/boards/layout.py b/adidt/boards/layout.py index f9649d0a..cfad8f5c 100644 --- a/adidt/boards/layout.py +++ b/adidt/boards/layout.py @@ -1,4 +1,4 @@ -from jinja2 import Environment, FileSystemLoader +from jinja2 import Environment, FileSystemLoader, StrictUndefined import os @@ -33,7 +33,7 @@ def gen_dt(self, **kwargs): loc = os.path.dirname(__file__) loc = os.path.join(loc, "..", "templates") file_loader = FileSystemLoader(loc) - env = Environment(loader=file_loader) + env = Environment(loader=file_loader, undefined=StrictUndefined) loc = os.path.join(self.template_filename) template = env.get_template(loc) diff --git a/adidt/templates/adsy1100_vu11p.tmpl b/adidt/templates/adsy1100_vu11p.tmpl new file mode 100644 index 00000000..c0a20273 --- /dev/null +++ b/adidt/templates/adsy1100_vu11p.tmpl @@ -0,0 +1,677 @@ +/dts-v1/; +/plugin/; + +#include +#include + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "{{ converter['device_profile_name'] }}" +#endif + +#ifndef OUT_CLK_SELECT +#define OUT_CLK_SELECT {{ fpga['fpga']['out_clk_select'] }} +#endif + +#ifndef SYS_CLK_SELECT +#define SYS_CLK_SELECT {{ fpga['fpga']['sys_clk_select'] }} +#endif + +#ifndef ASYNM_A_B_MODE +#define ASYNM_A_B_MODE 1 +#endif + +#ifndef HSCI_ENABLE +#define HSCI_ENABLE 0 +#endif + +#ifndef VU11_FIRMWARE_NAME +#define VU11_FIRMWARE_NAME "vu11p.bin" +#endif + +&vu11p_fpga_region { + #address-cells = <2>; + #size-cells = <2>; + + firmware-name = VU11_FIRMWARE_NAME; + + mig_clkout1: clock@0 { + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "vu11p_mig_1"; + compatible = "fixed-clock"; + }; + + clkin_125: clock@1 { + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clkin_ref"; + compatible = "fixed-clock"; + }; + + clkin_62p5: clock@2 { + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "clkin_div2_ref"; + compatible = "fixed-clock"; + }; + + axi_intc_0: interrupt-controller@88160000 { + #interrupt-cells = <2>; + clock-names = "mig_clkout1"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; + interrupt-controller; + interrupt-names = "irq"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>; + reg = <0x0 0x88160000 0x0 0x1000>; + xlnx,kind-of-intr = <0xffffc38>; + xlnx,num-intr-inputs = <25>; + }; + + adf4382_spi: spi@88000000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <8 0>; + num-cs = <0x1>; + reg = <0x0 0x88000000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + adf4382: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&clkin_62p5>; + clock-names = "ref_clk"; + clock-output-names = "adf4382_out_clk"; + adi,power-up-frequency = /bits/ 64 <{{ clock['map']['converter_clock_rate'] }}>; + }; + }; + + ltc6952_spi: spi@881a0000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <9 0>; + num-cs = <2>; + reg = <0x0 0x881A0000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + ltc6952: ltc6952@0 { + compatible = "adi,ltc6952"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <10000000>; + label = "ltc6952"; + + clocks = <&clkin_125> , <<c6948>; + clock-names = "clkin", "vcoin"; + vcoin-clock-scales = <1 10>; + + adi,vco-frequency-hz = <{{ clock['clock']['VCO'] }}>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + clock-output-names = "ltc6952_0_out0", "ltc6952_0_out1", + "ltc6952_0_out2", "ltc6952_0_out3", "ltc6952_0_out4", + "ltc6952_0_out5", "ltc6952_0_out6", "ltc6952_0_out7", + "ltc6952_0_out8", "ltc6952_0_out9", "ltc6952_0_out10"; + + #clock-cells = <1>; + + adi,pulse-generator-mode = <2>; /* Four Pulses */ + + // channel@1 { + // reg = <1>; + // adi,extended-name = "Aurora RF GTH"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@2 { + // reg = <2>; + // adi,extended-name = "Apollo PLL REF CLK"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // adi,sysref-mode = <0>; + // adi,jesd204-sysref-chan; + // }; + channel@3 { + reg = <3>; + adi,extended-name = "Apollo SYSREF"; + adi,divider = <{{ clock['map']['sysref_divider']['divider'] }}>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@4 { + reg = <4>; + adi,extended-name = "VUP JESD SYSREF"; + adi,divider = <{{ clock['map']['sysref_divider']['divider'] }}>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@5 { + reg = <5>; + adi,extended-name = "VUP Core CLK"; + adi,divider = <{{ clock['map']['core_clk_divider']['divider'] }}>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@6 { + reg = <6>; + adi,extended-name = "JESD REF CLK 1"; + adi,divider = <{{ clock['map']['ref_clk_divider']['divider'] }}>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@7 { + reg = <7>; + adi,extended-name = "JESD REF CLK 2"; + adi,divider = <{{ clock['map']['ref_clk_divider']['divider'] }}>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + // channel@8 { + // reg = <8>; + // adi,extended-name = "REF CLL RFPC"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@9 { + // reg = <9>; + // adi,extended-name = "SYNC RFPC"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@10 { + // reg = <10>; + // adi,extended-name = "Auroro RF GTY"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + }; + + ltc6948: ltc6948@1 { + #clock-cells = <0>; + compatible = "adi,ltc6948"; + reg = <1>; + spi-max-frequency = <5000000>; + clocks = <&clkin_125>; + clock-names = "clkin"; + clock-output-names = "ltc6948_out_clk"; + clock-scales = <1 10>; + }; + }; + + axi_gpio_0: gpio@88120000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88120000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_1: gpio@88130000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88130000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_2: gpio@88140000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + interrupt-controller; + reg = <0x0 0x88140000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x13>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_iic_main: i2c@88150000 { + clock-frequency = <100000000>; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <1 2>; + reg = <0x0 0x88150000 0x0 0x10000>; + }; + + axi_sysid_0: axi_sysid@42000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x0 0x88170000 0x0 0x1000>; + }; + + rx_dma: dma@88090000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88090000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <3 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma: dma@880f0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880F0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <4 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + axi_data_offload_rx: data_offload_rx@88020000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88020000 0x0 0x10000>; + }; + + axi_data_offload_tx: data_offload_tx@88050000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88050000 0x0 0x10000>; + }; + + axi_ad9084_adxcvr_rx: axi-adxcvr-rx@880b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880B0000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk", "rx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_adxcvr_tx: axi-adxcvr-tx@88110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88110000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk", "tx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@880a0000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x880A0000 0x0 0x1000>; + interrupt-parent = <&axi_intc_0>; + interrupts = <5 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx 1>, <<c6952 5>, <&axi_ad9084_adxcvr_rx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@88100000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x88100000 0x0 0x1000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <6 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx 1>, <<c6952 5>, <&axi_ad9084_adxcvr_tx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx 0 DEFRAMER_LINK_A0_TX>; + }; + + apollo_spi: spi@88030000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <7 0>; + num-cs = <1>; + reg = <0x0 0x88030000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + + // interrupt-names = "fft_done_A", "fft_done_B"; + // interrupt-parent = <&axi_gpio>; + // interrupts = <17 1 18 1>; + +#if HSCI_ENABLE + adi,axi-hsci-connected = <&axi_hsci>; + adi,hsci-auto-linkup-mode-en; + adi,hsci-disable-after-boot-en; +#endif + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + +#ifdef ASYNM_A_B_MODE + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>, + <&axi_ad9084_core_tx_b 0 DEFRAMER_LINK_B0_TX>; + + adi,side-b-use-seperate-tpl-en; +#else + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; +#endif + + reset-gpios = <&axi_gpio_2 0x31 0>; + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + //adi,standalone-enable; + }; + + }; + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@881b0000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0x0 0x881B0000 0x0 0x1000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@881d0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881D0000 0x0 0x1000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + +#if HSCI_ENABLE + hsci_clkgen: axi-clkgen@881F0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x881F0000 0x1000>; + #clock-cells = <0>; + clocks = <&mig_clkout1>, <&mig_clkout1>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@88200000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x88200000 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + adi,hsci-interface-speed-mhz = <800>; + }; +#endif + +#ifdef ASYNM_A_B_MODE + rx_dma_b: dma@88060000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88060000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <10 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma_b: dma@880c0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880C0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <11 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + + }; + + axi_ad9084_core_rx_b: axi-ad9084b-rx-b@881c0000 { + compatible = "adi,axi-adc-tpl-so-10.0.a"; + reg = <0x0 0x881C0000 0x0 0x10000>; + dmas = <&rx_dma_b 0>; + dma-names = "rx"; + clocks = <&trx0_ad9084 0>; /* FIXME */ + clock-names = "sampl_clk"; + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_core_tx_b: axi-ad9084-tx-b@881e0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881E0000 0x0 0x10000>; + dmas = <&tx_dma_b 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; /* FIXME */ + clock-names = "sampl_clk"; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx_b>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_rx_jesd_b: axi-jesd204-rx-b@88070000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x88070000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <12 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx_b 1>, <<c6952 5>, <&axi_ad9084_adxcvr_rx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_tx_jesd_b: axi-jesd204-tx-b@880d0000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x880D0000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <13 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx_b 1>, <<c6952 5>, <&axi_ad9084_adxcvr_tx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_adxcvr_rx_b: axi-adxcvr-rx-b@88080000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88080000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk_b", "rx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_adxcvr_tx_b: axi-adxcvr-tx-b@880e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880E0000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk_b", "tx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_data_offload_rx_b: data_offload_rx_b@88010000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88010000 0x0 0x10000>; + }; + + axi_data_offload_tx_b: data_offload_tx_b@88040000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88040000 0x0 0x10000>; + }; +#endif /* ASYNM_A_B_MODE */ + +}; \ No newline at end of file diff --git a/examples/adsy1100_gen.py b/examples/adsy1100_gen.py new file mode 100644 index 00000000..5fac29bf --- /dev/null +++ b/examples/adsy1100_gen.py @@ -0,0 +1,55 @@ +import adidt +import adijif +from pprint import pprint + + +vcxo = int(125e6) +cddc_dec = 4 +fddc_dec = 2 +converter_rate = int(20e9) + +sys = adijif.system("ad9084_rx", "ltc6952", "xilinx", vcxo, solver="CPLEX") + +sys.fpga.setup_by_dev_kit_name("adsy1100") +sys.converter.sample_clock = converter_rate / (cddc_dec * fddc_dec) +sys.converter.datapath.cddc_decimations = [cddc_dec] * 4 +sys.converter.datapath.fddc_decimations = [fddc_dec] * 8 +sys.converter.datapath.fddc_enabled = [True] * 8 + +sys.converter.clocking_option = "direct" +sys.add_pll_inline("adf4382", vcxo, sys.converter) +# sys.add_pll_sysref("adf4030", vcxo, sys.converter, sys.fpga) + + +sys.clock.minimize_feedback_dividers = False + +mode_rx = adijif.utils.get_jesd_mode_from_params( + sys.converter, M=4, L=8, S=1, Np=16, jesd_class="jesd204c" +) +# print(f"RX JESD Mode: {mode_rx}") +assert mode_rx +mode_rx = mode_rx[0]['mode'] + +sys.converter.set_quick_configuration_mode(mode_rx, "jesd204c") + + +# print(f"Lane rate: {sys.converter.bit_clock/1e9} Gbps") +# print(f"Needed Core clock: {sys.converter.bit_clock/66} MHz") + +sys.converter._check_clock_relations() + +cfg = sys.solve() + +pprint(cfg) + +############################################### + +som = adidt.adsy1100_vu11p() + +clock, fpga = som.map_clocks_to_board_layout(cfg) + +converter = {"device_profile_name": "profile.bin",} +pprint(clock) +pprint(fpga) + +som.gen_dt(clock=clock, fpga=fpga, converter=converter) \ No newline at end of file