diff --git a/docs/projects/ad469x_evb/ad4692_hdl_cnv_coraz7s.svg b/docs/projects/ad469x_evb/ad4692_hdl_cnv_coraz7s.svg new file mode 100644 index 00000000000..54c64c4779f --- /dev/null +++ b/docs/projects/ad469x_evb/ad4692_hdl_cnv_coraz7s.svg @@ -0,0 +1,2258 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + MEMORY INTERCONNECT + Cora Z7S + + + ARDUINO CONNECTOR + + + AD4692_DMA + 80MHz + + + + ARM (Zynq) + Zynq SoC + + + + + + MISO/SDI + SPI ENGINE FRAMEWORK + BUSY + CS + MOSI/SDO + SCLK + + + + + + AXIREGMAP + + INTER-CONNECT + + + EXECUTION + + OFFLOAD + + + + + AXI PULSEGEN + + CNV + + AXI CLKGEN + spi_clk = 160MHz + sys_clk = 100MHz + + + + + + + + + + + OR GATE + + EMIO_GPIO + + AND GATE + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 64b + + + 32b + trigger + + diff --git a/docs/projects/ad469x_evb/ad4692_hdl_pwm_coraz7s.svg b/docs/projects/ad469x_evb/ad4692_hdl_pwm_coraz7s.svg new file mode 100644 index 00000000000..74973c9d47f --- /dev/null +++ b/docs/projects/ad469x_evb/ad4692_hdl_pwm_coraz7s.svg @@ -0,0 +1,2200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + MEMORY INTERCONNECT + Cora Z7S + + + ARDUINO CONNECTOR + + + AD4692_DMA + 80MHz + + + + ARM (Zynq) + Zynq SoC + + + + + + MISO/SDI + SPI ENGINE FRAMEWORK + + CS + MOSI/SDO + SCLK + + + + + + AXIREGMAP + + INTER-CONNECT + + + EXECUTION + + OFFLOAD + + + + + AXI PULSEGEN + + AXI CLKGEN + spi_clk = 160MHz + sys_clk = 100MHz + + + + + + + + AND GATE + + s_axis_xfer_req + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 64b + + + 32b + trigger + + diff --git a/docs/projects/ad469x_evb/ad469x_hdl_coraz7s.svg b/docs/projects/ad469x_evb/ad469x_hdl_coraz7s.svg index f156eb3a485..1447f46beca 100644 --- a/docs/projects/ad469x_evb/ad469x_hdl_coraz7s.svg +++ b/docs/projects/ad469x_evb/ad469x_hdl_coraz7s.svg @@ -1,13 +1,13 @@ @@ -120,7 +120,7 @@ @@ -135,7 +135,7 @@ inkscape:stockid="TriangleInM"> @@ -151,7 +151,7 @@ inkscape:stockid="TriangleOutM"> @@ -167,7 +167,7 @@ inkscape:stockid="TriangleInM"> @@ -183,7 +183,7 @@ inkscape:stockid="TriangleOutM"> @@ -200,7 +200,7 @@ inkscape:connector-curvature="0" id="path16078" d="M 5.77,0 -2.88,5 V -5 Z" - style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" transform="scale(-0.8)" /> + + + + + + + + + + units="px" + visible="false" /> @@ -1094,12 +1140,12 @@ inkscape:groupmode="layer" inkscape:label="Layer 1"> + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.56852;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + style="display:inline;opacity:1;vector-effect:none;fill:none;fill-opacity:1;stroke:#3f4b55;stroke-width:2.03992;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:2.03992, 6.11976;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + style="display:inline;opacity:1;vector-effect:none;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.14474;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> ARDUINO CONNECTOR + style="display:inline;fill:none;fill-opacity:1;stroke:#3f4b55;stroke-width:2.1985;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:2.1985, 6.59549;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> 80MHz MISO/SDI SPI ENGINE FRAMEWORK BUSY CS MOSI/SDO SCLK AXIREGMAP INTER-CONNECT + y="113.49992" /> EXECUTION OFFLOAD CNV AXI CLKGEN spi_clk = 160MHz sys_clk = 100MHz AND GATE s_axis_xfer_req OR GATE - EMIO_GPIO + + AND GATE + + + 64b 32b trigger diff --git a/docs/projects/ad469x_evb/ad469x_hdl_zed.svg b/docs/projects/ad469x_evb/ad469x_hdl_zed.svg index d61b54da65e..70d58bb2c5b 100644 --- a/docs/projects/ad469x_evb/ad469x_hdl_zed.svg +++ b/docs/projects/ad469x_evb/ad469x_hdl_zed.svg @@ -1,13 +1,13 @@ @@ -120,7 +120,7 @@ @@ -135,7 +135,7 @@ inkscape:stockid="TriangleInM"> @@ -151,7 +151,7 @@ inkscape:stockid="TriangleOutM"> @@ -167,7 +167,7 @@ inkscape:stockid="TriangleInM"> @@ -183,7 +183,7 @@ inkscape:stockid="TriangleOutM"> @@ -200,7 +200,7 @@ inkscape:connector-curvature="0" id="path16078" d="M 5.77,0 -2.88,5 V -5 Z" - style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" transform="scale(-0.8)" /> + + + + + + + + + + units="px" + visible="false" /> @@ -1094,12 +1140,12 @@ inkscape:groupmode="layer" inkscape:label="Layer 1"> + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.56852;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> Zedboard + style="display:inline;opacity:1;vector-effect:none;fill:none;fill-opacity:1;stroke:#3f4b55;stroke-width:2.03992;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:2.03992, 6.11976;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + style="display:inline;opacity:1;vector-effect:none;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.14474;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> FMC CONNECTOR + style="display:inline;fill:none;fill-opacity:1;stroke:#3f4b55;stroke-width:2.1985;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:2.1985, 6.59549;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> 80MHz + style="opacity:1;fill:#f9f9f9;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.74916;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:normal" /> @@ -1432,86 +1478,86 @@ sodipodi:nodetypes="cc" inkscape:connector-curvature="0" id="path1206-1-0" - d="m 528.80556,98.139362 h 145" + d="M 528.80556,78.303623 H 721.31325" style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:1.99314;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3);shape-rendering:crispEdges;enable-background:new" /> MISO/SDI SPI ENGINE FRAMEWORK BUSY CS MOSI/SDO SCLK + style="display:inline;opacity:1;fill:#e5e5e5;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.74916;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:normal;shape-rendering:crispEdges;enable-background:new" /> + style="display:inline;opacity:1;fill:#e5e5e5;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.74916;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:normal;shape-rendering:crispEdges;enable-background:new" /> AXIREGMAP + style="display:inline;fill:#e5e5e5;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.74916;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:normal;shape-rendering:crispEdges;enable-background:new" /> INTER-CONNECT + y="113.49992" /> EXECUTION OFFLOAD CNV + style="display:inline;opacity:1;fill:#e5e5e5;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.74916;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;paint-order:normal;shape-rendering:crispEdges;enable-background:new" /> AXI CLKGEN spi_clk = 160MHz sys_clk = 100MHz + d="M 210.67332,210.66463 V 188.32129" + style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:2.28129;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-9-9-6-4-20-7);shape-rendering:crispEdges;enable-background:new" /> + d="m 554.80471,209.80595 -344.20226,-2.6e-4 -1.07686,-0.003" + style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:2.23406;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + d="M 727.53846,209.80595 H 565.70449 l -6.13966,0" + style="display:inline;opacity:1;fill:none;stroke:#000000;stroke-width:1.86108;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216-0-3-9-2);shape-rendering:crispEdges;enable-background:new" /> + d="m 53.098922,376.55651 v 53.15007 h 89.925268" + style="fill:none;stroke:#000000;stroke-width:1.67392;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1216)" /> AND GATE s_axis_xfer_req OR GATE - EMIO_GPIO + + AND GATE + + + + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.8;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.67501;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:0.673913" /> + style="opacity:1;fill:#000000;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.67501;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:0.673913" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:0.5506;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> @@ -1920,9 +1996,9 @@ inkscape:connector-curvature="0" id="path8426" d="M 406.04958,433.33004 H 404.6091" - style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.06700003;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> @@ -1930,9 +2006,9 @@ inkscape:connector-curvature="0" id="path8430" d="M 406.04958,437.86003 H 404.6091" - style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.06700003;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> @@ -1940,9 +2016,9 @@ inkscape:connector-curvature="0" id="path8434" d="M 406.04958,442.34471 H 404.6091" - style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.06700003;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> @@ -1950,14 +2026,14 @@ inkscape:connector-curvature="0" id="path8438" d="M 406.04958,446.82944 H 404.6091" - style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.06700003;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.067;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> @@ -1967,14 +2043,14 @@ id="g8892" style="display:inline;shape-rendering:crispEdges;enable-background:new"> @@ -1984,17 +2060,17 @@ style="fill:#ffffff;fill-opacity:1;stroke:#ffffff;stroke-opacity:1"> + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:1.2;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.973;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.308598;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.308598;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.308598;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:0.308598;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> + style="opacity:1;fill:#ffffff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.41103;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> 64b 32b trigger diff --git a/docs/projects/ad469x_evb/index.rst b/docs/projects/ad469x_evb/index.rst index 93542777020..3ecd6d224f3 100644 --- a/docs/projects/ad469x_evb/index.rst +++ b/docs/projects/ad469x_evb/index.rst @@ -7,25 +7,28 @@ Overview ------------------------------------------------------------------------------- The AD469X HDL reference design provides all the interfaces that are -necessary to interact with the devices on the :adi:`EVAL-AD4696` board. +necessary to interact with the devices on the :adi:`EVAL-AD4696` and +:adi:`EVAL-AD4692-ARDZ` boards. The design has a SPI Engine instance to control and acquire data from the -:adi:`AD4696` 16-bit precisions ADC, providing support to capture continuous -samples at maximum sampling rate. Currently the design supports the Zedboard. +:adi:`AD4696`/:adi:`AD4692` 16-bit precision ADCs, providing support to capture +continuous samples at maximum sampling rate. The ``PWM_OFFLOAD`` parameter +allows selecting the appropriate offload trigger and CNV gating scheme for +each device. Supported boards ------------------------------------------------------------------------------- - -- EVAL-AD4692 +- :adi:`EVAL-AD4692-ARDZ` - :adi:`EVAL-AD4696` + Supported devices ------------------------------------------------------------------------------- -- AD4691 -- AD4692 -- AD4693 -- AD4694 +- :adi:`AD4691` +- :adi:`AD4692` +- :adi:`AD4693` +- :adi:`AD4694` - :adi:`AD4695` - :adi:`AD4696` - :adi:`AD4697` @@ -44,8 +47,8 @@ Block design The reference design uses the standard :ref:`SPI Engine Framework ` to interface the :adi:`AD4696` ADC in single SDO Mode. The :ref:`SPI Engine Offload module `, which can be used to -capture continuous data stream at maximum data rate, is triggered by the BUSY -signal of the device. +capture continuous data stream at maximum data rate, is triggered depending on +the ``PWM_OFFLOAD`` parameter (see `Configuration modes`_). CNV signal gating ------------------------------------------------------------------------------- @@ -54,24 +57,38 @@ The :git-hdl:`AXI PWM GEN ` IP core is used to drive CNV when the SPI Engine is operating in Offload mode along with logic gates and a few extra signals to ensure proper control of the signal. -The AND gate has the DMA ``s_axis_xfer_req`` signal and the PWM signal as inputs. -Since the PWM is free running, this gate is necessary to prevent the sequencer -on the ADC from getting out of sync. When the DMA is unable to receive more -data, the ``s_axis_xfer_req`` signal is driven low, blocking the PWM signal. +In the default mode (``PWM_OFFLOAD=0``), the AND gate has the DMA +``s_axis_xfer_req`` signal and the PWM signal as inputs. Since the PWM is free +running, this gate is necessary to prevent the sequencer on the ADC from getting +out of sync. When the DMA is unable to receive more data, the +``s_axis_xfer_req`` signal is driven low, blocking the PWM signal. + +In register mode (``PWM_OFFLOAD=1``), the AND gate has the PWM signal and the +BUSY signal as inputs, gating the CNV based on the ADC busy state. + +In both modes 0 and 1, an OR gate allows the software to generate CNV pulses +using a GPIO signal. This is needed to exit conversion mode on the device, as +one extra pulse on the CNV pin is required before sending the exit command. +This also allows the system to read single samples using the SPI Engine FIFO +mode. -Also, to exit conversion mode on the device, one extra pulse on the CNV pin is -needed before sending the exit command, otherwise this command is ignored by the -ADC. This feature also allows the system to read single samples using the SPI -Engine FIFO mode. To achieve this, an OR gate is used to allow the software to -generate CNV pulses using a GPIO signal. +In manual mode (``PWM_OFFLOAD=2``), no CNV gating is used. Instead, the SPI +Engine offload trigger itself is gated by an AND of the PWM and DMA +``s_axis_xfer_req`` signals. Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The data path and clock domains are depicted in the below diagram: +Default mode (PWM_OFFLOAD=0) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The data path and clock domains are depicted in the below diagrams. +These diagrams correspond to the default configuration (``PWM_OFFLOAD=0``), +where the BUSY falling edge triggers the SPI Engine offload and the CNV signal +is gated by DMA ``s_axis_xfer_req`` AND PWM, with a GPIO OR override. Zedboard -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" .. image:: ad469x_hdl_zed.svg :width: 800 @@ -79,7 +96,7 @@ Zedboard :alt: AD469X_EVB/Zedboard block diagram Cora Z7S -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" .. image:: ad469x_hdl_coraz7s.svg :width: 800 @@ -87,13 +104,40 @@ Cora Z7S :alt: AD469X_EVB/Cora block diagram DE10-Nano -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" .. image:: ad469x_hdl_de10nano.svg :width: 800 :align: center :alt: AD469X_EVB/DE10-Nano block diagram +AD4692 register mode (PWM_OFFLOAD=1) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In register mode, the SPI Engine offload is triggered by the BUSY falling edge, +same as the default mode. The difference is in the CNV gating: instead of +gating with DMA ``s_axis_xfer_req``, the CNV signal is gated by an AND of the +PWM signal and the BUSY signal. An OR gate with a GPIO signal is still present +to allow software-generated CNV pulses. + +.. image:: ad4692_hdl_cnv_coraz7s.svg + :width: 800 + :align: center + :alt: AD4692/Cora Z7S register mode block diagram + +AD4692 manual mode (PWM_OFFLOAD=2) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +In manual mode, the SPI Engine offload trigger is gated by an AND of the PWM +signal and the DMA ``s_axis_xfer_req`` signal. This ensures that SPI +transactions only occur when both the PWM fires and the DMA is ready to receive +data. No CNV gating logic is instantiated. + +.. image:: ad4692_hdl_pwm_coraz7s.svg + :width: 800 + :align: center + :alt: AD4692/Cora Z7S manual mode block diagram + Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -109,13 +153,27 @@ In case we link CNV signal to PWM: .. shell:: bash - $make SPI_4WIRE=0 + $make SPI_4WIRE=0 PWM_OFFLOAD=0 In case we link CNV signal to SPI_CS: .. shell:: bash - $make SPI_4WIRE=1 + $make SPI_4WIRE=1 PWM_OFFLOAD=0 + +The ``PWM_OFFLOAD`` configuration parameter defines the SPI +Engine offload trigger source and CNV gating scheme. By default, it is set to 0. + +- ``PWM_OFFLOAD=0``: BUSY falling edge triggers offload, CNV gated by + DMA xfer_req AND PWM (original ad469x). +- ``PWM_OFFLOAD=1``: BUSY falling edge triggers offload, CNV gated by + PWM AND BUSY (ad4692 register mode). +- ``PWM_OFFLOAD=2``: PWM AND DMA xfer_req gates offload trigger, no CNV + gating (ad4692 manual mode). + +.. shell:: bash + + $make SPI_4WIRE=0 PWM_OFFLOAD=1 CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -286,18 +344,25 @@ the HDL repository, and then build the project as follows: .. shell:: $cd hdl/projects/ad469x_evb/zed - $make SPI_4WIRE=0 + $make SPI_4WIRE=0 PWM_OFFLOAD=0 + +or, for the AD4692 in register mode on Cora Z7S: + +.. shell:: + + $cd hdl/projects/ad469x_evb/coraz7s + $make SPI_4WIRE=0 PWM_OFFLOAD=1 The result of the build, if parameters were used, will be in a folder named by the configuration used: if the following command was run -``SPI_4WIRE=0`` +``SPI_4WIRE=0 PWM_OFFLOAD=1`` then the folder name will be: -``SPI4WIRE0`` +``SPI4WIRE0_PWMOFFLOAD1`` A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -309,10 +374,13 @@ Hardware related - Product datasheets: + - :adi:`AD4691`/:adi:`AD4692` + - :adi:`AD4693`/:adi:`AD4694` - :adi:`AD4695`/:adi:`AD4696` - :adi:`AD4697`/:adi:`AD4698` - `UG-1882, EVAL-AD4694FMCZ User Guide `__ +- `UG - EVAL-AD4692ARDZ User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/projects/ad469x_evb/common/ad469x_bd.tcl b/projects/ad469x_evb/common/ad469x_bd.tcl index 50deeaa7cd4..e8283238104 100644 --- a/projects/ad469x_evb/common/ad469x_bd.tcl +++ b/projects/ad469x_evb/common/ad469x_bd.tcl @@ -3,10 +3,16 @@ ### SPDX short identifier: ADIBSD ############################################################################### -# system level parameter +# system level parameters -set SPI_4WIRE $ad_project_params(SPI_4WIRE) +set SPI_4WIRE $ad_project_params(SPI_4WIRE) +set PWM_OFFLOAD $ad_project_params(PWM_OFFLOAD) puts "build parameter: SPI_4WIRE: $SPI_4WIRE" +puts "build parameter: PWM_OFFLOAD: $PWM_OFFLOAD" + +if {$SPI_4WIRE == 1 && $PWM_OFFLOAD != 0} { + error "ERROR: SPI_4WIRE=1 is only valid with PWM_OFFLOAD=0." +} create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 ad469x_spi @@ -46,20 +52,24 @@ ad_connect spi_clk ad469x_trigger_gen/ext_clk ad_connect $sys_cpu_clk ad469x_trigger_gen/s_axi_aclk ad_connect sys_cpu_resetn ad469x_trigger_gen/s_axi_aresetn -# trigger to BUSY's negative edge +# SPI Engine offload trigger configuration + +if {$PWM_OFFLOAD == 0 || $PWM_OFFLOAD == 1} { + + create_bd_cell -type module -reference sync_bits busy_sync + create_bd_cell -type module -reference ad_edge_detect busy_capture + set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture] -create_bd_cell -type module -reference sync_bits busy_sync -create_bd_cell -type module -reference ad_edge_detect busy_capture -set_property -dict [list CONFIG.EDGE 1] [get_bd_cells busy_capture] + ad_connect spi_clk busy_capture/clk + ad_connect busy_capture/rst GND -ad_connect spi_clk busy_capture/clk -ad_connect busy_capture/rst GND + ad_connect busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn + ad_connect spi_clk busy_sync/out_clk + ad_connect busy_sync/in_bits ad469x_spi_busy + ad_connect busy_sync/out_bits busy_capture/signal_in + ad_connect busy_capture/signal_out $hier_spi_engine/trigger -ad_connect busy_sync/out_resetn $hier_spi_engine/${hier_spi_engine}_axi_regmap/spi_resetn -ad_connect spi_clk busy_sync/out_clk -ad_connect busy_sync/in_bits ad469x_spi_busy -ad_connect busy_sync/out_bits busy_capture/signal_in -ad_connect busy_capture/signal_out $hier_spi_engine/trigger +} # dma to receive data stream @@ -84,20 +94,68 @@ ad_connect spi_clk $hier_spi_engine/spi_clk ad_connect $hier_spi_engine/m_spi ad469x_spi ad_connect axi_ad469x_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE -ad_ip_instance ilvector_logic cnv_gate -ad_ip_parameter cnv_gate CONFIG.C_SIZE 1 -ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and} +# PWM_OFFLOAD 2 (manual mode): trigger = PWM & DMA_xfer_req, no CNV gating + +if {$PWM_OFFLOAD == 2} { + ad_ip_instance ilvector_logic trigger_gate + ad_ip_parameter trigger_gate CONFIG.C_SIZE 1 + ad_ip_parameter trigger_gate CONFIG.C_OPERATION {and} + + ad_connect trigger_gate/Op1 ad469x_trigger_gen/pwm_0 + ad_connect trigger_gate/Op2 axi_ad469x_dma/s_axis_xfer_req + ad_connect $hier_spi_engine/trigger trigger_gate/Res +} + +# CNV gating configuration +# Note: CNV gating only applies when SPI_4WIRE==0 (CNV driven by PWM). +# When SPI_4WIRE=1, system_top.v routes SPI_CS to the CNV pin instead. + +if {$PWM_OFFLOAD == 0} { + + # CNV = ((DMA_xfer_req & PWM) & BUSY) | gpio_cnv + + ad_ip_instance ilvector_logic cnv_gate + ad_ip_parameter cnv_gate CONFIG.C_SIZE 1 + ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and} + + ad_ip_instance ilvector_logic cnv_gate_busy + ad_ip_parameter cnv_gate_busy CONFIG.C_SIZE 1 + ad_ip_parameter cnv_gate_busy CONFIG.C_OPERATION {and} + + ad_ip_instance ilvector_logic cnv_gate_gpio + ad_ip_parameter cnv_gate_gpio CONFIG.C_SIZE 1 + ad_ip_parameter cnv_gate_gpio CONFIG.C_OPERATION {or} + + ad_connect cnv_gate/Op1 axi_ad469x_dma/s_axis_xfer_req + ad_connect cnv_gate/Op2 ad469x_trigger_gen/pwm_0 + + ad_connect cnv_gate_busy/Op1 cnv_gate/Res + ad_connect cnv_gate_busy/Op2 ad469x_spi_busy + + ad_connect cnv_gate_gpio/Op1 cnv_gate_busy/Res + ad_connect cnv_gate_gpio/Op2 gpio_cnv + ad_connect cnv_gate_gpio/Res ad469x_spi_cnv + +} elseif {$PWM_OFFLOAD == 1} { + + # PWM_OFFLOAD 1 (register mode): CNV = (PWM & BUSY) | gpio_cnv + + ad_ip_instance ilvector_logic cnv_gate_busy + ad_ip_parameter cnv_gate_busy CONFIG.C_SIZE 1 + ad_ip_parameter cnv_gate_busy CONFIG.C_OPERATION {and} + + ad_ip_instance ilvector_logic cnv_gate_gpio + ad_ip_parameter cnv_gate_gpio CONFIG.C_SIZE 1 + ad_ip_parameter cnv_gate_gpio CONFIG.C_OPERATION {or} -ad_ip_instance ilvector_logic cnv_gate_gpio -ad_ip_parameter cnv_gate_gpio CONFIG.C_SIZE 1 -ad_ip_parameter cnv_gate_gpio CONFIG.C_OPERATION {or} + ad_connect cnv_gate_busy/Op1 ad469x_trigger_gen/pwm_0 + ad_connect cnv_gate_busy/Op2 ad469x_spi_busy -ad_connect cnv_gate/Op1 axi_ad469x_dma/s_axis_xfer_req -ad_connect cnv_gate/Op2 ad469x_trigger_gen/pwm_0 + ad_connect cnv_gate_gpio/Op1 cnv_gate_busy/Res + ad_connect cnv_gate_gpio/Op2 gpio_cnv + ad_connect cnv_gate_gpio/Res ad469x_spi_cnv -ad_connect cnv_gate_gpio/Op1 cnv_gate/Res -ad_connect cnv_gate_gpio/Op2 gpio_cnv -ad_connect cnv_gate_gpio/Res ad469x_spi_cnv +} ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap ad_cpu_interconnect 0x44a30000 axi_ad469x_dma diff --git a/projects/ad469x_evb/coraz7s/README.md b/projects/ad469x_evb/coraz7s/README.md index b2ca6384126..4f3323ff609 100644 --- a/projects/ad469x_evb/coraz7s/README.md +++ b/projects/ad469x_evb/coraz7s/README.md @@ -18,14 +18,36 @@ The overwritable parameter from the environment: - SPI_4WIRE - Defines if CNV signal is linked to PWM or to SPI_CS - 0 - CNV signal is linked to PWM - 1 - CNV signal is linked to SPI_CS +- PWM_OFFLOAD - Defines the SPI Engine offload trigger and CNV gating + - 0 - BUSY edge trigger, DMA+PWM+BUSY gated CNV (ad469x) + - 1 - BUSY edge trigger, PWM+BUSY gated CNV (ad4692 register) + - 2 - PWM+DMA gated trigger, no CNV gating (ad4692 manual) ### Example configurations -#### Default configuration +#### Default configuration: ad469x, BUSY edge trigger, DMA+PWM+BUSY gated CNV This specific command is equivalent to running `make` only: ``` cd projects/ad469x_evb/coraz7s -make SPI_4WIRE=0 +make SPI_4WIRE=0 PWM_OFFLOAD=0 +``` + +#### ad4692 register mode: BUSY edge trigger, PWM+BUSY gated CNV + +``` +make SPI_4WIRE=0 PWM_OFFLOAD=1 +``` + +#### ad4692 manual mode: PWM+DMA gated trigger, no CNV gating + +``` +make SPI_4WIRE=0 PWM_OFFLOAD=2 +``` + +#### 4-wire SPI mode: CNV driven by SPI_CS + +``` +make SPI_4WIRE=1 PWM_OFFLOAD=0 ``` \ No newline at end of file diff --git a/projects/ad469x_evb/coraz7s/system_bd.tcl b/projects/ad469x_evb/coraz7s/system_bd.tcl index aefaa7ad41b..b7cf0f6884c 100644 --- a/projects/ad469x_evb/coraz7s/system_bd.tcl +++ b/projects/ad469x_evb/coraz7s/system_bd.tcl @@ -19,6 +19,7 @@ ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 -set sys_cstring "SPI_4WIRE=$ad_project_params(SPI_4WIRE)" +set sys_cstring "SPI_4WIRE=$ad_project_params(SPI_4WIRE)\ + PWM_OFFLOAD=$ad_project_params(PWM_OFFLOAD)" sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad469x_evb/coraz7s/system_constr.xdc b/projects/ad469x_evb/coraz7s/system_constr.xdc index ae5d1d6c00d..d75b07fa402 100644 --- a/projects/ad469x_evb/coraz7s/system_constr.xdc +++ b/projects/ad469x_evb/coraz7s/system_constr.xdc @@ -6,8 +6,8 @@ # ad4696_ardz SPI interface set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_sclk]; ## CK_IO13 -set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_sdo]; ## CK_IO12 -set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_sdi]; ## CK_IO11 +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_sdi]; ## CK_IO12 +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_sdo]; ## CK_IO11 set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad469x_spi_cs]; ## CK_IO10 set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ad469x_busy_alt_gp0]; ## CK_IO09 diff --git a/projects/ad469x_evb/coraz7s/system_project.tcl b/projects/ad469x_evb/coraz7s/system_project.tcl index ba60d811f2a..3d996e569f1 100644 --- a/projects/ad469x_evb/coraz7s/system_project.tcl +++ b/projects/ad469x_evb/coraz7s/system_project.tcl @@ -10,9 +10,13 @@ source ../../scripts/adi_board.tcl # Parameter description # SPI_4WIRE - For 0 CNV is linked to PWM. For 1 CNV is linked to SPI_CS +# PWM_OFFLOAD - 0: BUSY edge trigger, DMA+PWM+BUSY gated CNV (ad469x) +# 1: BUSY edge trigger, PWM+BUSY gated CNV (ad4692 register) +# 2: PWM+DMA gated trigger, no CNV gating (ad4692 manual) adi_project ad469x_evb_coraz7s 0 [list \ - SPI_4WIRE [get_env_param SPI_4WIRE 0]] + SPI_4WIRE [get_env_param SPI_4WIRE 0] \ + PWM_OFFLOAD [get_env_param PWM_OFFLOAD 0]] adi_project_files ad469x_evb_coraz7s [list \ "../../../library/common/ad_iobuf.v" \ diff --git a/projects/ad469x_evb/zed/README.md b/projects/ad469x_evb/zed/README.md index e395e460665..346faa18f18 100644 --- a/projects/ad469x_evb/zed/README.md +++ b/projects/ad469x_evb/zed/README.md @@ -18,16 +18,38 @@ The overwritable parameter from the environment: - SPI_4WIRE - Defines if CNV signal is linked to PWM or to SPI_CS - 0 - CNV signal is linked to PWM - 1 - CNV signal is linked to SPI_CS +- PWM_OFFLOAD - Defines the SPI Engine offload trigger and CNV gating + - 0 - BUSY edge trigger, DMA+PWM+BUSY gated CNV (ad469x) + - 1 - BUSY edge trigger, PWM+BUSY gated CNV (ad4692 register) + - 2 - PWM+DMA gated trigger, no CNV gating (ad4692 manual) ### Example configurations -#### Default configuration +#### Default configuration: ad469x, BUSY edge trigger, DMA+PWM+BUSY gated CNV This specific command is equivalent to running `make` only: ``` cd projects/ad469x_evb/zed -make SPI_4WIRE=0 +make SPI_4WIRE=0 PWM_OFFLOAD=0 ``` -Corresponding device tree: [zynq-zed-adv7511-ad4696.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4696.dts) \ No newline at end of file +Corresponding device tree: [zynq-zed-adv7511-ad4696.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4696.dts) + +#### ad4692 register mode: BUSY edge trigger, PWM+BUSY gated CNV + +``` +make SPI_4WIRE=0 PWM_OFFLOAD=1 +``` + +#### ad4692 manual mode: PWM+DMA gated trigger, no CNV gating + +``` +make SPI_4WIRE=0 PWM_OFFLOAD=2 +``` + +#### 4-wire SPI mode: CNV driven by SPI_CS + +``` +make SPI_4WIRE=1 PWM_OFFLOAD=0 +``` \ No newline at end of file diff --git a/projects/ad469x_evb/zed/system_bd.tcl b/projects/ad469x_evb/zed/system_bd.tcl index 642ee45359f..daf16b545fc 100644 --- a/projects/ad469x_evb/zed/system_bd.tcl +++ b/projects/ad469x_evb/zed/system_bd.tcl @@ -18,6 +18,7 @@ ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 -set sys_cstring "SPI_4WIRE=$ad_project_params(SPI_4WIRE)" +set sys_cstring "SPI_4WIRE=$ad_project_params(SPI_4WIRE)\ + PWM_OFFLOAD=$ad_project_params(PWM_OFFLOAD)" sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad469x_evb/zed/system_project.tcl b/projects/ad469x_evb/zed/system_project.tcl index 21fb246badd..52b74aed164 100644 --- a/projects/ad469x_evb/zed/system_project.tcl +++ b/projects/ad469x_evb/zed/system_project.tcl @@ -12,7 +12,8 @@ source ../../scripts/adi_board.tcl # SPI_4WIRE - For 0 CNV is linked to PWM. For 1 CNV is linked to SPI_CS adi_project ad469x_evb_zed 0 [list \ - SPI_4WIRE [get_env_param SPI_4WIRE 0]] + SPI_4WIRE [get_env_param SPI_4WIRE 0] \ + PWM_OFFLOAD [get_env_param PWM_OFFLOAD 0]] adi_project_files ad469x_evb_zed [list \ "../../../library/common/ad_iobuf.v" \