From e3b958f6a9c6bbd278897d758dafd42939a2b44d Mon Sep 17 00:00:00 2001 From: Filip Gherman Date: Fri, 13 Mar 2026 13:14:34 +0200 Subject: [PATCH] projects: ad_xband16_ebz: Initial commit Adds AD_XBAND16_EBZ (QUAD-APOLLO) base design for VCU118 Signed-off-by: Filip Gherman --- .../common/ad_xband16_ebz_bd.tcl | 585 +++++++++++++++++ .../ad_xband16_ebz/common/hsci_phy_top.sv | 236 +++++++ projects/ad_xband16_ebz/vcu118/Makefile | 49 ++ projects/ad_xband16_ebz/vcu118/system_bd.tcl | 195 ++++++ .../ad_xband16_ebz/vcu118/system_constr.xdc | 273 ++++++++ .../ad_xband16_ebz/vcu118/system_project.tcl | 110 ++++ .../ad_xband16_ebz/vcu118/system_top_master.v | 591 +++++++++++++++++ .../ad_xband16_ebz/vcu118/system_top_slave.v | 593 ++++++++++++++++++ .../ad_xband16_ebz/vcu118/timing_constr.xdc | 73 +++ 9 files changed, 2705 insertions(+) create mode 100644 projects/ad_xband16_ebz/common/ad_xband16_ebz_bd.tcl create mode 100755 projects/ad_xband16_ebz/common/hsci_phy_top.sv create mode 100644 projects/ad_xband16_ebz/vcu118/Makefile create mode 100644 projects/ad_xband16_ebz/vcu118/system_bd.tcl create mode 100644 projects/ad_xband16_ebz/vcu118/system_constr.xdc create mode 100644 projects/ad_xband16_ebz/vcu118/system_project.tcl create mode 100644 projects/ad_xband16_ebz/vcu118/system_top_master.v create mode 100644 projects/ad_xband16_ebz/vcu118/system_top_slave.v create mode 100644 projects/ad_xband16_ebz/vcu118/timing_constr.xdc diff --git a/projects/ad_xband16_ebz/common/ad_xband16_ebz_bd.tcl b/projects/ad_xband16_ebz/common/ad_xband16_ebz_bd.tcl new file mode 100644 index 0000000000..1bd04b0d7a --- /dev/null +++ b/projects/ad_xband16_ebz/common/ad_xband16_ebz_bd.tcl @@ -0,0 +1,585 @@ +############################################################################### +## Copyright (C) 2026 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl +source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl + +# Common parameter for TX and RX +set JESD_MODE $ad_project_params(JESD_MODE) +set RX_LANE_RATE $ad_project_params(RX_LANE_RATE) +set TX_LANE_RATE $ad_project_params(TX_LANE_RATE) + +set HSCI_BYPASS [ expr { [info exists ad_project_params(HSCI_BYPASS)] \ + ? $ad_project_params(HSCI_BYPASS) : 0 } ] +set TDD_SUPPORT [ expr { [info exists ad_project_params(TDD_SUPPORT)] \ + ? $ad_project_params(TDD_SUPPORT) : 0 } ] +set SHARED_DEVCLK [ expr { [info exists ad_project_params(SHARED_DEVCLK)] \ + ? $ad_project_params(SHARED_DEVCLK) : 0 } ] +set DO_HAS_BYPASS [ expr { [info exists ad_project_params(DO_HAS_BYPASS)] \ + ? $ad_project_params(DO_HAS_BYPASS) : 1 } ] +set MCS_MODE [ expr { [info exists ad_project_params(MCS_MODE)] \ + ? $ad_project_params(MCS_MODE) : "MASTER" } ] + +if {$TDD_SUPPORT && !$SHARED_DEVCLK} { + error "ERROR: Cannot enable TDD support without shared deviceclocks!" +} + +set adc_do_mem_type [ expr { [info exists ad_project_params(ADC_DO_MEM_TYPE)] \ + ? $ad_project_params(ADC_DO_MEM_TYPE) : 0 } ] +set dac_do_mem_type [ expr { [info exists ad_project_params(DAC_DO_MEM_TYPE)] \ + ? $ad_project_params(DAC_DO_MEM_TYPE) : 0 } ] + +set do_axi_data_width [ expr { [info exists do_axi_data_width] \ + ? $do_axi_data_width : 256 } ] + +if {$JESD_MODE == "8B10B"} { + set DATAPATH_WIDTH 4 + set ENCODER_SEL 1 +} else { + set DATAPATH_WIDTH 8 + set ENCODER_SEL 2 +} + +# These are max values specific to the board +set MAX_RX_LANES_PER_LINK 4 +set MAX_TX_LANES_PER_LINK 4 +set MAX_RX_LINKS 4 +set MAX_TX_LINKS 4 +set MAX_RX_LANES [expr $MAX_RX_LANES_PER_LINK*$MAX_RX_LINKS] +set MAX_TX_LANES [expr $MAX_TX_LANES_PER_LINK*$MAX_TX_LINKS] + +# RX parameters +set RX_NUM_LINKS $ad_project_params(RX_NUM_LINKS) + +# RX JESD parameter per link +set RX_JESD_M $ad_project_params(RX_JESD_M) +set RX_JESD_L $ad_project_params(RX_JESD_L) +set RX_JESD_S $ad_project_params(RX_JESD_S) +set RX_JESD_NP $ad_project_params(RX_JESD_NP) + +set RX_NUM_OF_LANES [expr $RX_JESD_L * $RX_NUM_LINKS] +set RX_NUM_OF_CONVERTERS [expr $RX_JESD_M * $RX_NUM_LINKS] +set RX_SAMPLES_PER_FRAME $RX_JESD_S +set RX_SAMPLE_WIDTH $RX_JESD_NP + +set RX_DMA_SAMPLE_WIDTH $RX_JESD_NP +if {$RX_DMA_SAMPLE_WIDTH == 12} { + set RX_DMA_SAMPLE_WIDTH 16 +} + +set RX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $RX_JESD_L $RX_JESD_M $RX_JESD_S $RX_JESD_NP] + +set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 8 * $RX_DATAPATH_WIDTH / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)] + +# TX parameters +set TX_NUM_LINKS $ad_project_params(TX_NUM_LINKS) + +# TX JESD parameter per link +set TX_JESD_M $ad_project_params(TX_JESD_M) +set TX_JESD_L $ad_project_params(TX_JESD_L) +set TX_JESD_S $ad_project_params(TX_JESD_S) +set TX_JESD_NP $ad_project_params(TX_JESD_NP) + +set TX_NUM_OF_LANES [expr $TX_JESD_L * $TX_NUM_LINKS] +set TX_NUM_OF_CONVERTERS [expr $TX_JESD_M * $TX_NUM_LINKS] +set TX_SAMPLES_PER_FRAME $TX_JESD_S +set TX_SAMPLE_WIDTH $TX_JESD_NP + +set TX_DMA_SAMPLE_WIDTH $TX_JESD_NP +if {$TX_DMA_SAMPLE_WIDTH == 12} { + set TX_DMA_SAMPLE_WIDTH 16 +} + +set TX_DATAPATH_WIDTH [adi_jesd204_calc_tpl_width $DATAPATH_WIDTH $TX_JESD_L $TX_JESD_M $TX_JESD_S $TX_JESD_NP] + +set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 8 * $TX_DATAPATH_WIDTH / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)] + +set adc_data_offload_name apollo_rx_data_offload +set adc_data_width [expr $RX_DMA_SAMPLE_WIDTH*$RX_NUM_OF_CONVERTERS*$RX_SAMPLES_PER_CHANNEL] +set adc_dma_data_width $adc_data_width +set adc_fifo_address_width [expr int(ceil(log(($adc_fifo_samples_per_converter*$RX_NUM_OF_CONVERTERS) / ($adc_data_width/$RX_DMA_SAMPLE_WIDTH))/log(2)))] + +set dac_data_offload_name apollo_tx_data_offload +set dac_data_width [expr $TX_DMA_SAMPLE_WIDTH*$TX_NUM_OF_CONVERTERS*$TX_SAMPLES_PER_CHANNEL] +set dac_dma_data_width $dac_data_width +set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$TX_NUM_OF_CONVERTERS) / ($dac_data_width/$TX_DMA_SAMPLE_WIDTH))/log(2)))] + +create_bd_port -dir I rx_device_clk +create_bd_port -dir I tx_device_clk + +##AXI_ADF4030 IP +create_bd_port -dir IO adf4030_bsync_p +create_bd_port -dir IO adf4030_bsync_n +create_bd_port -dir I adf4030_clk +create_bd_port -dir I adf4030_trigger +create_bd_port -dir O adf4030_sysref +create_bd_port -dir O -from 5 -to 0 adf4030_trig_channel +create_bd_port -dir O adf4030_trig_request_out + +ad_ip_instance axi_adf4030 axi_adf4030_0 +ad_ip_parameter axi_adf4030_0 CONFIG.CHANNEL_COUNT 5 +ad_ip_parameter axi_adf4030_0 CONFIG.TRIGGER_STRETCH [expr {$MCS_MODE == "MASTER" ? 1 : 0}] + +ad_connect axi_adf4030_0/bsync_p adf4030_bsync_p +ad_connect axi_adf4030_0/bsync_n adf4030_bsync_n +ad_connect axi_adf4030_0/device_clk adf4030_clk +ad_connect axi_adf4030_0/trigger adf4030_trigger +ad_connect axi_adf4030_0/sysref adf4030_sysref +ad_connect axi_adf4030_0/trig_channel adf4030_trig_channel +ad_connect axi_adf4030_0/trig_request_out adf4030_trig_request_out + +##AXI_HSCI IP +if {!$HSCI_BYPASS} { + for {set i 0} {$i < 2} {incr i} { + create_bd_port -dir O hsci_pll_reset_$i + create_bd_port -dir I hsci_pclk_$i + create_bd_port -dir I hsci_rst_seq_done_$i + create_bd_port -dir I hsci_pll_locked_$i + } + + for {set i 0} {$i < 4} {incr i} { + set j [expr $i > 1 ? 1 : 0] + + create_bd_port -dir O -from 7 -to 0 hsci_menc_clk_$i + create_bd_port -dir O -from 7 -to 0 hsci_data_out_$i + create_bd_port -dir I -from 7 -to 0 hsci_data_in_$i + + create_bd_port -dir I hsci_vtc_rdy_bsc_tx_$i + create_bd_port -dir I hsci_dly_rdy_bsc_tx_$i + create_bd_port -dir I hsci_vtc_rdy_bsc_rx_$i + create_bd_port -dir I hsci_dly_rdy_bsc_rx_$i + + ad_ip_instance axi_hsci axi_hsci_$i + ad_connect axi_hsci_${i}/hsci_miso_data hsci_data_in_$i + ad_connect axi_hsci_${i}/hsci_menc_clk hsci_menc_clk_$i + ad_connect axi_hsci_${i}/hsci_pclk hsci_pclk_$j + ad_connect axi_hsci_${i}/hsci_rst_seq_done hsci_rst_seq_done_$j + ad_connect axi_hsci_${i}/hsci_pll_locked hsci_pll_locked_$j + ad_connect axi_hsci_${i}/hsci_vtc_rdy_bsc_tx hsci_vtc_rdy_bsc_tx_$i + ad_connect axi_hsci_${i}/hsci_dly_rdy_bsc_tx hsci_dly_rdy_bsc_tx_$i + ad_connect axi_hsci_${i}/hsci_vtc_rdy_bsc_rx hsci_vtc_rdy_bsc_rx_$i + ad_connect axi_hsci_${i}/hsci_dly_rdy_bsc_rx hsci_dly_rdy_bsc_rx_$i + ad_connect hsci_data_out_$i axi_hsci_${i}/hsci_mosi_data + } + + ad_ip_instance ilvector_logic hsci_pll_reset_logic_0 + ad_ip_parameter hsci_pll_reset_logic_0 config.c_operation {and} + ad_ip_parameter hsci_pll_reset_logic_0 config.c_size {1} + + ad_connect axi_hsci_0/hsci_pll_reset hsci_pll_reset_logic_0/Op1 + ad_connect axi_hsci_1/hsci_pll_reset hsci_pll_reset_logic_0/Op2 + ad_connect hsci_pll_reset_logic_0/Res hsci_pll_reset_0 + + ad_ip_instance ilvector_logic hsci_pll_reset_logic_1 + ad_ip_parameter hsci_pll_reset_logic_1 config.c_operation {and} + ad_ip_parameter hsci_pll_reset_logic_1 config.c_size {1} + + ad_connect axi_hsci_2/hsci_pll_reset hsci_pll_reset_logic_1/Op1 + ad_connect axi_hsci_3/hsci_pll_reset hsci_pll_reset_logic_1/Op2 + ad_connect hsci_pll_reset_logic_1/Res hsci_pll_reset_1 + + ad_ip_instance axi_clkgen axi_hsci_clkgen + ad_ip_parameter axi_hsci_clkgen CONFIG.ID 1 + ad_ip_parameter axi_hsci_clkgen CONFIG.CLKIN_PERIOD 10 + ad_ip_parameter axi_hsci_clkgen CONFIG.VCO_DIV 1 + ad_ip_parameter axi_hsci_clkgen CONFIG.VCO_MUL 8 + ad_ip_parameter axi_hsci_clkgen CONFIG.CLK0_DIV 4 + + create_bd_port -dir O selectio_clk_in + + ad_connect axi_ddr_cntrl/addn_ui_clkout1 axi_hsci_clkgen/clk + ad_connect selectio_clk_in axi_hsci_clkgen/clk_0 +} + +# common xcvr + +ad_ip_instance util_adxcvr util_apollo_xcvr +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_FBDIV_4_5 5 +ad_ip_parameter util_apollo_xcvr CONFIG.TX_NUM_OF_LANES $MAX_TX_LANES +ad_ip_parameter util_apollo_xcvr CONFIG.RX_NUM_OF_LANES $MAX_RX_LANES +ad_ip_parameter util_apollo_xcvr CONFIG.RX_OUT_DIV 1 +ad_ip_parameter util_apollo_xcvr CONFIG.LINK_MODE $ENCODER_SEL +ad_ip_parameter util_apollo_xcvr CONFIG.RX_LANE_RATE $RX_LANE_RATE +ad_ip_parameter util_apollo_xcvr CONFIG.TX_LANE_RATE $TX_LANE_RATE + +ad_ip_instance axi_adxcvr axi_apollo_rx_xcvr +ad_ip_parameter axi_apollo_rx_xcvr CONFIG.ID 0 +ad_ip_parameter axi_apollo_rx_xcvr CONFIG.LINK_MODE $ENCODER_SEL +ad_ip_parameter axi_apollo_rx_xcvr CONFIG.NUM_OF_LANES $MAX_RX_LANES +ad_ip_parameter axi_apollo_rx_xcvr CONFIG.TX_OR_RX_N 0 +ad_ip_parameter axi_apollo_rx_xcvr CONFIG.QPLL_ENABLE 0 +ad_ip_parameter axi_apollo_rx_xcvr CONFIG.LPM_OR_DFE_N 1 +ad_ip_parameter axi_apollo_rx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0 + +ad_ip_instance axi_adxcvr axi_apollo_tx_xcvr +ad_ip_parameter axi_apollo_tx_xcvr CONFIG.ID 0 +ad_ip_parameter axi_apollo_tx_xcvr CONFIG.LINK_MODE $ENCODER_SEL +ad_ip_parameter axi_apollo_tx_xcvr CONFIG.NUM_OF_LANES $MAX_TX_LANES +ad_ip_parameter axi_apollo_tx_xcvr CONFIG.TX_OR_RX_N 1 +ad_ip_parameter axi_apollo_tx_xcvr CONFIG.QPLL_ENABLE 1 +ad_ip_parameter axi_apollo_tx_xcvr CONFIG.SYS_CLK_SEL 0x3 ; # QPLL0 + +# adc peripherals + +adi_axi_jesd204_rx_create axi_apollo_rx_jesd $RX_NUM_OF_LANES $RX_NUM_LINKS $ENCODER_SEL +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.TPL_DATA_PATH_WIDTH $RX_DATAPATH_WIDTH + +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.SYSREF_IOB false +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 1 + +adi_tpl_jesd204_rx_create rx_apollo_tpl_core $RX_NUM_OF_LANES \ + $RX_NUM_OF_CONVERTERS \ + $RX_SAMPLES_PER_FRAME \ + $RX_SAMPLE_WIDTH \ + $RX_DATAPATH_WIDTH \ + $RX_DMA_SAMPLE_WIDTH + +ad_ip_instance util_cpack2 util_apollo_cpack [list \ + NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $RX_DMA_SAMPLE_WIDTH \ +] + +ad_ip_parameter util_apollo_cpack CONFIG.PIPELINE_STAGES 2 + +set adc_data_offload_size [expr $adc_data_width / 8 * 2**$adc_fifo_address_width] +ad_data_offload_create $adc_data_offload_name \ + 0 \ + $adc_do_mem_type \ + $adc_data_offload_size \ + $adc_data_width \ + $adc_data_width \ + $do_axi_data_width \ + $SHARED_DEVCLK + +ad_ip_parameter $adc_data_offload_name/i_data_offload CONFIG.HAS_BYPASS $DO_HAS_BYPASS + +ad_ip_instance axi_dmac axi_apollo_rx_dma +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_TYPE_SRC 1 +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.ID 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.AXI_SLICE_SRC 1 +ad_ip_parameter axi_apollo_rx_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_apollo_rx_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_LENGTH_WIDTH 24 +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096 +ad_ip_parameter axi_apollo_rx_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width +ad_ip_parameter axi_apollo_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 512 + +# extra GPIO peripheral + +ad_ip_instance axi_gpio axi_gpio_2 [list \ + C_INTERRUPT_PRESENT 1 \ + C_IS_DUAL 1 \ +] + +create_bd_port -dir I -from 31 -to 0 gpio2_i +create_bd_port -dir O -from 31 -to 0 gpio2_o +create_bd_port -dir O -from 31 -to 0 gpio2_t +create_bd_port -dir I -from 31 -to 0 gpio3_i +create_bd_port -dir O -from 31 -to 0 gpio3_o +create_bd_port -dir O -from 31 -to 0 gpio3_t + +# dac peripherals + +adi_axi_jesd204_tx_create axi_apollo_tx_jesd $TX_NUM_OF_LANES $TX_NUM_LINKS $ENCODER_SEL +ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.TPL_DATA_PATH_WIDTH $TX_DATAPATH_WIDTH + +ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.SYSREF_IOB false +#ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 + +adi_tpl_jesd204_tx_create tx_apollo_tpl_core $TX_NUM_OF_LANES \ + $TX_NUM_OF_CONVERTERS \ + $TX_SAMPLES_PER_FRAME \ + $TX_SAMPLE_WIDTH \ + $TX_DATAPATH_WIDTH \ + $TX_DMA_SAMPLE_WIDTH + +ad_ip_parameter tx_apollo_tpl_core/dac_tpl_core CONFIG.IQCORRECTION_DISABLE 0 + +ad_ip_instance util_upack2 util_apollo_upack [list \ + NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \ + SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \ + SAMPLE_DATA_WIDTH $TX_DMA_SAMPLE_WIDTH \ +] + +ad_ip_parameter util_apollo_upack CONFIG.PIPELINE_STAGES 2 + +set dac_data_offload_size [expr $dac_data_width / 8 * 2**$dac_fifo_address_width] +ad_data_offload_create $dac_data_offload_name \ + 1 \ + $dac_do_mem_type \ + $dac_data_offload_size \ + $dac_data_width \ + $dac_data_width \ + $do_axi_data_width \ + $SHARED_DEVCLK + +ad_ip_parameter $dac_data_offload_name/i_data_offload CONFIG.HAS_BYPASS $DO_HAS_BYPASS + +ad_ip_instance axi_dmac axi_apollo_tx_dma +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_TYPE_SRC 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_TYPE_DEST 1 +ad_ip_parameter axi_apollo_tx_dma CONFIG.ID 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.AXI_SLICE_DEST 1 +ad_ip_parameter axi_apollo_tx_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_LENGTH_WIDTH 24 +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_apollo_tx_dma CONFIG.CYCLIC 1 +ad_ip_parameter axi_apollo_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096 +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 512 +ad_ip_parameter axi_apollo_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width + +# reference clocks & resets + +for {set i 0} {$i < [expr max($MAX_TX_LANES,$MAX_RX_LANES)]} {incr i} { + set quad_index [expr int($i / 4)] + if {[expr $i % 4] == 0} { + create_bd_port -dir I ref_clk_q$quad_index + ad_xcvrpll ref_clk_q$quad_index util_apollo_xcvr/qpll_ref_clk_$i + } + ad_xcvrpll ref_clk_q$quad_index util_apollo_xcvr/cpll_ref_clk_$i +} + +ad_xcvrpll axi_apollo_tx_xcvr/up_pll_rst util_apollo_xcvr/up_qpll_rst_* +ad_xcvrpll axi_apollo_rx_xcvr/up_pll_rst util_apollo_xcvr/up_cpll_rst_* + +ad_connect $sys_cpu_resetn util_apollo_xcvr/up_rstn +ad_connect $sys_cpu_clk util_apollo_xcvr/up_clk + +# connections (adc) +set max_lane_map {3 2 1 0 7 6 5 4 11 10 8 9 12 13 14 15} +set lane_map {} + +for {set i 0} {$i < $RX_NUM_LINKS} {incr i} { + for {set j 0} {$j < $RX_JESD_L} {incr j} { + set cur_lane [expr $i*$MAX_RX_LANES_PER_LINK+$j] + lappend lane_map [lindex $max_lane_map $cur_lane] + } +} +ad_xcvrcon util_apollo_xcvr axi_apollo_rx_xcvr axi_apollo_rx_jesd $max_lane_map {} rx_device_clk $MAX_RX_LANES $lane_map + +# connections (dac) +set max_lane_map {3 2 1 0 5 4 7 6 8 11 10 9 12 13 14 15} +set lane_map {} + +for {set i 0} {$i < $TX_NUM_LINKS} {incr i} { + for {set j 0} {$j < $TX_JESD_L} {incr j} { + set cur_lane [expr $i*$MAX_TX_LANES_PER_LINK+$j] + lappend lane_map [lindex $max_lane_map $cur_lane] + } +} +ad_xcvrcon util_apollo_xcvr axi_apollo_tx_xcvr axi_apollo_tx_jesd $max_lane_map {} tx_device_clk $MAX_TX_LANES $lane_map + +# device clock domain +ad_connect rx_device_clk rx_apollo_tpl_core/link_clk +ad_connect rx_device_clk util_apollo_cpack/clk +ad_connect rx_device_clk $adc_data_offload_name/s_axis_aclk + +ad_connect tx_device_clk tx_apollo_tpl_core/link_clk +ad_connect tx_device_clk util_apollo_upack/clk +ad_connect tx_device_clk $dac_data_offload_name/m_axis_aclk + +# Clocks +ad_connect $sys_dma_clk $adc_data_offload_name/m_axis_aclk +ad_connect $sys_dma_clk $dac_data_offload_name/s_axis_aclk + +ad_connect $sys_dma_clk axi_apollo_rx_dma/s_axis_aclk +ad_connect $sys_dma_clk axi_apollo_tx_dma/m_axis_aclk +ad_connect $sys_cpu_clk $dac_data_offload_name/s_axi_aclk +ad_connect $sys_cpu_clk $adc_data_offload_name/s_axi_aclk + +# Resets +# create_bd_port -dir O rx_device_clk_rstn + +ad_connect rx_device_clk_rstgen/peripheral_aresetn $adc_data_offload_name/s_axis_aresetn +ad_connect $sys_dma_resetn $adc_data_offload_name/m_axis_aresetn +ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn +ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn + +ad_connect $sys_dma_resetn axi_apollo_rx_dma/m_dest_axi_aresetn +ad_connect $sys_dma_resetn axi_apollo_tx_dma/m_src_axi_aresetn +ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn +ad_connect $sys_cpu_resetn $adc_data_offload_name/s_axi_aresetn + +# +# connect adc dataflow +# +# Connect Link Layer to Transport Layer +# +ad_connect axi_apollo_rx_jesd/rx_sof rx_apollo_tpl_core/link_sof +ad_connect axi_apollo_rx_jesd/rx_data_tdata rx_apollo_tpl_core/link_data +ad_connect axi_apollo_rx_jesd/rx_data_tvalid rx_apollo_tpl_core/link_valid + +ad_connect rx_apollo_tpl_core/adc_valid_0 util_apollo_cpack/fifo_wr_en +for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} { + ad_connect rx_apollo_tpl_core/adc_enable_$i util_apollo_cpack/enable_$i + ad_connect rx_apollo_tpl_core/adc_data_$i util_apollo_cpack/fifo_wr_data_$i +} +ad_connect rx_apollo_tpl_core/adc_dovf util_apollo_cpack/fifo_wr_overflow + +ad_connect util_apollo_cpack/packed_fifo_wr_data $adc_data_offload_name/s_axis_tdata +ad_connect util_apollo_cpack/packed_fifo_wr_en $adc_data_offload_name/s_axis_tvalid +ad_connect $adc_data_offload_name/s_axis_tlast GND +ad_connect $adc_data_offload_name/s_axis_tkeep VCC + +ad_connect $adc_data_offload_name/m_axis axi_apollo_rx_dma/s_axis + +# connect dac dataflow +# + +# Connect Link Layer to Transport Layer +# +ad_connect tx_apollo_tpl_core/link axi_apollo_tx_jesd/tx_data + +ad_connect tx_apollo_tpl_core/dac_valid_0 util_apollo_upack/fifo_rd_en +for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} { + ad_connect util_apollo_upack/fifo_rd_data_$i tx_apollo_tpl_core/dac_data_$i + ad_connect tx_apollo_tpl_core/dac_enable_$i util_apollo_upack/enable_$i +} + +ad_connect $dac_data_offload_name/s_axis axi_apollo_tx_dma/m_axis + +ad_connect util_apollo_upack/s_axis $dac_data_offload_name/m_axis + +ad_connect $dac_data_offload_name/init_req axi_apollo_tx_dma/m_axis_xfer_req +ad_connect $adc_data_offload_name/init_req axi_apollo_rx_dma/s_axis_xfer_req +ad_connect tx_apollo_tpl_core/dac_dunf GND + +# extra GPIOs + +ad_connect gpio2_i axi_gpio_2/gpio_io_i +ad_connect gpio2_o axi_gpio_2/gpio_io_o +ad_connect gpio2_t axi_gpio_2/gpio_io_t +ad_connect gpio3_i axi_gpio_2/gpio2_io_i +ad_connect gpio3_o axi_gpio_2/gpio2_io_o +ad_connect gpio3_t axi_gpio_2/gpio2_io_t + +# interconnect (cpu) + +ad_cpu_interconnect 0x44a60000 axi_apollo_rx_xcvr +ad_cpu_interconnect 0x44b60000 axi_apollo_tx_xcvr +ad_cpu_interconnect 0x44a10000 rx_apollo_tpl_core +ad_cpu_interconnect 0x44b10000 tx_apollo_tpl_core +ad_cpu_interconnect 0x44a90000 axi_apollo_rx_jesd +ad_cpu_interconnect 0x44b90000 axi_apollo_tx_jesd +ad_cpu_interconnect 0x7c420000 axi_apollo_rx_dma +ad_cpu_interconnect 0x7c430000 axi_apollo_tx_dma +ad_cpu_interconnect 0x7c440000 $dac_data_offload_name +ad_cpu_interconnect 0x7c450000 $adc_data_offload_name +ad_cpu_interconnect 0x7c470000 axi_gpio_2 +if {!$HSCI_BYPASS} { + ad_cpu_interconnect 0x44ad0000 axi_hsci_clkgen + ad_cpu_interconnect 0x7c500000 axi_hsci_0 + ad_cpu_interconnect 0x7c600000 axi_hsci_1 + ad_cpu_interconnect 0x7c700000 axi_hsci_2 + ad_cpu_interconnect 0x7c800000 axi_hsci_3 +} +ad_cpu_interconnect 0x7c900000 axi_adf4030_0 +# Reserved for TDD! 0x7c460000 + +# interconnect (gt/adc) + +ad_mem_hp0_interconnect $sys_cpu_clk axi_apollo_rx_xcvr/m_axi +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_dma_clk axi_apollo_rx_dma/m_dest_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect $sys_dma_clk axi_apollo_tx_dma/m_src_axi + +# interrupts + +ad_cpu_interrupt ps-13 mb-12 axi_apollo_rx_dma/irq +ad_cpu_interrupt ps-12 mb-13 axi_apollo_tx_dma/irq +ad_cpu_interrupt ps-11 mb-14 axi_apollo_rx_jesd/irq +ad_cpu_interrupt ps-10 mb-15 axi_apollo_tx_jesd/irq +ad_cpu_interrupt ps-14 mb-8 axi_gpio_2/ip2intc_irpt + +# +# Sync at TPL level +# + +create_bd_port -dir I ext_sync_in + +# Enable ADC external sync +ad_ip_parameter rx_apollo_tpl_core/adc_tpl_core CONFIG.EXT_SYNC 1 +ad_connect ext_sync_in rx_apollo_tpl_core/adc_tpl_core/adc_sync_in + +# Enable DAC external sync +ad_ip_parameter tx_apollo_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1 +ad_connect ext_sync_in tx_apollo_tpl_core/dac_tpl_core/dac_sync_in + +ad_ip_instance ilvector_logic manual_sync_or [list \ + C_SIZE 1 \ + C_OPERATION {or} \ +] + +ad_connect rx_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or/Op1 +ad_connect tx_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or/Op2 + +ad_connect manual_sync_or/Res tx_apollo_tpl_core/dac_tpl_core/dac_sync_manual_req_in +ad_connect manual_sync_or/Res rx_apollo_tpl_core/adc_tpl_core/adc_sync_manual_req_in + +# Reset pack cores +ad_ip_instance ilreduced_logic cpack_rst_logic +ad_ip_parameter cpack_rst_logic config.c_operation {or} +ad_ip_parameter cpack_rst_logic config.c_size {3} + +ad_ip_instance ilvector_logic rx_do_rstout_logic +ad_ip_parameter rx_do_rstout_logic config.c_operation {not} +ad_ip_parameter rx_do_rstout_logic config.c_size {1} + +ad_connect $adc_data_offload_name/s_axis_tready rx_do_rstout_logic/Op1 + +ad_ip_instance ilconcat cpack_reset_sources +ad_ip_parameter cpack_reset_sources config.num_ports {3} +ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0 +ad_connect rx_apollo_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1 +ad_connect rx_do_rstout_logic/res cpack_reset_sources/in2 + +ad_connect cpack_reset_sources/dout cpack_rst_logic/op1 +ad_connect cpack_rst_logic/res util_apollo_cpack/reset + +# Reset unpack cores +ad_ip_instance ilreduced_logic upack_rst_logic +ad_ip_parameter upack_rst_logic config.c_operation {or} +ad_ip_parameter upack_rst_logic config.c_size {2} + +ad_ip_instance ilconcat upack_reset_sources +ad_ip_parameter upack_reset_sources config.num_ports {2} +ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0 +ad_connect tx_apollo_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1 + +ad_connect upack_reset_sources/dout upack_rst_logic/op1 +ad_connect upack_rst_logic/res util_apollo_upack/reset + +if {$TDD_SUPPORT} { + ad_ip_instance util_tdd_sync tdd_sync_0 + ad_connect tx_device_clk tdd_sync_0/clk + ad_connect tx_device_clk_rstgen/peripheral_aresetn tdd_sync_0/rstn + ad_connect tdd_sync_0/sync_in GND + ad_connect tdd_sync_0/sync_mode GND + ad_ip_parameter tdd_sync_0 CONFIG.TDD_SYNC_PERIOD 250000000; # More or less 1 PPS ;) + + ad_ip_instance axi_tdd axi_tdd_0 [list ASYNC_TDD_SYNC 0] + ad_connect tx_device_clk axi_tdd_0/clk + ad_connect tx_device_clk_rstgen/peripheral_reset axi_tdd_0/rst + ad_connect $sys_cpu_clk axi_tdd_0/s_axi_aclk + ad_connect $sys_cpu_resetn axi_tdd_0/s_axi_aresetn + ad_cpu_interconnect 0x7c460000 axi_tdd_0 + + ad_connect tdd_sync_0/sync_out axi_tdd_0/tdd_sync + + delete_bd_objs [get_bd_nets apollo_adc_fifo_dma_wr] + + ad_connect axi_tdd_0/tdd_tx_valid $dac_data_offload_name/sync_ext + ad_connect axi_tdd_0/tdd_rx_valid $adc_data_offload_name/sync_ext + +} else { + ad_connect GND $dac_data_offload_name/sync_ext + ad_connect GND $adc_data_offload_name/sync_ext +} diff --git a/projects/ad_xband16_ebz/common/hsci_phy_top.sv b/projects/ad_xband16_ebz/common/hsci_phy_top.sv new file mode 100755 index 0000000000..a108f5e635 --- /dev/null +++ b/projects/ad_xband16_ebz/common/hsci_phy_top.sv @@ -0,0 +1,236 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2026 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ps/1ps + +module hsci_phy_top ( + + input wire pll_inclk, + input wire [0:1] hsci_pll_reset, + + output logic [0:1] hsci_pclk, + output logic [0:1] hsci_pll_locked, + + output logic [0:3] hsci_mosi_d_p, + output logic [0:3] hsci_mosi_d_n, + + input wire [0:3] hsci_miso_d_p, + input wire [0:3] hsci_miso_d_n, + + output logic [0:3] hsci_mosi_clk_p, + output logic [0:3] hsci_mosi_clk_n, + + input wire [0:3] hsci_miso_clk_p, + input wire [0:3] hsci_miso_clk_n, + + input wire [7:0] hsci_menc_clk_0, + input wire [7:0] hsci_menc_clk_1, + input wire [7:0] hsci_menc_clk_2, + input wire [7:0] hsci_menc_clk_3, + + input wire [7:0] hsci_mosi_data_0, + input wire [7:0] hsci_mosi_data_1, + input wire [7:0] hsci_mosi_data_2, + input wire [7:0] hsci_mosi_data_3, + + output logic [7:0] hsci_miso_data_0, + output logic [7:0] hsci_miso_data_1, + output logic [7:0] hsci_miso_data_2, + output logic [7:0] hsci_miso_data_3, + + output logic [0:3] vtc_rdy_bsc_tx, + output logic [0:3] dly_rdy_bsc_tx, + output logic [0:3] vtc_rdy_bsc_rx, + output logic [0:3] dly_rdy_bsc_rx, + output logic [0:1] rst_seq_done + +); + //TX + logic [7:0] hsci_mosi_data_br [0:3]; + logic [7:0] hsci_mosi_data [0:3]; + + // RX + logic [7:0] hsci_miso_data_br [0:3]; + logic [7:0] hsci_miso_data [0:3]; + logic [7:0] hsci_miso_clk_d [0:3]; + logic fifo_empty_6; + logic fifo_empty_8; + logic fifo_empty_45; + logic fifo_empty_47; + logic fifo_empty_0; + logic fifo_empty_2; + logic fifo_empty_39; + logic fifo_empty_41; + + assign hsci_mosi_data[0] = hsci_mosi_data_0; + assign hsci_mosi_data[1] = hsci_mosi_data_1; + assign hsci_mosi_data[2] = hsci_mosi_data_2; + assign hsci_mosi_data[3] = hsci_mosi_data_3; + + assign hsci_miso_data_0 = hsci_miso_data[0]; + assign hsci_miso_data_1 = hsci_miso_data[1]; + assign hsci_miso_data_2 = hsci_miso_data[2]; + assign hsci_miso_data_3 = hsci_miso_data[3]; + + function integer hssio_i; + input integer i; + hssio_i = i > 1 ? 1 : 0; + endfunction + + genvar i, j; + generate + for (i = 0; i < 4; i ++) begin + for (j = 0; j < 8; j ++) begin + assign hsci_mosi_data_br[i][7 - j] = hsci_mosi_data[i][j]; + assign hsci_miso_data[i][7 - j] = (rst_seq_done[hssio_i(i)]) ? hsci_miso_data_br[i][j] : 8'h0; + end + end + endgenerate + + high_speed_selectio_wiz_0 hssio_wiz_0 ( + .fifo_rd_clk_6 (hsci_pclk[0]), + .fifo_rd_clk_8 (hsci_pclk[0]), + .fifo_rd_clk_45 (hsci_pclk[0]), + .fifo_rd_clk_47 (hsci_pclk[0]), + .fifo_rd_en_6 (1'b0), + .fifo_rd_en_8 (1'b1 & !fifo_empty_8 & rst_seq_done[0]), + .fifo_rd_en_45 (1'b0), + .fifo_rd_en_47 (1'b1 & !fifo_empty_47 & rst_seq_done[0]), + .fifo_empty_6 (fifo_empty_6), + .fifo_empty_8 (fifo_empty_8), + .fifo_empty_45 (fifo_empty_45), + .fifo_empty_47 (fifo_empty_47), + .dly_rdy_bsc1 (dly_rdy_bsc_rx[1]), + .vtc_rdy_bsc1 (vtc_rdy_bsc_rx[1]), + .en_vtc_bsc1 (1'b1), + .vtc_rdy_bsc5 (vtc_rdy_bsc_tx[0]), + .dly_rdy_bsc5 (dly_rdy_bsc_tx[0]), + .en_vtc_bsc5 (1'b1), + .dly_rdy_bsc6 (dly_rdy_bsc_tx[1]), + .vtc_rdy_bsc6 (vtc_rdy_bsc_tx[1]), + .en_vtc_bsc6 (1'b1), + .dly_rdy_bsc7 (dly_rdy_bsc_rx[0]), + .vtc_rdy_bsc7 (vtc_rdy_bsc_rx[0]), + .en_vtc_bsc7 (1'b1), + .rst_seq_done (rst_seq_done[0]), + .shared_pll0_clkoutphy_out (), + .pll0_clkout0 (hsci_pclk[0]), + .rst (hsci_pll_reset[0]), + .clk (pll_inclk), + .pll0_locked (hsci_pll_locked[0]), + .data_in_p_0 (hsci_miso_d_p[0]), + .data_in_n_0 (hsci_miso_d_n[0]), + .data_to_fabric_data_in_p_0 (hsci_miso_data_br[0]), + .data_in_p_1 (hsci_miso_d_p[1]), + .data_in_n_1 (hsci_miso_d_n[1]), + .data_to_fabric_data_in_p_1 (hsci_miso_data_br[1]), + .clk_in_p_0 (hsci_miso_clk_p[0]), + .clk_in_n_0 (hsci_miso_clk_n[0]), + .data_to_fabric_clk_in_p_0 (hsci_miso_clk_d[0]), + .clk_in_p_1 (hsci_miso_clk_p[1]), + .clk_in_n_1 (hsci_miso_clk_n[1]), + .data_to_fabric_clk_in_p_1 (hsci_miso_clk_d[1]), + .data_out_p_0 (hsci_mosi_d_p[0]), + .data_out_n_0 (hsci_mosi_d_n[0]), + .data_from_fabric_data_out_p_0 (hsci_mosi_data_br[0]), + .data_out_p_1 (hsci_mosi_d_p[1]), + .data_out_n_1 (hsci_mosi_d_n[1]), + .data_from_fabric_data_out_p_1 (hsci_mosi_data_br[1]), + .clk_out_p_0 (hsci_mosi_clk_p[0]), + .clk_out_n_0 (hsci_mosi_clk_n[0]), + .data_from_fabric_clk_out_p_0 (hsci_menc_clk_0), + .clk_out_p_1 (hsci_mosi_clk_p[1]), + .clk_out_n_1 (hsci_mosi_clk_n[1]), + .data_from_fabric_clk_out_p_1 (hsci_menc_clk_1) + ); + + high_speed_selectio_wiz_1 hssio_wiz_1 ( + .fifo_rd_clk_0 (hsci_pclk[1]), + .fifo_rd_clk_2 (hsci_pclk[1]), + .fifo_rd_clk_39 (hsci_pclk[1]), + .fifo_rd_clk_41 (hsci_pclk[1]), + .fifo_rd_en_0 (1'b0), + .fifo_rd_en_2 (1'b1 & !fifo_empty_2 & rst_seq_done[1]), + .fifo_rd_en_39 (1'b0), + .fifo_rd_en_41 (1'b1 & !fifo_empty_41 & rst_seq_done[1]), + .fifo_empty_0 (fifo_empty_0), + .fifo_empty_2 (fifo_empty_2), + .fifo_empty_39 (fifo_empty_39), + .fifo_empty_41 (fifo_empty_41), + .dly_rdy_bsc0 (dly_rdy_bsc_rx[3]), + .vtc_rdy_bsc0 (vtc_rdy_bsc_rx[3]), + .en_vtc_bsc0 (1'b1), + .vtc_rdy_bsc1 (vtc_rdy_bsc_tx[3]), + .dly_rdy_bsc1 (dly_rdy_bsc_tx[3]), + .en_vtc_bsc1 (1'b1), + .dly_rdy_bsc6 (dly_rdy_bsc_rx[2]), + .vtc_rdy_bsc6 (vtc_rdy_bsc_rx[2]), + .en_vtc_bsc6 (1'b1), + .dly_rdy_bsc7 (dly_rdy_bsc_tx[2]), + .vtc_rdy_bsc7 (vtc_rdy_bsc_tx[2]), + .en_vtc_bsc7 (1'b1), + .rst_seq_done (rst_seq_done[1]), + .shared_pll0_clkoutphy_out (), + .pll0_clkout0 (hsci_pclk[1]), + .rst (hsci_pll_reset[1]), + .clk (pll_inclk), + .pll0_locked (hsci_pll_locked[1]), + .data_in_p_2 (hsci_miso_d_p[2]), + .data_in_n_2 (hsci_miso_d_n[2]), + .data_to_fabric_data_in_p_2 (hsci_miso_data_br[2]), + .data_in_p_3 (hsci_miso_d_p[3]), + .data_in_n_3 (hsci_miso_d_n[3]), + .data_to_fabric_data_in_p_3 (hsci_miso_data_br[3]), + .clk_in_p_2 (hsci_miso_clk_p[2]), + .clk_in_n_2 (hsci_miso_clk_n[2]), + .data_to_fabric_clk_in_p_2 (hsci_miso_clk_d[2]), + .clk_in_p_3 (hsci_miso_clk_p[3]), + .clk_in_n_3 (hsci_miso_clk_n[3]), + .data_to_fabric_clk_in_p_3 (hsci_miso_clk_d[3]), + .data_out_p_2 (hsci_mosi_d_p[2]), + .data_out_n_2 (hsci_mosi_d_n[2]), + .data_from_fabric_data_out_p_2 (hsci_mosi_data_br[2]), + .data_out_p_3 (hsci_mosi_d_p[3]), + .data_out_n_3 (hsci_mosi_d_n[3]), + .data_from_fabric_data_out_p_3 (hsci_mosi_data_br[3]), + .clk_out_p_2 (hsci_mosi_clk_p[2]), + .clk_out_n_2 (hsci_mosi_clk_n[2]), + .data_from_fabric_clk_out_p_2 (hsci_menc_clk_2), + .clk_out_p_3 (hsci_mosi_clk_p[3]), + .clk_out_n_3 (hsci_mosi_clk_n[3]), + .data_from_fabric_clk_out_p_3 (hsci_menc_clk_3) + ); + +endmodule diff --git a/projects/ad_xband16_ebz/vcu118/Makefile b/projects/ad_xband16_ebz/vcu118/Makefile new file mode 100644 index 0000000000..8f9fdb3695 --- /dev/null +++ b/projects/ad_xband16_ebz/vcu118/Makefile @@ -0,0 +1,49 @@ +#################################################################################### +## Copyright (c) 2026 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad_xband16_ebz_vcu118 + +M_DEPS += timing_constr.xdc +M_DEPS += ../common/hsci_phy_top.sv +M_DEPS += ${ADI_HDL_DIR}/projects/scripts/adi_pd.tcl +M_DEPS += ${ADI_HDL_DIR}/projects/common/xilinx/data_offload_bd.tcl +M_DEPS += ${ADI_HDL_DIR}/projects/common/xilinx/dacfifo_bd.tcl +M_DEPS += ${ADI_HDL_DIR}/projects/common/xilinx/adcfifo_bd.tcl +M_DEPS += ${ADI_HDL_DIR}/projects/common/vcu118/vcu118_system_constr.xdc +M_DEPS += ${ADI_HDL_DIR}/projects/common/vcu118/vcu118_system_bd.tcl +M_DEPS += ${ADI_HDL_DIR}/library/util_hbm/scripts/adi_util_hbm.tcl +M_DEPS += ${ADI_HDL_DIR}/library/jesd204/scripts/jesd204.tcl +M_DEPS += ${ADI_HDL_DIR}/library/common/ad_iobuf.v +M_DEPS += ${ADI_HDL_DIR}/library/common/ad_3w_spi.v +M_DEPS += ${ADI_HDL_DIR}/library/common/ad_rst.v +M_DEPS += ${ADI_HDL_DIR}/library/xilinx/common/ad_rst_constr.xdc +M_DEPS += ../../ad_xband16_ebz/common/ad_xband16_ebz_bd.tcl + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += axi_tdd +LIB_DEPS += axi_hsci +LIB_DEPS += axi_adf4030 +LIB_DEPS += axi_clkgen +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_do_ram +LIB_DEPS += util_hbm +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_tdd_sync +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad_xband16_ebz/vcu118/system_bd.tcl b/projects/ad_xband16_ebz/vcu118/system_bd.tcl new file mode 100644 index 0000000000..e20fcad91f --- /dev/null +++ b/projects/ad_xband16_ebz/vcu118/system_bd.tcl @@ -0,0 +1,195 @@ +############################################################################### +## Copyright (C) 2026 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl +source ../../ad_xband16_ebz/common/ad_xband16_ebz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +set MCS_MODE [ expr { [info exists ad_project_params(MCS_MODE)] \ + ? $ad_project_params(MCS_MODE) : "MASTER" } ] + +ad_ip_parameter axi_apollo_rx_jesd/rx CONFIG.NUM_INPUT_PIPELINE 3 +ad_ip_parameter axi_apollo_tx_jesd/tx CONFIG.NUM_OUTPUT_PIPELINE 1 + +# Set SPI clock to 100/32 = 3.125 MHz +ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 16 +ad_ip_parameter axi_spi CONFIG.Multiples16 2 + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + +# Parameters for 15.5Gpbs lane rate +ad_ip_parameter util_apollo_xcvr CONFIG.RX_CLK25_DIV 31 +ad_ip_parameter util_apollo_xcvr CONFIG.TX_CLK25_DIV 31 +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_CFG0 0x1fa +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_CFG1 0x2b +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_CFG2 0x2 +ad_ip_parameter util_apollo_xcvr CONFIG.CPLL_FBDIV 2 +ad_ip_parameter util_apollo_xcvr CONFIG.CH_HSPMUX 0x4040 +ad_ip_parameter util_apollo_xcvr CONFIG.PREIQ_FREQ_BST 1 +ad_ip_parameter util_apollo_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 +ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG0 0x3002 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG2 0x1E9 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3 0x23 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN2 0x23 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN3 0x23 +ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN4 0x23 +ad_ip_parameter util_apollo_xcvr CONFIG.RX_WIDEMODE_CDR 0x1 +ad_ip_parameter util_apollo_xcvr CONFIG.RX_XMODE_SEL 0x0 +ad_ip_parameter util_apollo_xcvr CONFIG.TXDRV_FREQBAND 1 +ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG1 0xAA00 +ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG2 0xAA00 +ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG3 0xAA00 +ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG0 0x3100 +ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG1 0x0 +ad_ip_parameter util_apollo_xcvr CONFIG.TX_PI_BIASSET 1 +ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG1 0x54 + +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_REFCLK_DIV 1 +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG0 0x333c +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG4 0x2 +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_FBDIV 20 +ad_ip_parameter util_apollo_xcvr CONFIG.PPF0_CFG 0xB00 +ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_LPF 0x2ff + +# 204C params 26.4 Gpbs +if {$ad_project_params(JESD_MODE) == "64B66B"} { + + # Set higher swing for the diff driver, other case 16.5Gbps won't work + ad_ip_parameter axi_apollo_tx_xcvr CONFIG.TX_DIFFCTRL 0xC + + # Lane rate indepentent parameters + ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3 0x10 + ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN2 0x10 + ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN3 0x10 + ad_ip_parameter util_apollo_xcvr CONFIG.RXCDR_CFG3_GEN4 0x10 + ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG1 0x0 + ad_ip_parameter util_apollo_xcvr CONFIG.RX_WIDEMODE_CDR 0x2 + ad_ip_parameter util_apollo_xcvr CONFIG.CH_HSPMUX 0x9090 + ad_ip_parameter util_apollo_xcvr CONFIG.PREIQ_FREQ_BST 3 + ad_ip_parameter util_apollo_xcvr CONFIG.TX_PI_BIASSET 3 + ad_ip_parameter util_apollo_xcvr CONFIG.RXDFE_KH_CFG2 0x281C + ad_ip_parameter util_apollo_xcvr CONFIG.RXDFE_KH_CFG3 0x4120 + + # Lane rate indepentent QPLL parameters + ad_ip_parameter util_apollo_xcvr CONFIG.PPF0_CFG 0x900 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG0 0x331c + + # Lane rate dependent QPLL params (these match for 26.4 Gpbs) + ad_ip_parameter util_apollo_xcvr CONFIG.PPF1_CFG 0x600 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_LPF 0x37f + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG2 0x0FC1 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG2_G3 0x0FC1 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_CFG4 0x84 + + # set dividers for 26.4 Gbps, are overwritten by software + ad_ip_parameter util_apollo_xcvr CONFIG.RX_CLK25_DIV 16 + ad_ip_parameter util_apollo_xcvr CONFIG.TX_CLK25_DIV 16 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_FBDIV 33 + ad_ip_parameter util_apollo_xcvr CONFIG.QPLL_REFCLK_DIV 1 + + if {$ad_project_params(RX_LANE_RATE) < 20} { + ad_ip_parameter util_apollo_xcvr CONFIG.RTX_BUF_CML_CTRL 0x5 + ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG0 0x0104 + } else { + ad_ip_parameter util_apollo_xcvr CONFIG.RTX_BUF_CML_CTRL 0x7 + ad_ip_parameter util_apollo_xcvr CONFIG.RXPI_CFG0 0x3006 + } + + if {$ad_project_params(TX_LANE_RATE) < 20} { + ad_ip_parameter util_apollo_xcvr CONFIG.TXDRV_FREQBAND 1 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG0 0x3C2 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG1 0xAA00 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG2 0xAA00 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG3 0xAA00 + ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG0 0x0100 + ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG1 0x1000 + ad_ip_parameter util_apollo_xcvr CONFIG.TXSWBST_EN 0 + } else { + ad_ip_parameter util_apollo_xcvr CONFIG.TXDRV_FREQBAND 3 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG0 0x3C6 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG1 0xF800 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG2 0xF800 + ad_ip_parameter util_apollo_xcvr CONFIG.TXFE_CFG3 0xF800 + ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG0 0x3000 + ad_ip_parameter util_apollo_xcvr CONFIG.TXPI_CFG1 0x0 + ad_ip_parameter util_apollo_xcvr CONFIG.TXSWBST_EN 1 + } + +} + +# Second SPI controller +create_bd_port -dir O -from 7 -to 0 spi_2_csn_o +create_bd_port -dir I -from 7 -to 0 spi_2_csn_i +create_bd_port -dir I spi_2_clk_i +create_bd_port -dir O spi_2_clk_o +create_bd_port -dir I spi_2_sdo_i +create_bd_port -dir O spi_2_sdo_o +create_bd_port -dir I spi_2_sdi_i + +ad_ip_instance axi_quad_spi axi_spi_2 +ad_ip_parameter axi_spi_2 CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_2 CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi_2 CONFIG.C_SCK_RATIO 8 +# ad_ip_parameter axi_spi_2 CONFIG.Multiples16 8 + +ad_connect spi_2_csn_i axi_spi_2/ss_i +ad_connect spi_2_csn_o axi_spi_2/ss_o +ad_connect spi_2_clk_i axi_spi_2/sck_i +ad_connect spi_2_clk_o axi_spi_2/sck_o +ad_connect spi_2_sdo_i axi_spi_2/io0_i +ad_connect spi_2_sdo_o axi_spi_2/io0_o +ad_connect spi_2_sdi_i axi_spi_2/io1_i + +ad_connect sys_cpu_clk axi_spi_2/ext_spi_clk + +ad_cpu_interrupt ps-15 mb-7 axi_spi_2/ip2intc_irpt + +ad_cpu_interconnect 0x44A80000 axi_spi_2 + +# Third SPI controller +create_bd_port -dir O -from 7 -to 0 spi_3_csn_o +create_bd_port -dir I -from 7 -to 0 spi_3_csn_i +create_bd_port -dir I spi_3_clk_i +create_bd_port -dir O spi_3_clk_o +create_bd_port -dir I spi_3_sdo_i +create_bd_port -dir O spi_3_sdo_o +create_bd_port -dir I spi_3_sdi_i + +ad_ip_instance axi_quad_spi axi_spi_3 +ad_ip_parameter axi_spi_3 CONFIG.C_USE_STARTUP 0 +ad_ip_parameter axi_spi_3 CONFIG.C_NUM_SS_BITS 8 +ad_ip_parameter axi_spi_3 CONFIG.C_SCK_RATIO 16 +ad_ip_parameter axi_spi_3 CONFIG.Multiples16 16 + +ad_connect spi_3_csn_i axi_spi_3/ss_i +ad_connect spi_3_csn_o axi_spi_3/ss_o +ad_connect spi_3_clk_i axi_spi_3/sck_i +ad_connect spi_3_clk_o axi_spi_3/sck_o +ad_connect spi_3_sdo_i axi_spi_3/io0_i +ad_connect spi_3_sdo_o axi_spi_3/io0_o +ad_connect spi_3_sdi_i axi_spi_3/io1_i + +ad_connect sys_cpu_clk axi_spi_3/ext_spi_clk + +ad_cpu_interrupt ps-9 mb-16 axi_spi_3/ip2intc_irpt + +ad_cpu_interconnect 0x44B80000 axi_spi_3 + +set_property range 256K [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_hsci_0}] +set_property range 256K [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_hsci_1}] +set_property range 256K [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_hsci_2}] +set_property range 256K [get_bd_addr_segs {sys_mb/Data/SEG_data_axi_hsci_3}] diff --git a/projects/ad_xband16_ebz/vcu118/system_constr.xdc b/projects/ad_xband16_ebz/vcu118/system_constr.xdc new file mode 100644 index 0000000000..4eb2c8912c --- /dev/null +++ b/projects/ad_xband16_ebz/vcu118/system_constr.xdc @@ -0,0 +1,273 @@ +############################################################################### +## Copyright (C) 2026 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# +## Quad-Apollo +# + +set_property -dict {PACKAGE_PIN AG45 } [get_ports m2c_p[10] ]; ## DP8_M2C_P B8 MGTYRXP0_122 +set_property -dict {PACKAGE_PIN AG46 } [get_ports m2c_n[10] ]; ## DP8_M2C_N B9 MGTYRXN0_122 +set_property -dict {PACKAGE_PIN AF43 } [get_ports m2c_p[11] ]; ## DP9_M2C_P B4 MGTYRXP1_122 +set_property -dict {PACKAGE_PIN AF44 } [get_ports m2c_n[11] ]; ## DP9_M2C_N B5 MGTYRXN1_122 +set_property -dict {PACKAGE_PIN AE45 } [get_ports m2c_p[9] ]; ## DP10_M2C_P Y10 MGTYRXP2_122 +set_property -dict {PACKAGE_PIN AE46 } [get_ports m2c_n[9] ]; ## DP10_M2C_N Y11 MGTYRXN2_122 +set_property -dict {PACKAGE_PIN AD43 } [get_ports m2c_p[8] ]; ## DP11_M2C_P Z12 MGTYRXP3_122 +set_property -dict {PACKAGE_PIN AD44 } [get_ports m2c_n[8] ]; ## DP11_M2C_N Z13 MGTYRXN3_122 +set_property -dict {PACKAGE_PIN AC45 } [get_ports m2c_p[7] ]; ## DP12_M2C_P Y14 MGTYRXP0_125 +set_property -dict {PACKAGE_PIN AC46 } [get_ports m2c_n[7] ]; ## DP12_M2C_N Y15 MGTYRXN0_125 +set_property -dict {PACKAGE_PIN AB43 } [get_ports m2c_p[6] ]; ## DP13_M2C_P Z16 MGTYRXP1_125 +set_property -dict {PACKAGE_PIN AB44 } [get_ports m2c_n[6] ]; ## DP13_M2C_N Z17 MGTYRXN1_125 +set_property -dict {PACKAGE_PIN AA45 } [get_ports m2c_p[5] ]; ## DP14_M2C_P Y18 MGTYRXP2_125 +set_property -dict {PACKAGE_PIN AA46 } [get_ports m2c_n[5] ]; ## DP14_M2C_N Y19 MGTYRXN2_125 +set_property -dict {PACKAGE_PIN Y43 } [get_ports m2c_p[4] ]; ## DP15_M2C_P Y22 MGTYRXP3_125 +set_property -dict {PACKAGE_PIN Y44 } [get_ports m2c_n[4] ]; ## DP15_M2C_N Y23 MGTYRXN3_125 +set_property -dict {PACKAGE_PIN J45 } [get_ports m2c_p[2] ]; ## DP17_M2C_P Y34 MGTYRXP1_127 +set_property -dict {PACKAGE_PIN J46 } [get_ports m2c_n[2] ]; ## DP17_M2C_N Y35 MGTYRXN1_127 +set_property -dict {PACKAGE_PIN E45 } [get_ports m2c_p[0] ]; ## DP19_M2C_P Y38 MGTYRXP3_127 +set_property -dict {PACKAGE_PIN E46 } [get_ports m2c_n[0] ]; ## DP19_M2C_N Y39 MGTYRXN3_127 +set_property -dict {PACKAGE_PIN L45 } [get_ports m2c_p[3] ]; ## DP16_M2C_P Z32 MGTYRXP0_127 +set_property -dict {PACKAGE_PIN L46 } [get_ports m2c_n[3] ]; ## DP16_M2C_N Z33 MGTYRXN0_127 +set_property -dict {PACKAGE_PIN G45 } [get_ports m2c_p[1] ]; ## DP18_M2C_P Z36 MGTYRXP2_127 +set_property -dict {PACKAGE_PIN G46 } [get_ports m2c_n[1] ]; ## DP18_M2C_N Z37 MGTYRXN2_127 +set_property -dict {PACKAGE_PIN AU45 } [get_ports m2c_p[15] ]; ## DP23_M2C_P M2 MGTYRXP3_120 +set_property -dict {PACKAGE_PIN AU46 } [get_ports m2c_n[15] ]; ## DP23_M2C_N M3 MGTYRXN3_120 +set_property -dict {PACKAGE_PIN AW45 } [get_ports m2c_p[14] ]; ## DP22_M2C_P M6 MGTYRXP2_120 +set_property -dict {PACKAGE_PIN AW46 } [get_ports m2c_n[14] ]; ## DP22_M2C_N M7 MGTYRXN2_120 +set_property -dict {PACKAGE_PIN BA45 } [get_ports m2c_p[13] ]; ## DP21_M2C_P M10 MGTYRXP1_120 +set_property -dict {PACKAGE_PIN BA46 } [get_ports m2c_n[13] ]; ## DP21_M2C_N M11 MGTYRXN1_120 +set_property -dict {PACKAGE_PIN BC45 } [get_ports m2c_p[12] ]; ## DP20_M2C_P M14 MGTYRXP0_120 +set_property -dict {PACKAGE_PIN BC46 } [get_ports m2c_n[12] ]; ## DP20_M2C_N M15 MGTYRXN0_120 +# +## Serdes Data Output +# +set_property -dict {PACKAGE_PIN AK42 } [get_ports c2m_p[8] ]; ## DP8_C2M_P B28 MGTYTXP0_122 +set_property -dict {PACKAGE_PIN AK43 } [get_ports c2m_n[8] ]; ## DP8_C2M_N B29 MGTYTXN0_122 +set_property -dict {PACKAGE_PIN AJ40 } [get_ports c2m_p[11] ]; ## DP9_C2M_P B24 MGTYTXP1_122 +set_property -dict {PACKAGE_PIN AJ41 } [get_ports c2m_n[11] ]; ## DP9_C2M_N B25 MGTYTXN1_122 +set_property -dict {PACKAGE_PIN AG40 } [get_ports c2m_p[10] ]; ## DP10_C2M_P Z24 MGTYTXP2_122 +set_property -dict {PACKAGE_PIN AG41 } [get_ports c2m_n[10] ]; ## DP10_C2M_N Z25 MGTYTXN2_122 +set_property -dict {PACKAGE_PIN AE40 } [get_ports c2m_p[9] ]; ## DP11_C2M_P Y26 MGTYTXP3_122 +set_property -dict {PACKAGE_PIN AE41 } [get_ports c2m_n[9] ]; ## DP11_C2M_N Y27 MGTYTXN3_122 +set_property -dict {PACKAGE_PIN AC40 } [get_ports c2m_p[5] ]; ## DP12_C2M_P Z28 MGTYTXP0_125 +set_property -dict {PACKAGE_PIN AC41 } [get_ports c2m_n[5] ]; ## DP12_C2M_N Z29 MGTYTXN0_125 +set_property -dict {PACKAGE_PIN AA40 } [get_ports c2m_p[4] ]; ## DP13_C2M_P Y30 MGTYTXP1_125 +set_property -dict {PACKAGE_PIN AA41 } [get_ports c2m_n[4] ]; ## DP13_C2M_N Y31 MGTYTXN1_125 +set_property -dict {PACKAGE_PIN W40 } [get_ports c2m_p[7] ]; ## DP14_C2M_P M18 MGTYTXP2_125 +set_property -dict {PACKAGE_PIN W41 } [get_ports c2m_n[7] ]; ## DP14_C2M_N M19 MGTYTXN2_125 +set_property -dict {PACKAGE_PIN U40 } [get_ports c2m_p[6] ]; ## DP15_C2M_P M22 MGTYTXP3_125 +set_property -dict {PACKAGE_PIN U41 } [get_ports c2m_n[6] ]; ## DP15_C2M_N M23 MGTYTXN3_125 +set_property -dict {PACKAGE_PIN H42 } [get_ports c2m_p[3] ]; ## DP16_C2M_P M26 MGTYTXP0_127 +set_property -dict {PACKAGE_PIN H43 } [get_ports c2m_n[3] ]; ## DP16_C2M_N M27 MGTYTXN0_127 +set_property -dict {PACKAGE_PIN F42 } [get_ports c2m_p[2] ]; ## DP17_C2M_P M30 MGTYTXP1_127 +set_property -dict {PACKAGE_PIN F43 } [get_ports c2m_n[2] ]; ## DP17_C2M_N M31 MGTYTXN1_127 +set_property -dict {PACKAGE_PIN D42 } [get_ports c2m_p[1] ]; ## DP18_C2M_P M34 MGTYTXP2_127 +set_property -dict {PACKAGE_PIN D43 } [get_ports c2m_n[1] ]; ## DP18_C2M_N M35 MGTYTXN2_127 +set_property -dict {PACKAGE_PIN B42 } [get_ports c2m_p[0] ]; ## DP19_C2M_P M38 MGTYTXP3_127 +set_property -dict {PACKAGE_PIN B43 } [get_ports c2m_n[0] ]; ## DP19_C2M_N M39 MGTYTXN3_127 +set_property -dict {PACKAGE_PIN AV42 } [get_ports c2m_p[15] ]; ## DP23_C2M_P Y2 MGTYTXP3_120 +set_property -dict {PACKAGE_PIN AV43 } [get_ports c2m_n[15] ]; ## DP23_C2M_N Y3 MGTYTXN3_120 +set_property -dict {PACKAGE_PIN BB42 } [get_ports c2m_p[13] ]; ## DP21_C2M_P Y6 MGTYTXP1_120 +set_property -dict {PACKAGE_PIN BB43 } [get_ports c2m_n[13] ]; ## DP21_C2M_N Y7 MGTYTXN1_120 +set_property -dict {PACKAGE_PIN AY42 } [get_ports c2m_p[14] ]; ## DP22_C2M_P Z4 MGTYTXP2_120 +set_property -dict {PACKAGE_PIN AY43 } [get_ports c2m_n[14] ]; ## DP22_C2M_N Z5 MGTYTXN2_120 +set_property -dict {PACKAGE_PIN BD42 } [get_ports c2m_p[12] ]; ## DP20_C2M_P Z8 MGTYTXP0_120 +set_property -dict {PACKAGE_PIN BD43 } [get_ports c2m_n[12] ]; ## DP20_C2M_N Z9 MGTYTXN0_120 +# +## Refernce clocks +# +set_property -dict {PACKAGE_PIN AK38 } [get_ports ref_clk_p[0] ]; ## GBTCLK0_M2C_P D4 MGTREFCLK0P_121 +set_property -dict {PACKAGE_PIN AK39 } [get_ports ref_clk_n[0] ]; ## GBTCLK0_M2C_N D5 MGTREFCLK0N_121 +set_property -dict {PACKAGE_PIN V38 } [get_ports ref_clk_replica_p ]; ## - - MGTREFCLK0P_126 +set_property -dict {PACKAGE_PIN V39 } [get_ports ref_clk_replica_n ]; ## - - MGTREFCLK0N_126 +set_property -dict {PACKAGE_PIN AM38 } [get_ports ref_clk_p[1] ]; ## GBTCLK1_M2C_P B20 MGTREFCLK1P_120,120,121,122,125,126,127 +set_property -dict {PACKAGE_PIN AM39 } [get_ports ref_clk_n[1] ]; ## GBTCLK1_M2C_N B21 MGTREFCLK1N_120,120,121,122,125,126,127 +set_property -dict {PACKAGE_PIN AN40 } [get_ports ref_clk_p[2] ]; ## GBTCLK5_M2C_P Z20 MGTREFCLK0P_120 +set_property -dict {PACKAGE_PIN AN41 } [get_ports ref_clk_n[2] ]; ## GBTCLK5_M2C_N Z21 MGTREFCLK0N_120 +# set_property -dict {PACKAGE_PIN AL32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports ref_clk_p[2] ]; ## CLK0_M2C_P H4 IO_L13P_T2L_N0_GC_QBC_43 +# set_property -dict {PACKAGE_PIN AM32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE} [get_ports ref_clk_n[2] ]; ## CLK0_M2C_N H5 IO_L13N_T2L_N1_GC_QBC_43 +## Sysref +set_property -dict {PACKAGE_PIN P35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports sysref_m2c_p ]; ## CLK1_M2C_P G2 IO_L14P_T2L_N2_GC_45 +set_property -dict {PACKAGE_PIN P36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports sysref_m2c_n ]; ## CLK1_M2C_N G3 IO_L14N_T2L_N3_GC_45 +## Apollo SPIs +set_property -dict {PACKAGE_PIN AL35 IOSTANDARD LVCMOS18 } [get_ports apollo_sclk ]; ## LA00_P_CC G6 IO_L7P_T1L_N0_QBC_AD13P_43 +set_property -dict {PACKAGE_PIN AL36 IOSTANDARD LVCMOS18 } [get_ports pdn_12v_pg ]; ## LA00_N_CC G7 IO_L7N_T1L_N1_QBC_AD13N_43 +set_property -dict {PACKAGE_PIN R34 IOSTANDARD LVCMOS18 } [get_ports clk_sdi ]; ## LA17_P_CC D20 IO_L13P_T2L_N0_GC_QBC_45 +# FIXME: Swapped with sdo because of the rework +set_property -dict {PACKAGE_PIN P34 IOSTANDARD LVCMOS18 } [get_ports clk_sclk ]; ## LA17_N_CC D21 IO_L13N_T2L_N1_GC_QBC_45 +set_property -dict {PACKAGE_PIN AJ32 IOSTANDARD LVCMOS18 } [get_ports apollo_sdi ]; ## LA02_P H7 IO_L14P_T2L_N2_GC_43 +set_property -dict {PACKAGE_PIN AK32 IOSTANDARD LVCMOS18 } [get_ports apollo_sdo ]; ## LA02_N H8 IO_L14N_T2L_N3_GC_43 +set_property -dict {PACKAGE_PIN N34 IOSTANDARD LVCMOS18 } [get_ports vddd_1p8_pg ]; ## LA22_P G24 IO_L20P_T3L_N2_AD1P_45 +set_property -dict {PACKAGE_PIN N35 IOSTANDARD LVCMOS18 } [get_ports vdda_1p8_pg ]; ## LA22_N G25 IO_L20N_T3L_N3_AD1N_45 +set_property -dict {PACKAGE_PIN AG32 IOSTANDARD LVCMOS18 } [get_ports apollo_csb[0] ]; ## LA15_P H19 IO_L24P_T3U_N10_43 +set_property -dict {PACKAGE_PIN AG33 IOSTANDARD LVCMOS18 } [get_ports apollo_csb[1] ]; ## LA15_N H20 IO_L24N_T3U_N11_43 +set_property -dict {PACKAGE_PIN N38 IOSTANDARD LVCMOS18 } [get_ports apollo_csb[2] ]; ## LA30_P H34 IO_L18P_T2U_N10_AD2P_45 +set_property -dict {PACKAGE_PIN M38 IOSTANDARD LVCMOS18 } [get_ports apollo_csb[3] ]; ## LA30_N H35 IO_L18N_T2U_N11_AD2N_45 +## ADF4382 +# FIXME: Swapped with sclk because of the rework +set_property -dict {PACKAGE_PIN R31 IOSTANDARD LVCMOS18 } [get_ports clk_sdo ]; ## LA18_P_CC C22 IO_L10P_T1U_N6_QBC_AD4P_45 +set_property -dict {PACKAGE_PIN P31 IOSTANDARD LVCMOS18 } [get_ports ext_trig ]; ## LA18_N_CC C23 IO_L10N_T1U_N7_QBC_AD4N_45 +set_property -dict {PACKAGE_PIN T34 IOSTANDARD LVCMOS18 } [get_ports art_csb[0] ]; ## LA24_P H28 IO_L6P_T0U_N10_AD6P_45 +set_property -dict {PACKAGE_PIN T35 IOSTANDARD LVCMOS18 } [get_ports art_csb[1] ]; ## LA24_N H29 IO_L6N_T0U_N11_AD6N_45 +set_property -dict {PACKAGE_PIN V32 IOSTANDARD LVCMOS18 } [get_ports art_csb[2] ]; ## LA26_P D26 IO_L2P_T0L_N2_45 +set_property -dict {PACKAGE_PIN U33 IOSTANDARD LVCMOS18 } [get_ports art_csb[3] ]; ## LA26_N D27 IO_L2N_T0L_N3_45 +## ADF4030 +# set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports adf4030_sclk ]; ## LA11_P H16 IO_L17P_T2U_N8_AD10P_43 +# set_property -dict {PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports adf4030_sdio ]; ## LA11_N H17 IO_L17N_T2U_N9_AD10N_43 +# set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports adf4030_csn ]; ## LA04_N H11 IO_L6N_T0U_N11_AD6N_43 +## LTC6952 +set_property -dict {PACKAGE_PIN AL30 IOSTANDARD LVCMOS18 } [get_ports art_5v_en ]; ## LA01_P_CC D8 IO_L16P_T2U_N6_QBC_AD3P_43 +set_property -dict {PACKAGE_PIN AL31 IOSTANDARD LVCMOS18 } [get_ports art_5v_pg ]; ## LA01_N_CC D9 IO_L16N_T2U_N7_QBC_AD3N_43 +set_property -dict {PACKAGE_PIN AP35 IOSTANDARD LVCMOS18 } [get_ports ltc6953_csn ]; ## LA10_P C14 IO_L3P_T0L_N4_AD15P_43 +set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18 } [get_ports ltc6952_csn ]; ## LA10_N C15 IO_L3N_T0L_N5_AD15N_43 +set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18 } [get_ports vco_csn ]; ## LA04_P H10 IO_L6P_T0U_N10_AD6P_43 +# ## HSCI +set_property -dict {PACKAGE_PIN P37 IOSTANDARD LVDS } [get_ports hsci_ckin_p[0] ]; ## LA31_P G33 IO_L16P_T2U_N6_QBC_AD3P_45 +set_property -dict {PACKAGE_PIN N37 IOSTANDARD LVDS } [get_ports hsci_ckin_n[0] ]; ## LA31_N G34 IO_L16N_T2U_N7_QBC_AD3N_45 +set_property -dict {PACKAGE_PIN L34 IOSTANDARD LVDS } [get_ports hsci_ckin_p[1] ]; ## LA33_P G36 IO_L19P_T3L_N0_DBC_AD9P_45 +set_property -dict {PACKAGE_PIN K34 IOSTANDARD LVDS } [get_ports hsci_ckin_n[1] ]; ## LA33_N G37 IO_L19N_T3L_N1_DBC_AD9N_45 +set_property -dict {PACKAGE_PIN AG34 IOSTANDARD LVDS } [get_ports hsci_ckin_p[2] ]; ## LA16_P G18 IO_L22P_T3U_N6_DBC_AD0P_43 +set_property -dict {PACKAGE_PIN AH35 IOSTANDARD LVDS } [get_ports hsci_ckin_n[2] ]; ## LA16_N G19 IO_L22N_T3U_N7_DBC_AD0N_43 +set_property -dict {PACKAGE_PIN AT39 IOSTANDARD LVDS } [get_ports hsci_ckin_p[3] ]; ## LA03_P G9 IO_L4P_T0U_N6_DBC_AD7P_43 +set_property -dict {PACKAGE_PIN AT40 IOSTANDARD LVDS } [get_ports hsci_ckin_n[3] ]; ## LA03_N G10 IO_L4N_T0U_N7_DBC_AD7N_43 +set_property -dict {PACKAGE_PIN M36 IOSTANDARD LVDS } [get_ports hsci_din_p[0] ]; ## LA28_P H31 IO_L17P_T2U_N8_AD10P_45 +set_property -dict {PACKAGE_PIN L36 IOSTANDARD LVDS } [get_ports hsci_din_n[0] ]; ## LA28_N H32 IO_L17N_T2U_N9_AD10N_45 +set_property -dict {PACKAGE_PIN L33 IOSTANDARD LVDS } [get_ports hsci_din_p[1] ]; ## LA32_P H37 IO_L21P_T3L_N4_AD8P_45 +set_property -dict {PACKAGE_PIN K33 IOSTANDARD LVDS } [get_ports hsci_din_n[1] ]; ## LA32_N H38 IO_L21N_T3L_N5_AD8N_45 +set_property -dict {PACKAGE_PIN AG31 IOSTANDARD LVDS } [get_ports hsci_din_p[2] ]; ## LA14_P C18 IO_L23P_T3U_N8_43 +set_property -dict {PACKAGE_PIN AH31 IOSTANDARD LVDS } [get_ports hsci_din_n[2] ]; ## LA14_N C19 IO_L23N_T3U_N9_43 +set_property -dict {PACKAGE_PIN AP36 IOSTANDARD LVDS } [get_ports hsci_din_p[3] ]; ## LA07_P H13 IO_L5P_T0U_N8_AD14P_43 +set_property -dict {PACKAGE_PIN AP37 IOSTANDARD LVDS } [get_ports hsci_din_n[3] ]; ## LA07_N H14 IO_L5N_T0U_N9_AD14N_43 +set_property -dict {PACKAGE_PIN N33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_p[0] ]; ## LA19_P H22 IO_L22P_T3U_N6_DBC_AD0P_45 +set_property -dict {PACKAGE_PIN M33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_n[0] ]; ## LA19_N H23 IO_L22N_T3U_N7_DBC_AD0N_45 +set_property -dict {PACKAGE_PIN U35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_p[1] ]; ## LA29_P G30 IO_L4P_T0U_N6_DBC_AD7P_45 +set_property -dict {PACKAGE_PIN T36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_n[1] ]; ## LA29_N G31 IO_L4N_T0U_N7_DBC_AD7N_45 +set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_p[2] ]; ## LA09_P D14 IO_L19P_T3L_N0_DBC_AD9P_43 +set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_n[2] ]; ## LA09_N D15 IO_L19N_T3L_N1_DBC_AD9N_43 +set_property -dict {PACKAGE_PIN AP38 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_p[3] ]; ## LA05_P D11 IO_L1P_T0L_N0_DBC_43 +set_property -dict {PACKAGE_PIN AR38 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_cko_n[3] ]; ## LA05_N D12 IO_L1N_T0L_N1_DBC_43 +set_property -dict {PACKAGE_PIN N32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_p[0] ]; ## LA20_P G21 IO_L23P_T3U_N8_45 +set_property -dict {PACKAGE_PIN M32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_n[0] ]; ## LA20_N G22 IO_L23N_T3U_N9_45 +set_property -dict {PACKAGE_PIN V34 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_n[1] ]; ## LA27_N C27 IO_L5P_T0U_N8_AD14P_45 +set_property -dict {PACKAGE_PIN V33 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_p[1] ]; ## LA27_P C26 IO_L5N_T0U_N9_AD14N_45 +set_property -dict {PACKAGE_PIN AJ35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_p[2] ]; ## LA13_P D17 IO_L20P_T3L_N2_AD1P_43 +set_property -dict {PACKAGE_PIN AJ36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_n[2] ]; ## LA13_N D18 IO_L20N_T3L_N3_AD1N_43 +set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_p[3] ]; ## LA06_P C10 IO_L2P_T0L_N2_43 +set_property -dict {PACKAGE_PIN AT36 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports hsci_do_n[3] ]; ## LA06_N C11 IO_L2N_T0L_N3_43 +## Trigger +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS18 } [get_ports trig0_a[0] ]; ## HA09_P E9 IO_L6P_T0U_N10_AD6P_70 +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS18 } [get_ports trig0_a[1] ]; ## HA16_P E15 IO_L11P_T1U_N8_GC_70 +set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS18 } [get_ports trig0_a[2] ]; ## HA08_P F10 IO_L10P_T1U_N6_QBC_AD4P_70 +set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS18 } [get_ports trig0_a[3] ]; ## HA15_P F16 IO_L19P_T3L_N0_DBC_AD9P_70 +set_property -dict {PACKAGE_PIN V14 IOSTANDARD LVCMOS18 } [get_ports trig1_a[0] ]; ## HA09_N E10 IO_L6N_T0U_N11_AD6N_70 +set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS18 } [get_ports trig1_a[1] ]; ## HA16_N E16 IO_L11N_T1U_N9_GC_70 +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS18 } [get_ports trig1_a[2] ]; ## HA08_N F11 IO_L10N_T1U_N7_QBC_AD4N_70 +set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18 } [get_ports trig1_a[3] ]; ## HA15_N F17 IO_L19N_T3L_N1_DBC_AD9N_70 +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS18 } [get_ports trig0_b[0] ]; ## HA13_P E12 IO_L4P_T0U_N6_DBC_AD7P_70 +set_property -dict {PACKAGE_PIN M15 IOSTANDARD LVCMOS18 } [get_ports trig0_b[1] ]; ## HA20_P E18 IO_L17P_T2U_N8_AD10P_70 +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS18 } [get_ports trig0_b[2] ]; ## HA12_P F13 IO_L9P_T1L_N4_AD12P_70 +set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS18 } [get_ports trig0_b[3] ]; ## HA19_P F19 IO_L20P_T3L_N2_AD1P_70 +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS18 } [get_ports trig1_b[0] ]; ## HA13_N E13 IO_L4N_T0U_N7_DBC_AD7N_70 +set_property -dict {PACKAGE_PIN L15 IOSTANDARD LVCMOS18 } [get_ports trig1_b[1] ]; ## HA20_N E19 IO_L17N_T2U_N9_AD10N_70 +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS18 } [get_ports trig1_b[2] ]; ## HA12_N F14 IO_L9N_T1L_N5_AD12N_70 +set_property -dict {PACKAGE_PIN L13 IOSTANDARD LVCMOS18 } [get_ports trig1_b[3] ]; ## HA19_N F20 IO_L20N_T3L_N3_AD1N_70 +## Reset +set_property -dict {PACKAGE_PIN Y32 IOSTANDARD LVCMOS18 } [get_ports resetb[0] ]; ## LA23_P D23 IO_L1P_T0L_N0_DBC_45 +set_property -dict {PACKAGE_PIN W32 IOSTANDARD LVCMOS18 } [get_ports resetb[1] ]; ## LA23_N D24 IO_L1N_T0L_N1_DBC_45 +set_property -dict {PACKAGE_PIN AH33 IOSTANDARD LVCMOS18 } [get_ports resetb[2] ]; ## LA12_P G15 IO_L21P_T3L_N4_AD8P_43 +set_property -dict {PACKAGE_PIN AH34 IOSTANDARD LVCMOS18 } [get_ports resetb[3] ]; ## LA12_N G16 IO_L21N_T3L_N5_AD8N_43 +## GPIO +set_property -dict {PACKAGE_PIN M35 IOSTANDARD LVCMOS18 } [get_ports txen[0] ]; ## LA21_P H25 IO_L24P_T3U_N10_45 +set_property -dict {PACKAGE_PIN L35 IOSTANDARD LVCMOS18 } [get_ports txen[1] ]; ## LA21_N H26 IO_L24N_T3U_N11_45 +set_property -dict {PACKAGE_PIN Y34 IOSTANDARD LVCMOS18 } [get_ports rxen[0] ]; ## LA25_P G27 IO_L3P_T0L_N4_AD15P_45 +set_property -dict {PACKAGE_PIN W34 IOSTANDARD LVCMOS18 } [get_ports rxen[1] ]; ## LA25_N G28 IO_L3N_T0L_N5_AD15N_45 +set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 } [get_ports irqa[0] ]; ## HA00_P_CC F4 IO_L13P_T2L_N0_GC_QBC_70 +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS18 } [get_ports irqa[1] ]; ## HA01_P_CC E2 IO_L7P_T1L_N0_QBC_AD13P_70 +set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS18 } [get_ports irqa[2] ]; ## HA04_P F7 IO_L1P_T0L_N0_DBC_70 +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS18 } [get_ports irqa[3] ]; ## HA05_P E6 IO_L14P_T2L_N2_GC_70 +set_property -dict {PACKAGE_PIN N13 IOSTANDARD LVCMOS18 } [get_ports irqb[0] ]; ## HA00_N_CC F5 IO_L13N_T2L_N1_GC_QBC_70 +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS18 } [get_ports irqb[1] ]; ## HA01_N_CC E3 IO_L7N_T1L_N1_QBC_AD13N_70 +set_property -dict {PACKAGE_PIN Y13 IOSTANDARD LVCMOS18 } [get_ports irqb[2] ]; ## HA04_N F8 IO_L1N_T0L_N1_DBC_70 +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS18 } [get_ports irqb[3] ]; ## HA05_N E7 IO_L14N_T2L_N3_GC_70 +set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 } [get_ports txrxn[0] ]; ## HA02_P K7 IO_L5P_T0U_N8_AD14P_70 +set_property -dict {PACKAGE_PIN Y12 IOSTANDARD LVCMOS18 } [get_ports txrxn[1] ]; ## HA02_N K8 IO_L5N_T0U_N9_AD14N_70 +set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS18 } [get_ports slice[0] ]; ## HA03_P J6 IO_L3P_T0L_N4_AD15P_70 +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS18 } [get_ports slice[1] ]; ## HA03_N J7 IO_L3N_T0L_N5_AD15N_70 +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS18 } [get_ports slice[2] ]; ## HA06_P K10 IO_L12P_T1U_N10_GC_70 +set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVCMOS18 } [get_ports txrxwe ]; ## HA06_N K11 IO_L12N_T1U_N11_GC_70 +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS18 } [get_ports fcnsel[0] ]; ## HA07_P J9 IO_L2P_T0L_N2_70 +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS18 } [get_ports fcnsel[1] ]; ## HA07_N J10 IO_L2N_T0L_N3_70 +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS18 } [get_ports fcnsel[2] ]; ## HA10_P K13 IO_L8P_T1L_N2_AD5P_70 +set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS18 } [get_ports profile[0] ]; ## HA10_N K14 IO_L8N_T1L_N3_AD5N_70 +set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS18 } [get_ports profile[1] ]; ## HA11_P J12 IO_L18P_T2U_N10_AD2P_70 +set_property -dict {PACKAGE_PIN P12 IOSTANDARD LVCMOS18 } [get_ports profile[2] ]; ## HA11_N J13 IO_L18N_T2U_N11_AD2N_70 +set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS18 } [get_ports profile[3] ]; ## HA17_P_CC K16 IO_L16P_T2U_N6_QBC_AD3P_70 +set_property -dict {PACKAGE_PIN P11 IOSTANDARD LVCMOS18 } [get_ports profile[4] ]; ## HA17_N_CC K17 IO_L16N_T2U_N7_QBC_AD3N_70 + +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS18 } [get_ports hpf_b[0] ]; ## LA08_P G12 IO_L18P_T2U_N10_AD2P_43 +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS18 } [get_ports hpf_b[1] ]; ## LA08_N G13 IO_L18N_T2U_N11_AD2N_43 +set_property -dict {PACKAGE_PIN M11 IOSTANDARD LVCMOS18 } [get_ports hpf_b[2] ]; ## HA14_P J15 IO_L22P_T3U_N6_DBC_AD0P_70 +set_property -dict {PACKAGE_PIN L11 IOSTANDARD LVCMOS18 } [get_ports hpf_b[3] ]; ## HA14_N J16 IO_L22N_T3U_N7_DBC_AD0N_70 +set_property -dict {PACKAGE_PIN K14 IOSTANDARD LVCMOS18 } [get_ports lpf_b[0] ]; ## HA21_P K19 IO_L23P_T3U_N8_70 +set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18 } [get_ports lpf_b[1] ]; ## HA21_N K20 IO_L23N_T3U_N9_70 +set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18 } [get_ports lpf_b[2] ]; ## HA22_P J21 IO_L24P_T3U_N10_70 +set_property -dict {PACKAGE_PIN J12 IOSTANDARD LVCMOS18 } [get_ports lpf_b[3] ]; ## HA22_N J22 IO_L24N_T3U_N11_70 +set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS18 } [get_ports admv8913_cs_n ]; ## HA18_N J19 IO_L15N_T2L_N5_AD11N_70 + +set_property -dict {PACKAGE_PIN AK29 IOSTANDARD LVCMOS18 } [get_ports hpf_b[0] ]; ## LA08_P G12 IO_L18P_T2U_N10_AD2P_43 +## Syncin +# set_property -dict {PACKAGE_PIN AN34 IOSTANDARD LVCMOS18 } [get_ports syncin_c2m_p ]; ## SYNC_C2M_P L16 IO_L8P_T1L_N2_AD5P_43 +# set_property -dict {PACKAGE_PIN AN35 IOSTANDARD LVCMOS18 } [get_ports syncin_c2m_n ]; ## SYNC_C2M_N L17 IO_L8N_T1L_N3_AD5N_43 +## RX_DSA +set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18 } [get_ports ad4030_csn ]; ## LA04_N H11 IO_L6N_T0U_N11_AD6N_43 +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS18 } [get_ports vneg_m1p0_pg ]; ## LA11_P H16 IO_L17P_T2U_N8_AD10P_43 +set_property -dict {PACKAGE_PIN AJ31 IOSTANDARD LVCMOS18 } [get_ports vdda_1p0_pg ]; ## LA11_N H17 IO_L17N_T2U_N9_AD10N_43 +set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18 } [get_ports clk_stat ]; ## HA23_P K22 IO_L21P_T3L_N4_AD8P_70 +set_property -dict {PACKAGE_PIN J11 IOSTANDARD LVCMOS18 } [get_ports art_stat ]; ## HA23_N K23 IO_L21N_T3L_N5_AD8N_70 +set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS18 } [get_ports vddd_0p8_pg ]; ## HA18_P J18 IO_L15P_T2L_N4_AD11P_70 +## FMC HPC Connections +# set_property -dict {PACKAGE_PIN AW10 IOSTANDARD LVCMOS18 } [get_ports syncin_a1_n ]; ## LA28_N H32 IO_L4N_T0U_N7_DBC_AD7N_67 +# set_property -dict {PACKAGE_PIN AV10 IOSTANDARD LVCMOS18 } [get_ports syncin_a1_p ]; ## LA28_P H31 IO_L4P_T0U_N6_DBC_AD7P_67 +# set_property -dict {PACKAGE_PIN AP15 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports syncout_b0_n ]; ## LA29_N G31 IO_L18N_T2U_N11_AD2N_67 +# set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 } [get_ports syncout_b1_p ]; ## LA30_P H34 IO_L21P_T3L_N4_AD8P_67 +# set_property -dict {PACKAGE_PIN AN15 IOSTANDARD LVCMOS18 } [get_ports syncout_b0_p[0] ]; ## LA29_P G30 IO_L18P_T2U_N10_AD2P_67 +# set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18 } [get_ports syncout_b1_n[0] ]; ## LA30_N H35 IO_L21N_T3L_N5_AD8N_67 +# set_property -dict {PACKAGE_PIN AM13 IOSTANDARD LVCMOS18 } [get_ports syncout_b0_p[1] ]; ## LA31_P G33 IO_L23P_T3U_N8_67 +# set_property -dict {PACKAGE_PIN AM12 IOSTANDARD LVCMOS18 } [get_ports syncout_b1_n[1] ]; ## LA31_N G34 IO_L23N_T3U_N9_67 +# set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS18 } [get_ports syncout_b0_p[2] ]; ## LA32_P H37 IO_L22P_T3U_N6_DBC_AD0P_67 +# set_property -dict {PACKAGE_PIN AJ12 IOSTANDARD LVCMOS18 } [get_ports syncout_b1_n[2] ]; ## LA32_N H38 IO_L22N_T3U_N7_DBC_AD0N_67 +# set_property -dict {PACKAGE_PIN AK14 IOSTANDARD LVCMOS18 } [get_ports syncout_b0_p[3] ]; ## LA33_P G36 IO_L24P_T3U_N10_67 +# set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS18 } [get_ports syncout_b1_n[3] ]; ## LA33_N G37 IO_L24N_T3U_N11_67 +set_property -dict {PACKAGE_PIN AU11 IOSTANDARD LVCMOS18 } [get_ports gp4[0] ]; ## LA21_P H25 IO_L6P_T0U_N10_AD6P_67 +set_property -dict {PACKAGE_PIN AV11 IOSTANDARD LVCMOS18 } [get_ports gp5[0] ]; ## LA21_N H26 IO_L6N_T0U_N11_AD6N_67 +set_property -dict {PACKAGE_PIN AW13 IOSTANDARD LVCMOS18 } [get_ports gp4[1] ]; ## LA22_P G24 IO_L5P_T0U_N8_AD14P_67 +set_property -dict {PACKAGE_PIN AY13 IOSTANDARD LVCMOS18 } [get_ports gp5[1] ]; ## LA22_N G25 IO_L5N_T0U_N9_AD14N_67 +set_property -dict {PACKAGE_PIN AP13 IOSTANDARD LVCMOS18 } [get_ports gp4[2] ]; ## LA24_P H28 IO_L14P_T2L_N2_GC_67 +set_property -dict {PACKAGE_PIN AR13 IOSTANDARD LVCMOS18 } [get_ports gp5[2] ]; ## LA24_N H29 IO_L14N_T2L_N3_GC_67 +set_property -dict {PACKAGE_PIN AT12 IOSTANDARD LVCMOS18 } [get_ports gp4[3] ]; ## LA25_P G27 IO_L1P_T0L_N0_DBC_67 +set_property -dict {PACKAGE_PIN AU12 IOSTANDARD LVCMOS18 } [get_ports gp5[3] ]; ## LA25_N G28 IO_L1N_T0L_N1_DBC_67 + +# PMOD0 connections (NCO Sync and DMA Sync Start signals) +set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS18 } [get_ports dma_start ]; ## PMOD0_0 J52.1 +set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS18 } [get_ports trig_request ]; ## PMOD0_1 J52.3 +set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS18 } [get_ports sync_start_debug ]; ## PMOD0_2 J52.5 +set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS18 } [get_ports apollo_trig_debug]; ## PMOD0_3 J52.7 +# set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS18 } [get_ports pmod0_4 ] ; ## PMOD0_4 J52.2 +# set_property -dict {PACKAGE_PIN AU16 IOSTANDARD LVCMOS18 } [get_ports pmod0_5 ] ; ## PMOD0_5 J52.4 +# set_property -dict {PACKAGE_PIN AT15 IOSTANDARD LVCMOS18 } [get_ports pmod0_6 ] ; ## PMOD0_6 J52.6 +# set_property -dict {PACKAGE_PIN AT16 IOSTANDARD LVCMOS18 } [get_ports pmod0_7 ] ; ## PMOD0_7 J52.8 + +# PMOD1 calibration board connector +set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS12 } [get_ports pmod1_adc_sync_n ]; ## PMOD1_0 J53.1 +set_property -dict {PACKAGE_PIN M30 IOSTANDARD LVCMOS12 } [get_ports pmod1_adc_sdi ]; ## PMOD1_1 J53.3 +set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS12 } [get_ports pmod1_adc_sdo ]; ## PMOD1_2 J53.5 +set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS12 } [get_ports pmod1_adc_sclk ]; ## PMOD1_3 J53.7 + +set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS12 } [get_ports pmod1_5045_v2 ]; ## PMOD1_4 J53.2 +set_property -dict {PACKAGE_PIN L31 IOSTANDARD LVCMOS12 } [get_ports pmod1_5045_v1 ]; ## PMOD1_5 J53.4 +set_property -dict {PACKAGE_PIN M31 IOSTANDARD LVCMOS12 } [get_ports pmod1_ctrl_ind ]; ## PMOD1_6 J53.6 +set_property -dict {PACKAGE_PIN R29 IOSTANDARD LVCMOS12 } [get_ports pmod1_ctrl_rx_combined ]; ## PMOD1_7 J53.8 + +set_false_path -through [get_nets -hierarchical -regexp .*IOBUFDS_inst/I.*] +set_false_path -through [get_nets -hierarchical -regexp .*IOBUFDS_inst/T.*] diff --git a/projects/ad_xband16_ebz/vcu118/system_project.tcl b/projects/ad_xband16_ebz/vcu118/system_project.tcl new file mode 100644 index 0000000000..a57da503a3 --- /dev/null +++ b/projects/ad_xband16_ebz/vcu118/system_project.tcl @@ -0,0 +1,110 @@ +############################################################################### +## Copyright (C) 2026 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source ../../../projects/scripts/adi_project_xilinx.tcl +source ../../../projects/scripts/adi_board.tcl +set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl] + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# ID=42 make JESD_MODE=64B66B RX_LANE_RATE=13.2 TX_LANE_RATE=13.2 RX_JESD_M=8 TX_JESD_M=8 RX_JESD_L=4 TX_JESD_L=4 RX_JESD_S=1 TX_JESD_S=1 RX_JESD_NP=16 TX_JESD_NP=16 RX_NUM_LINKS=4 TX_NUM_LINKS=4 +# ID=43 make JESD_MODE=64B66B RX_LANE_RATE=26.4 TX_LANE_RATE=26.4 RX_JESD_M=8 TX_JESD_M=8 RX_JESD_L=4 TX_JESD_L=4 RX_JESD_S=1 TX_JESD_S=1 RX_JESD_NP=16 TX_JESD_NP=16 RX_NUM_LINKS=4 TX_NUM_LINKS=4 + + +# +# Parameter description: +# MCS_MODE : Used for multiple boards synchronizations +# MASTER - Builds the master design that will generate the reference triggers for sync +# SLAVE - Builds the slave design that will receive the trigger +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C +# +# RX_LANE_RATE : Lane rate of the Rx link ( Apollo to FPGA ) +# TX_LANE_RATE : Lane rate of the Tx link ( FPGA to Apollo ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample +# [RX/TX]_NUM_LINKS : Number of links - This project has 4 Apollos so 4 is the defaul value +# [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) +# +set mcs_mode MASTER + +if {[info exists ::env(MCS_MODE)]} { + set mcs_mode $::env(MCS_MODE) +} else { + set env(MCS_MODE) $mcs_mode +} + +adi_project ad_xband16_ebz_vcu118 0 [list \ + MCS_MODE [get_env_param MCS_MODE $mcs_mode] \ + JESD_MODE [get_env_param JESD_MODE 64B66B] \ + RX_LANE_RATE [get_env_param RX_RATE 13.2 ] \ + TX_LANE_RATE [get_env_param TX_RATE 13.2 ] \ + RX_JESD_M [get_env_param RX_JESD_M 8 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 1 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 16 ] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 4 ] \ + TX_JESD_M [get_env_param TX_JESD_M 8 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 1 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 16 ] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 4 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 16 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 16 ] \ + DO_HAS_BYPASS [get_env_param DO_HAS_BYPASS 0 ] \ +] + +adi_project_files ad_xband16_ebz_vcu118 [list \ + "system_constr.xdc"\ + "timing_constr.xdc"\ + "../common/hsci_phy_top.sv"\ + "$ad_hdl_dir/library/common/ad_3w_spi.v" \ + "$ad_hdl_dir/library/common/ad_rst.v"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc"\ + "$ad_hdl_dir/projects/common/vcu118/vcu118_system_constr.xdc" ] + +set MCS_MODE [get_env_param MCS_MODE MASTER] + +switch $mcs_mode { + MASTER { + adi_project_files ad_xband16_ebz_vcu118 [list \ + "system_top_master.v" \ + ] + } + SLAVE { + adi_project_files ad_xband16_ebz_vcu118 [list \ + "system_top_slave.v" \ + ] + } +} + +create_ip -name high_speed_selectio_wiz -vendor xilinx.com -library ip -version 3.6 -module_name high_speed_selectio_wiz_0 +set_property -dict [list CONFIG.APPEND_PIN_NO {0} CONFIG.PLL_LOCS {PLL_X0Y12 PLL_X0Y13} CONFIG.BUS_DIR {3} CONFIG.FIFO_RD_EN_CONTROL {1} CONFIG.PLL0_DATA_SPEED {1600} CONFIG.PLL0_INPUT_CLK_FREQ {200.000} CONFIG.PLL0_RX_EXTERNAL_CLK_TO_DATA {3} CONFIG.PLL0_PLLOUT0 {200.000} CONFIG.RIU_FROM_PLL {1} CONFIG.ENABLE_PLL0_PLLOUT1 {1} CONFIG.PLL0_PLLOUT1 {100.000} CONFIG.PLL0_CLK_SOURCE {BUFG_TO_PLL} CONFIG.BANK {45_(HP)} CONFIG.DIFFERENTIAL_IO_STD {LVDS} CONFIG.SINGLE_IO_STD {LVCMOS18} CONFIG.TX_PRE_EMPHASIS_D {FALSE} CONFIG.ENABLE_N_PINS {0} CONFIG.BYTE0_PIN6_SIGNAL_NAME {clk_in_p_1} CONFIG.BYTE0_PIN7_SIGNAL_NAME {clk_in_n_1} CONFIG.BYTE0_PIN8_SIGNAL_NAME {data_in_p_1} CONFIG.BYTE0_PIN9_SIGNAL_NAME {data_in_n_1} CONFIG.BYTE0_PIN0_LOC {Y32} CONFIG.BYTE0_PIN1_LOC {W32} CONFIG.BYTE0_PIN2_LOC {V32} CONFIG.BYTE0_PIN3_LOC {U33} CONFIG.BYTE0_PIN4_LOC {Y34} CONFIG.BYTE0_PIN5_LOC {W34} CONFIG.BYTE0_PIN6_LOC {U35} CONFIG.BYTE0_PIN7_LOC {T36} CONFIG.BYTE0_PIN8_LOC {V33} CONFIG.BYTE0_PIN9_LOC {V34} CONFIG.BYTE0_PIN10_LOC {T34} CONFIG.BYTE0_PIN11_LOC {T35} CONFIG.BYTE0_PIN12_LOC {Y33} CONFIG.BYTE0_PIN0_NAME {IO_L1P_T0L_N0_DBC_45} CONFIG.BYTE0_PIN1_NAME {IO_L1N_T0L_N1_DBC_45} CONFIG.BYTE0_PIN2_NAME {IO_L2P_T0L_N2_45} CONFIG.BYTE0_PIN3_NAME {IO_L2N_T0L_N3_45} CONFIG.BYTE0_PIN4_NAME {IO_L3P_T0L_N4_AD15P_45} CONFIG.BYTE0_PIN5_NAME {IO_L3N_T0L_N5_AD15N_45} CONFIG.BYTE0_PIN6_NAME {IO_L4P_T0U_N6_DBC_AD7P_45} CONFIG.BYTE0_PIN7_NAME {IO_L4N_T0U_N7_DBC_AD7N_45} CONFIG.BYTE0_PIN8_NAME {IO_L5P_T0U_N8_AD14P_45} CONFIG.BYTE0_PIN9_NAME {IO_L5N_T0U_N9_AD14N_45} CONFIG.BYTE0_PIN10_NAME {IO_L6P_T0U_N10_AD6P_45} CONFIG.BYTE0_PIN11_NAME {IO_L6N_T0U_N11_AD6N_45} CONFIG.BYTE0_PIN12_NAME {IO_T0U_N12_VRP_45} CONFIG.BYTE0_PIN6_DATA_STROBE {Strobe} CONFIG.BYTE0_PIN7_DATA_STROBE {Strobe} CONFIG.BYTE0_PIN6_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN7_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN8_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN9_SIG_TYPE {DIFF} CONFIG.ENABLE_BYTE0_PIN6 {true} CONFIG.ENABLE_BYTE0_PIN7 {true} CONFIG.ENABLE_BYTE0_PIN8 {true} CONFIG.ENABLE_BYTE0_PIN9 {true} CONFIG.BYTE1_PIN0_LOC {T30} CONFIG.BYTE1_PIN1_LOC {T31} CONFIG.BYTE1_PIN2_LOC {U31} CONFIG.BYTE1_PIN3_LOC {U32} CONFIG.BYTE1_PIN4_LOC {Y31} CONFIG.BYTE1_PIN5_LOC {W31} CONFIG.BYTE1_PIN6_LOC {R31} CONFIG.BYTE1_PIN7_LOC {P31} CONFIG.BYTE1_PIN8_LOC {R32} CONFIG.BYTE1_PIN9_LOC {P32} CONFIG.BYTE1_PIN10_LOC {T33} CONFIG.BYTE1_PIN11_LOC {R33} CONFIG.BYTE1_PIN12_LOC {V30} CONFIG.BYTE1_PIN0_NAME {IO_L7P_T1L_N0_QBC_AD13P_45} CONFIG.BYTE1_PIN1_NAME {IO_L7N_T1L_N1_QBC_AD13N_45} CONFIG.BYTE1_PIN2_NAME {IO_L8P_T1L_N2_AD5P_45} CONFIG.BYTE1_PIN3_NAME {IO_L8N_T1L_N3_AD5N_45} CONFIG.BYTE1_PIN4_NAME {IO_L9P_T1L_N4_AD12P_45} CONFIG.BYTE1_PIN5_NAME {IO_L9N_T1L_N5_AD12N_45} CONFIG.BYTE1_PIN6_NAME {IO_L10P_T1U_N6_QBC_AD4P_45} CONFIG.BYTE1_PIN7_NAME {IO_L10N_T1U_N7_QBC_AD4N_45} CONFIG.BYTE1_PIN8_NAME {IO_L11P_T1U_N8_GC_45} CONFIG.BYTE1_PIN9_NAME {IO_L11N_T1U_N9_GC_45} CONFIG.BYTE1_PIN10_NAME {IO_L12P_T1U_N10_GC_45} CONFIG.BYTE1_PIN11_NAME {IO_L12N_T1U_N11_GC_45} CONFIG.BYTE1_PIN12_NAME {IO_T1U_N12_45} CONFIG.ENABLE_BYTE2_PIN0 {false} CONFIG.ENABLE_BYTE2_PIN6 {true} CONFIG.ENABLE_BYTE2_PIN7 {true} CONFIG.ENABLE_BYTE2_PIN8 {true} CONFIG.ENABLE_BYTE2_PIN9 {true} CONFIG.BYTE2_PIN6_BUS_DIR {TX} CONFIG.BYTE2_PIN7_BUS_DIR {TX} CONFIG.BYTE2_PIN8_BUS_DIR {TX} CONFIG.BYTE2_PIN9_BUS_DIR {TX} CONFIG.BYTE2_PIN6_SIG_TYPE {DIFF} CONFIG.BYTE2_PIN7_SIG_TYPE {DIFF} CONFIG.BYTE2_PIN8_SIG_TYPE {DIFF} CONFIG.BYTE2_PIN9_SIG_TYPE {DIFF} CONFIG.BYTE2_PIN0_DATA_STROBE {Data} CONFIG.BYTE2_PIN6_DATA_STROBE {Clk Fwd} CONFIG.BYTE2_PIN7_DATA_STROBE {Clk Fwd} CONFIG.BYTE2_PIN6_SIGNAL_NAME {clk_out_p_0} CONFIG.BYTE2_PIN7_SIGNAL_NAME {clk_out_n_0} CONFIG.BYTE2_PIN8_SIGNAL_NAME {data_out_p_0} CONFIG.BYTE2_PIN9_SIGNAL_NAME {data_out_n_0} CONFIG.BYTE2_PIN0_LOC {R34} CONFIG.BYTE2_PIN1_LOC {P34} CONFIG.BYTE2_PIN2_LOC {P35} CONFIG.BYTE2_PIN3_LOC {P36} CONFIG.BYTE2_PIN4_LOC {M37} CONFIG.BYTE2_PIN5_LOC {L38} CONFIG.BYTE2_PIN6_LOC {P37} CONFIG.BYTE2_PIN7_LOC {N37} CONFIG.BYTE2_PIN8_LOC {M36} CONFIG.BYTE2_PIN9_LOC {L36} CONFIG.BYTE2_PIN10_LOC {N38} CONFIG.BYTE2_PIN11_LOC {M38} CONFIG.BYTE2_PIN12_LOC {R36} CONFIG.BYTE2_PIN0_NAME {IO_L13P_T2L_N0_GC_QBC_45} CONFIG.BYTE2_PIN1_NAME {IO_L13N_T2L_N1_GC_QBC_45} CONFIG.BYTE2_PIN2_NAME {IO_L14P_T2L_N2_GC_45} CONFIG.BYTE2_PIN3_NAME {IO_L14N_T2L_N3_GC_45} CONFIG.BYTE2_PIN4_NAME {IO_L15P_T2L_N4_AD11P_45} CONFIG.BYTE2_PIN5_NAME {IO_L15N_T2L_N5_AD11N_45} CONFIG.BYTE2_PIN6_NAME {IO_L16P_T2U_N6_QBC_AD3P_45} CONFIG.BYTE2_PIN7_NAME {IO_L16N_T2U_N7_QBC_AD3N_45} CONFIG.BYTE2_PIN8_NAME {IO_L17P_T2U_N8_AD10P_45} CONFIG.BYTE2_PIN9_NAME {IO_L17N_T2U_N9_AD10N_45} CONFIG.BYTE2_PIN10_NAME {IO_L18P_T2U_N10_AD2P_45} CONFIG.BYTE2_PIN11_NAME {IO_L18N_T2U_N11_AD2N_45} CONFIG.BYTE2_PIN12_NAME {IO_T2U_N12_45} CONFIG.ENABLE_BYTE3_PIN0 {true} CONFIG.ENABLE_BYTE3_PIN1 {true} CONFIG.ENABLE_BYTE3_PIN4 {true} CONFIG.ENABLE_BYTE3_PIN5 {true} CONFIG.ENABLE_BYTE3_PIN6 {true} CONFIG.ENABLE_BYTE3_PIN7 {true} CONFIG.ENABLE_BYTE3_PIN8 {true} CONFIG.ENABLE_BYTE3_PIN9 {true} CONFIG.ENABLE_BYTE3_PIN12 {false} CONFIG.BYTE3_PIN0_BUS_DIR {TX} CONFIG.BYTE3_PIN1_BUS_DIR {TX} CONFIG.BYTE3_PIN4_BUS_DIR {TX} CONFIG.BYTE3_PIN5_BUS_DIR {TX} CONFIG.BYTE3_PIN0_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN1_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN4_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN5_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN6_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN7_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN8_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN9_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN0_DATA_STROBE {Clk Fwd} CONFIG.BYTE3_PIN1_DATA_STROBE {Clk Fwd} CONFIG.BYTE3_PIN6_DATA_STROBE {Strobe} CONFIG.BYTE3_PIN7_DATA_STROBE {Strobe} CONFIG.BYTE3_PIN0_SIGNAL_NAME {clk_out_p_1} CONFIG.BYTE3_PIN1_SIGNAL_NAME {clk_out_n_1} CONFIG.BYTE3_PIN4_SIGNAL_NAME {data_out_p_1} CONFIG.BYTE3_PIN5_SIGNAL_NAME {data_out_n_1} CONFIG.BYTE3_PIN6_SIGNAL_NAME {clk_in_p_0} CONFIG.BYTE3_PIN7_SIGNAL_NAME {clk_in_n_0} CONFIG.BYTE3_PIN8_SIGNAL_NAME {data_in_p_0} CONFIG.BYTE3_PIN9_SIGNAL_NAME {data_in_n_0} CONFIG.BYTE3_PIN0_LOC {L34} CONFIG.BYTE3_PIN1_LOC {K34} CONFIG.BYTE3_PIN2_LOC {N34} CONFIG.BYTE3_PIN3_LOC {N35} CONFIG.BYTE3_PIN4_LOC {L33} CONFIG.BYTE3_PIN5_LOC {K33} CONFIG.BYTE3_PIN6_LOC {N33} CONFIG.BYTE3_PIN7_LOC {M33} CONFIG.BYTE3_PIN8_LOC {N32} CONFIG.BYTE3_PIN9_LOC {M32} CONFIG.BYTE3_PIN10_LOC {M35} CONFIG.BYTE3_PIN11_LOC {L35} CONFIG.BYTE3_PIN12_LOC {K36} CONFIG.BYTE3_PIN0_NAME {IO_L19P_T3L_N0_DBC_AD9P_45} CONFIG.BYTE3_PIN1_NAME {IO_L19N_T3L_N1_DBC_AD9N_45} CONFIG.BYTE3_PIN2_NAME {IO_L20P_T3L_N2_AD1P_45} CONFIG.BYTE3_PIN3_NAME {IO_L20N_T3L_N3_AD1N_45} CONFIG.BYTE3_PIN4_NAME {IO_L21P_T3L_N4_AD8P_45} CONFIG.BYTE3_PIN5_NAME {IO_L21N_T3L_N5_AD8N_45} CONFIG.BYTE3_PIN6_NAME {IO_L22P_T3U_N6_DBC_AD0P_45} CONFIG.BYTE3_PIN7_NAME {IO_L22N_T3U_N7_DBC_AD0N_45} CONFIG.BYTE3_PIN8_NAME {IO_L23P_T3U_N8_45} CONFIG.BYTE3_PIN9_NAME {IO_L23N_T3U_N9_45} CONFIG.BYTE3_PIN10_NAME {IO_L24P_T3U_N10_45} CONFIG.BYTE3_PIN11_NAME {IO_L24N_T3U_N11_45} CONFIG.BYTE3_PIN12_NAME {IO_T3U_N12_45} CONFIG.BYTE2_PIN7_INIT {1} CONFIG.BYTE2_PIN9_INIT {1} CONFIG.BYTE3_PIN1_INIT {1} CONFIG.BYTE3_PIN5_INIT {1}] [get_ips high_speed_selectio_wiz_0] + +generate_target {instantiation_template} [get_files ./ad_xband16_ebz_vcu118.srcs/sources_1/ip/high_speed_selectio_wiz_0/high_speed_selectio_wiz_0.xci] +generate_target all [get_files ./ad_xband16_ebz_vcu118.srcs/sources_1/ip/high_speed_selectio_wiz_0/high_speed_selectio_wiz_0.xci] + +create_ip -name high_speed_selectio_wiz -vendor xilinx.com -library ip -version 3.6 -module_name high_speed_selectio_wiz_1 +set_property -dict [list CONFIG.APPEND_PIN_NO {0} CONFIG.PLL_LOCS {PLL_X0Y8 PLL_X0Y9} CONFIG.BUS_DIR {3} CONFIG.FIFO_RD_EN_CONTROL {1} CONFIG.PLL0_DATA_SPEED {1600} CONFIG.PLL0_INPUT_CLK_FREQ {200.000} CONFIG.PLL0_RX_EXTERNAL_CLK_TO_DATA {3} CONFIG.PLL0_PLLOUT0 {200.000} CONFIG.RIU_FROM_PLL {1} CONFIG.ENABLE_PLL0_PLLOUT1 {1} CONFIG.PLL0_PLLOUT1 {100.000} CONFIG.PLL0_CLK_SOURCE {BUFG_TO_PLL} CONFIG.BANK {43_(HP)} CONFIG.DIFFERENTIAL_IO_STD {LVDS} CONFIG.SINGLE_IO_STD {LVCMOS18} CONFIG.TX_PRE_EMPHASIS_D {FALSE} CONFIG.ENABLE_N_PINS {0} CONFIG.BYTE0_PIN0_SIGNAL_NAME {clk_in_p_3} CONFIG.BYTE0_PIN1_SIGNAL_NAME {clk_in_n_3} CONFIG.BYTE0_PIN2_SIGNAL_NAME {data_in_p_3} CONFIG.BYTE0_PIN3_SIGNAL_NAME {data_in_n_3} CONFIG.BYTE0_PIN6_SIGNAL_NAME {clk_out_p_3} CONFIG.BYTE0_PIN7_SIGNAL_NAME {clk_out_n_3} CONFIG.BYTE0_PIN8_SIGNAL_NAME {data_out_p_3} CONFIG.BYTE0_PIN9_SIGNAL_NAME {data_out_n_3} CONFIG.BYTE0_PIN0_LOC {AP38} CONFIG.BYTE0_PIN1_LOC {AR38} CONFIG.BYTE0_PIN2_LOC {AT35} CONFIG.BYTE0_PIN3_LOC {AT36} CONFIG.BYTE0_PIN4_LOC {AP35} CONFIG.BYTE0_PIN5_LOC {AR35} CONFIG.BYTE0_PIN6_LOC {AT39} CONFIG.BYTE0_PIN7_LOC {AT40} CONFIG.BYTE0_PIN8_LOC {AP36} CONFIG.BYTE0_PIN9_LOC {AP37} CONFIG.BYTE0_PIN10_LOC {AR37} CONFIG.BYTE0_PIN11_LOC {AT37} CONFIG.BYTE0_PIN12_LOC {AR34} CONFIG.BYTE0_PIN0_NAME {IO_L1P_T0L_N0_DBC_43} CONFIG.BYTE0_PIN1_NAME {IO_L1N_T0L_N1_DBC_43} CONFIG.BYTE0_PIN2_NAME {IO_L2P_T0L_N2_43} CONFIG.BYTE0_PIN3_NAME {IO_L2N_T0L_N3_43} CONFIG.BYTE0_PIN4_NAME {IO_L3P_T0L_N4_AD15P_43} CONFIG.BYTE0_PIN5_NAME {IO_L3N_T0L_N5_AD15N_43} CONFIG.BYTE0_PIN6_NAME {IO_L4P_T0U_N6_DBC_AD7P_43} CONFIG.BYTE0_PIN7_NAME {IO_L4N_T0U_N7_DBC_AD7N_43} CONFIG.BYTE0_PIN8_NAME {IO_L5P_T0U_N8_AD14P_43} CONFIG.BYTE0_PIN9_NAME {IO_L5N_T0U_N9_AD14N_43} CONFIG.BYTE0_PIN10_NAME {IO_L6P_T0U_N10_AD6P_43} CONFIG.BYTE0_PIN11_NAME {IO_L6N_T0U_N11_AD6N_43} CONFIG.BYTE0_PIN12_NAME {IO_T0U_N12_VRP_43} CONFIG.BYTE0_PIN6_BUS_DIR {TX} CONFIG.BYTE0_PIN7_BUS_DIR {TX} CONFIG.BYTE0_PIN8_BUS_DIR {TX} CONFIG.BYTE0_PIN9_BUS_DIR {TX} CONFIG.BYTE0_PIN0_DATA_STROBE {Strobe} CONFIG.BYTE0_PIN1_DATA_STROBE {Strobe} CONFIG.BYTE0_PIN6_DATA_STROBE {Clk Fwd} CONFIG.BYTE0_PIN7_DATA_STROBE {Clk Fwd} CONFIG.BYTE0_PIN0_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN1_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN2_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN3_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN6_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN7_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN8_SIG_TYPE {DIFF} CONFIG.BYTE0_PIN9_SIG_TYPE {DIFF} CONFIG.ENABLE_BYTE0_PIN0 {true} CONFIG.ENABLE_BYTE0_PIN1 {true} CONFIG.ENABLE_BYTE0_PIN2 {true} CONFIG.ENABLE_BYTE0_PIN3 {true} CONFIG.ENABLE_BYTE0_PIN6 {true} CONFIG.ENABLE_BYTE0_PIN7 {true} CONFIG.ENABLE_BYTE0_PIN8 {true} CONFIG.ENABLE_BYTE0_PIN9 {true} CONFIG.BYTE1_PIN0_LOC {AL35} CONFIG.BYTE1_PIN1_LOC {AL36} CONFIG.BYTE1_PIN2_LOC {AN34} CONFIG.BYTE1_PIN3_LOC {AN35} CONFIG.BYTE1_PIN4_LOC {AM36} CONFIG.BYTE1_PIN5_LOC {AN36} CONFIG.BYTE1_PIN6_LOC {AN33} CONFIG.BYTE1_PIN7_LOC {AP33} CONFIG.BYTE1_PIN8_LOC {AK34} CONFIG.BYTE1_PIN9_LOC {AL34} CONFIG.BYTE1_PIN10_LOC {AM33} CONFIG.BYTE1_PIN11_LOC {AM34} CONFIG.BYTE1_PIN12_LOC {AK35} CONFIG.BYTE1_PIN0_NAME {IO_L7P_T1L_N0_QBC_AD13P_43} CONFIG.BYTE1_PIN1_NAME {IO_L7N_T1L_N1_QBC_AD13N_43} CONFIG.BYTE1_PIN2_NAME {IO_L8P_T1L_N2_AD5P_43} CONFIG.BYTE1_PIN3_NAME {IO_L8N_T1L_N3_AD5N_43} CONFIG.BYTE1_PIN4_NAME {IO_L9P_T1L_N4_AD12P_43} CONFIG.BYTE1_PIN5_NAME {IO_L9N_T1L_N5_AD12N_43} CONFIG.BYTE1_PIN6_NAME {IO_L10P_T1U_N6_QBC_AD4P_43} CONFIG.BYTE1_PIN7_NAME {IO_L10N_T1U_N7_QBC_AD4N_43} CONFIG.BYTE1_PIN8_NAME {IO_L11P_T1U_N8_GC_43} CONFIG.BYTE1_PIN9_NAME {IO_L11N_T1U_N9_GC_43} CONFIG.BYTE1_PIN10_NAME {IO_L12P_T1U_N10_GC_43} CONFIG.BYTE1_PIN11_NAME {IO_L12N_T1U_N11_GC_43} CONFIG.BYTE1_PIN12_NAME {IO_T1U_N12_43} CONFIG.ENABLE_BYTE2_PIN0 {false} CONFIG.BYTE2_PIN0_DATA_STROBE {Data} CONFIG.BYTE2_PIN0_LOC {AL32} CONFIG.BYTE2_PIN1_LOC {AM32} CONFIG.BYTE2_PIN2_LOC {AJ32} CONFIG.BYTE2_PIN3_LOC {AK32} CONFIG.BYTE2_PIN4_LOC {AL29} CONFIG.BYTE2_PIN5_LOC {AM29} CONFIG.BYTE2_PIN6_LOC {AL30} CONFIG.BYTE2_PIN7_LOC {AL31} CONFIG.BYTE2_PIN8_LOC {AJ30} CONFIG.BYTE2_PIN9_LOC {AJ31} CONFIG.BYTE2_PIN10_LOC {AK29} CONFIG.BYTE2_PIN11_LOC {AK30} CONFIG.BYTE2_PIN12_LOC {AM31} CONFIG.BYTE2_PIN0_NAME {IO_L13P_T2L_N0_GC_QBC_43} CONFIG.BYTE2_PIN1_NAME {IO_L13N_T2L_N1_GC_QBC_43} CONFIG.BYTE2_PIN2_NAME {IO_L14P_T2L_N2_GC_43} CONFIG.BYTE2_PIN3_NAME {IO_L14N_T2L_N3_GC_43} CONFIG.BYTE2_PIN4_NAME {IO_L15P_T2L_N4_AD11P_43} CONFIG.BYTE2_PIN5_NAME {IO_L15N_T2L_N5_AD11N_43} CONFIG.BYTE2_PIN6_NAME {IO_L16P_T2U_N6_QBC_AD3P_43} CONFIG.BYTE2_PIN7_NAME {IO_L16N_T2U_N7_QBC_AD3N_43} CONFIG.BYTE2_PIN8_NAME {IO_L17P_T2U_N8_AD10P_43} CONFIG.BYTE2_PIN9_NAME {IO_L17N_T2U_N9_AD10N_43} CONFIG.BYTE2_PIN10_NAME {IO_L18P_T2U_N10_AD2P_43} CONFIG.BYTE2_PIN11_NAME {IO_L18N_T2U_N11_AD2N_43} CONFIG.BYTE2_PIN12_NAME {IO_T2U_N12_43} CONFIG.ENABLE_BYTE3_PIN0 {true} CONFIG.ENABLE_BYTE3_PIN1 {true} CONFIG.ENABLE_BYTE3_PIN2 {true} CONFIG.ENABLE_BYTE3_PIN3 {true} CONFIG.ENABLE_BYTE3_PIN6 {true} CONFIG.ENABLE_BYTE3_PIN7 {true} CONFIG.ENABLE_BYTE3_PIN8 {true} CONFIG.ENABLE_BYTE3_PIN9 {true} CONFIG.ENABLE_BYTE3_PIN12 {false} CONFIG.BYTE3_PIN6_BUS_DIR {TX} CONFIG.BYTE3_PIN7_BUS_DIR {TX} CONFIG.BYTE3_PIN8_BUS_DIR {TX} CONFIG.BYTE3_PIN9_BUS_DIR {TX} CONFIG.BYTE3_PIN0_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN1_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN2_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN3_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN6_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN7_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN8_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN9_SIG_TYPE {DIFF} CONFIG.BYTE3_PIN0_DATA_STROBE {Strobe} CONFIG.BYTE3_PIN1_DATA_STROBE {Strobe} CONFIG.BYTE3_PIN6_DATA_STROBE {Clk Fwd} CONFIG.BYTE3_PIN7_DATA_STROBE {Clk Fwd} CONFIG.BYTE3_PIN0_SIGNAL_NAME {clk_in_p_2} CONFIG.BYTE3_PIN1_SIGNAL_NAME {clk_in_n_2} CONFIG.BYTE3_PIN2_SIGNAL_NAME {data_in_p_2} CONFIG.BYTE3_PIN3_SIGNAL_NAME {data_in_n_2} CONFIG.BYTE3_PIN6_SIGNAL_NAME {clk_out_p_2} CONFIG.BYTE3_PIN7_SIGNAL_NAME {clk_out_n_2} CONFIG.BYTE3_PIN8_SIGNAL_NAME {data_out_p_2} CONFIG.BYTE3_PIN9_SIGNAL_NAME {data_out_n_2} CONFIG.BYTE3_PIN0_LOC {AJ33} CONFIG.BYTE3_PIN1_LOC {AK33} CONFIG.BYTE3_PIN2_LOC {AJ35} CONFIG.BYTE3_PIN3_LOC {AJ36} CONFIG.BYTE3_PIN4_LOC {AH33} CONFIG.BYTE3_PIN5_LOC {AH34} CONFIG.BYTE3_PIN6_LOC {AG34} CONFIG.BYTE3_PIN7_LOC {AH35} CONFIG.BYTE3_PIN8_LOC {AG31} CONFIG.BYTE3_PIN9_LOC {AH31} CONFIG.BYTE3_PIN10_LOC {AG32} CONFIG.BYTE3_PIN11_LOC {AG33} CONFIG.BYTE3_PIN12_LOC {AH30} CONFIG.BYTE3_PIN0_NAME {IO_L19P_T3L_N0_DBC_AD9P_43} CONFIG.BYTE3_PIN1_NAME {IO_L19N_T3L_N1_DBC_AD9N_43} CONFIG.BYTE3_PIN2_NAME {IO_L20P_T3L_N2_AD1P_43} CONFIG.BYTE3_PIN3_NAME {IO_L20N_T3L_N3_AD1N_43} CONFIG.BYTE3_PIN4_NAME {IO_L21P_T3L_N4_AD8P_43} CONFIG.BYTE3_PIN5_NAME {IO_L21N_T3L_N5_AD8N_43} CONFIG.BYTE3_PIN6_NAME {IO_L22P_T3U_N6_DBC_AD0P_43} CONFIG.BYTE3_PIN7_NAME {IO_L22N_T3U_N7_DBC_AD0N_43} CONFIG.BYTE3_PIN8_NAME {IO_L23P_T3U_N8_43} CONFIG.BYTE3_PIN9_NAME {IO_L23N_T3U_N9_43} CONFIG.BYTE3_PIN10_NAME {IO_L24P_T3U_N10_43} CONFIG.BYTE3_PIN11_NAME {IO_L24N_T3U_N11_43} CONFIG.BYTE3_PIN12_NAME {IO_T3U_N12_43} CONFIG.BYTE0_PIN7_INIT {1} CONFIG.BYTE0_PIN9_INIT {1} CONFIG.BYTE3_PIN7_INIT {1} CONFIG.BYTE3_PIN9_INIT {1}] [get_ips high_speed_selectio_wiz_1] + +generate_target {instantiation_template} [get_files ./ad_xband16_ebz_vcu118.srcs/sources_1/ip/high_speed_selectio_wiz_1/high_speed_selectio_wiz_1.xci] +generate_target all [get_files ./ad_xband16_ebz_vcu118.srcs/sources_1/ip/high_speed_selectio_wiz_1/high_speed_selectio_wiz_1.xci] + +# Avoid critical warning in OOC mode from the clock definitions +# since at that stage the submodules are not stiched together yet +if {$ADI_USE_OOC_SYNTHESIS == 1} { + set_property used_in_synthesis false [get_files timing_constr.xdc] +} + +set_property strategy Congestion_SpreadLogic_high [get_runs impl_1] + +adi_project_run ad_xband16_ebz_vcu118 diff --git a/projects/ad_xband16_ebz/vcu118/system_top_master.v b/projects/ad_xband16_ebz/vcu118/system_top_master.v new file mode 100644 index 0000000000..1370dad44c --- /dev/null +++ b/projects/ad_xband16_ebz/vcu118/system_top_master.v @@ -0,0 +1,591 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2026 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + input uart_sin, + output uart_sout, + + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, + + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, + + inout [16:0] gpio_bd, + + output iic_rstn, + inout iic_scl, + inout iic_sda, + + input vadj_1v8_pgood, + + // FMCp IOs + input [15:0] m2c_p, + input [15:0] m2c_n, + output [15:0] c2m_p, + output [15:0] c2m_n, + + input [2:0] ref_clk_p, + input [2:0] ref_clk_n, + input ref_clk_replica_p, + input ref_clk_replica_n, + + inout sysref_m2c_p, + inout sysref_m2c_n, + + output apollo_sclk, + input apollo_sdo, + output apollo_sdi, + output [3:0] apollo_csb, + + output clk_sclk, + input clk_sdo, + output clk_sdi, + input clk_stat, + + output art_5v_en, + input art_5v_pg, + output [3:0] art_csb, + input art_stat, + + output ltc6953_csn, + output ltc6952_csn, + output ad4030_csn, + output vco_csn, + + output [3:0] hsci_ckin_p, + output [3:0] hsci_ckin_n, + output [3:0] hsci_din_p, + output [3:0] hsci_din_n, + input [3:0] hsci_cko_p, + input [3:0] hsci_cko_n, + input [3:0] hsci_do_p, + input [3:0] hsci_do_n, + + input ext_trig, + + output [3:0] trig0_a, + output [3:0] trig1_a, + output [3:0] trig0_b, + output [3:0] trig1_b, + + output [3:0] resetb, + output [1:0] txen, + output [1:0] rxen, + input [3:0] irqa, + input [3:0] irqb, + output [1:0] txrxn, + output [2:0] slice, + output txrxwe, + output [2:0] fcnsel, + output [4:0] profile, + + output [3:0] hpf_b, + output [3:0] lpf_b, + output admv8913_cs_n, + + input pdn_12v_pg, + input vddd_0p8_pg, + input vdda_1p0_pg, + input vddd_1p8_pg, + input vdda_1p8_pg, + input vneg_m1p0_pg, + + inout [3:0] gp4, + inout [3:0] gp5, + + // PMOD0 for MCS cotrol + output dma_start, + output trig_request, + output sync_start_debug, + output apollo_trig_debug, + + // PMOD1 for calibration board + output pmod1_adc_sync_n, + output pmod1_adc_sdi, + input pmod1_adc_sdo, + output pmod1_adc_sclk, + + output pmod1_5045_v2, + output pmod1_5045_v1, + output pmod1_ctrl_ind, + output pmod1_ctrl_rx_combined +); + + // internal signals + wire [127:0] gpio_i; + wire [127:0] gpio_o; + wire [127:0] gpio_t; + + wire spi_2_clk; + wire [ 7:0] spi_2_csn; + wire spi_2_mosi; + wire spi_2_miso; + + wire spi_3_clk; + wire [ 7:0] spi_3_csn; + wire spi_3_mosi; + wire spi_3_miso; + + wire ref_clk; + wire ref_clk_replica; + wire sysref; + wire [3:0] link0_tx_syncin; + wire [3:0] link0_rx_syncout; + + wire clkin0; + wire clkin1; + wire rx_device_clk; + wire tx_device_clk; + + wire pll_inclk; + wire [ 0:1] hsci_pll_reset; + wire [ 0:1] hsci_pclk; + wire [ 0:1] hsci_pll_locked; + wire [ 0:3] hsci_vtc_rdy_bsc_tx; + wire [ 0:3] hsci_dly_rdy_bsc_tx; + wire [ 0:3] hsci_vtc_rdy_bsc_rx; + wire [ 0:3] hsci_dly_rdy_bsc_rx; + wire [ 0:1] hsci_rst_seq_done; + + wire selectio_clk_in; + wire [ 7:0] hsci_menc_clk [0:3]; + wire [ 7:0] hsci_data_in [0:3]; + wire [ 7:0] hsci_data_out [0:3]; + + wire [ 4:0] trig_channel; + wire trigger_captured; + wire sync_start; + wire sync_start_edge; + + reg trigger_stretched = 1'b0; + reg trigger_sync1 = 1'b0; + reg trigger_sync2 = 1'b0; + + assign iic_rstn = 1'b1; + + // instantiations + IBUFDS_GTE4 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (ref_clk_p[0]), + .IB (ref_clk_n[0]), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS_GTE4 i_ibufds_ref_clk_replica ( + .CEB (1'd0), + .I (ref_clk_replica_p), + .IB (ref_clk_replica_n), + .O (ref_clk_replica), + .ODIV2 ()); + + IBUFDS_GTE4 i_ibufds_tx_device_clk ( + .I (ref_clk_p[1]), + .IB (ref_clk_n[1]), + .CEB(1'b0), + .ODIV2 (clkin0)); + + IBUFDS_GTE4 i_ibufds_rx_device_clk ( + .I (ref_clk_p[2]), + .IB (ref_clk_n[2]), + .CEB(1'b0), + .ODIV2 (clkin1)); + + BUFG_GT i_tx_device_clk ( + .I (clkin0), + .O (tx_device_clk)); + + BUFG_GT i_rx_device_clk ( + .I (clkin1), + .O (rx_device_clk)); + + // spi + assign art_csb = spi_2_csn[3:0]; + assign ad4030_csn = spi_2_csn[4]; + assign vco_csn = spi_2_csn[5]; + assign ltc6952_csn = spi_2_csn[6]; + assign ltc6953_csn = spi_2_csn[7]; + assign clk_sclk = spi_2_clk; + + assign pmod1_adc_sync_n = spi_3_csn[0]; + assign pmod1_adc_sdi = spi_3_mosi; + assign pmod1_adc_sclk = spi_3_clk; + + assign spi_3_miso = ~pmod1_adc_sync_n ? pmod1_adc_sdo : 1'b0; + + // gpios + ad_iobuf #( + .DATA_WIDTH(8) + ) i_iobuf ( + .dio_t (gpio_t[39:32]), + .dio_i (gpio_o[39:32]), + .dio_o (gpio_i[39:32]), + .dio_p ({gp5[3:0], // 39-36 + gp4[3:0]})); // 35-32 + + assign gpio_i[43:40] = irqa; + assign gpio_i[47:44] = irqb; + + assign trig0_a = {4{trig_channel[0]}}; + assign trig1_a = {4{trig_channel[1]}}; + assign trig0_b = {4{trig_channel[2]}}; + assign trig1_b = {4{trig_channel[3]}}; + assign dma_start = trig_channel[4]; + assign resetb = gpio_o[67:64]; + assign txen = gpio_o[69:68]; + assign rxen = gpio_o[71:70]; + assign txrxn = gpio_o[73:72]; + assign slice = gpio_o[76:74]; + assign txrxwe = gpio_o[77]; + assign fcnsel = gpio_o[80:78]; + assign profile = gpio_o[85:81]; + assign hpf_b = gpio_o[89:86]; + assign lpf_b = gpio_o[93:90]; + assign admv8913_cs_n = gpio_o[94]; + assign art_5v_en = gpio_o[95]; + assign pmod1_5045_v2 = gpio_o[96]; + assign pmod1_5045_v1 = gpio_o[97]; + assign pmod1_ctrl_ind = gpio_o[98]; + assign pmod1_ctrl_rx_combined = gpio_o[99]; + assign apollo_trig_debug = trig_channel[0]; + + assign gpio_i[100] = pdn_12v_pg; + assign gpio_i[101] = vddd_0p8_pg; + assign gpio_i[102] = vdda_1p0_pg; + assign gpio_i[103] = vddd_1p8_pg; + assign gpio_i[104] = vdda_1p8_pg; + assign gpio_i[105] = vneg_m1p0_pg; + assign gpio_i[106] = art_5v_pg; + assign gpio_i[107] = art_stat; + assign gpio_i[108] = clk_stat; + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf_bd ( + .dio_t (gpio_t[16:0]), + .dio_i (gpio_o[16:0]), + .dio_o (gpio_i[16:0]), + .dio_p (gpio_bd)); + + assign gpio_i[127:109] = gpio_o[127:109]; + assign gpio_i[ 31:17] = gpio_o[ 31:17]; + + always @(posedge dma_start or posedge trigger_captured) begin + if (trigger_captured) + trigger_stretched <= 1'b0; + else + trigger_stretched <= 1'b1; + end + + always @(posedge sysref) begin + trigger_sync1 <= trigger_stretched; + trigger_sync2 <= trigger_sync1; + end + + assign trigger_captured = trigger_sync2; + + assign sync_start_edge = trigger_sync1 & ~trigger_sync2; + assign sync_start = sync_start_edge & sysref; + assign sync_start_debug = sync_start; + + hsci_phy_top hsci_phy_top( + .pll_inclk (selectio_clk_in), + .hsci_pll_reset (hsci_pll_reset), + + .hsci_pclk (hsci_pclk), + .hsci_mosi_d_p (hsci_din_p), + .hsci_mosi_d_n (hsci_din_n), + + .hsci_miso_d_p (hsci_do_p), + .hsci_miso_d_n (hsci_do_n), + + .hsci_pll_locked (hsci_pll_locked), + + .hsci_mosi_clk_p (hsci_ckin_p), + .hsci_mosi_clk_n (hsci_ckin_n), + + .hsci_miso_clk_p (hsci_cko_p), + .hsci_miso_clk_n (hsci_cko_n), + + .hsci_menc_clk_0 (hsci_menc_clk[0]), + .hsci_menc_clk_1 (hsci_menc_clk[1]), + .hsci_menc_clk_2 (hsci_menc_clk[2]), + .hsci_menc_clk_3 (hsci_menc_clk[3]), + + .hsci_mosi_data_0 (hsci_data_out[0]), + .hsci_mosi_data_1 (hsci_data_out[1]), + .hsci_mosi_data_2 (hsci_data_out[2]), + .hsci_mosi_data_3 (hsci_data_out[3]), + + .hsci_miso_data_0 (hsci_data_in[0]), + .hsci_miso_data_1 (hsci_data_in[1]), + .hsci_miso_data_2 (hsci_data_in[2]), + .hsci_miso_data_3 (hsci_data_in[3]), + + .vtc_rdy_bsc_tx (hsci_vtc_rdy_bsc_tx), + .dly_rdy_bsc_tx (hsci_dly_rdy_bsc_tx), + .vtc_rdy_bsc_rx (hsci_vtc_rdy_bsc_rx), + .dly_rdy_bsc_rx (hsci_dly_rdy_bsc_rx), + .rst_seq_done (hsci_rst_seq_done) + ); + + system_wrapper i_system_wrapper ( + .sys_rst (sys_rst), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .ddr4_act_n (ddr4_act_n), + .ddr4_adr (ddr4_addr), + .ddr4_ba (ddr4_ba), + .ddr4_bg (ddr4_bg), + .ddr4_ck_c (ddr4_ck_n), + .ddr4_ck_t (ddr4_ck_p), + .ddr4_cke (ddr4_cke), + .ddr4_cs_n (ddr4_cs_n), + .ddr4_dm_n (ddr4_dm_n), + .ddr4_dq (ddr4_dq), + .ddr4_dqs_c (ddr4_dqs_n), + .ddr4_dqs_t (ddr4_dqs_p), + .ddr4_odt (ddr4_odt), + .ddr4_reset_n (ddr4_reset_n), + .phy_sd (1'b1), + .phy_rst_n (phy_rst_n), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .sgmii_phyclk_clk_n (phy_clk_n), + .sgmii_phyclk_clk_p (phy_clk_p), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .uart_sin (uart_sin), + .uart_sout (uart_sout), + .spi_clk_i (apollo_sclk), + .spi_clk_o (apollo_sclk), + .spi_csn_i (apollo_csb), + .spi_csn_o (apollo_csb), + .spi_sdi_i (apollo_sdo), + .spi_sdo_i (apollo_sdi), + .spi_sdo_o (apollo_sdi), + + .spi_2_clk_i (spi_2_clk), + .spi_2_clk_o (spi_2_clk), + .spi_2_csn_i (spi_2_csn), + .spi_2_csn_o (spi_2_csn), + .spi_2_sdi_i (clk_sdo), + .spi_2_sdo_i (clk_sdi), + .spi_2_sdo_o (clk_sdi), + + .spi_3_clk_i (spi_3_clk), + .spi_3_clk_o (spi_3_clk), + .spi_3_csn_i (spi_3_csn), + .spi_3_csn_o (spi_3_csn), + .spi_3_sdi_i (spi_3_miso), + .spi_3_sdo_i (spi_3_mosi), + .spi_3_sdo_o (spi_3_mosi), + + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + + .gpio2_i (gpio_i[95:64]), + .gpio2_o (gpio_o[95:64]), + .gpio2_t (gpio_t[95:64]), + .gpio3_i (gpio_i[127:96]), + .gpio3_o (gpio_o[127:96]), + .gpio3_t (gpio_t[127:96]), + // FMCp + // quad 127 + .rx_data_0_n (m2c_n[3]), + .rx_data_0_p (m2c_p[3]), + .rx_data_1_n (m2c_n[2]), + .rx_data_1_p (m2c_p[2]), + .rx_data_2_n (m2c_n[1]), + .rx_data_2_p (m2c_p[1]), + .rx_data_3_n (m2c_n[0]), + .rx_data_3_p (m2c_p[0]), + // quad 125 + .rx_data_4_n (m2c_n[7]), + .rx_data_4_p (m2c_p[7]), + .rx_data_5_n (m2c_n[6]), + .rx_data_5_p (m2c_p[6]), + .rx_data_6_n (m2c_n[5]), + .rx_data_6_p (m2c_p[5]), + .rx_data_7_n (m2c_n[4]), + .rx_data_7_p (m2c_p[4]), + // quad 122 + .rx_data_8_n (m2c_n[10]), + .rx_data_8_p (m2c_p[10]), + .rx_data_9_n (m2c_n[11]), + .rx_data_9_p (m2c_p[11]), + .rx_data_10_n (m2c_n[9]), + .rx_data_10_p (m2c_p[9]), + .rx_data_11_n (m2c_n[8]), + .rx_data_11_p (m2c_p[8]), + // quad 120 + .rx_data_12_n (m2c_n[12]), + .rx_data_12_p (m2c_p[12]), + .rx_data_13_n (m2c_n[13]), + .rx_data_13_p (m2c_p[13]), + .rx_data_14_n (m2c_n[14]), + .rx_data_14_p (m2c_p[14]), + .rx_data_15_n (m2c_n[15]), + .rx_data_15_p (m2c_p[15]), + // quad 127 + .tx_data_0_n (c2m_n[3]), + .tx_data_0_p (c2m_p[3]), + .tx_data_1_n (c2m_n[2]), + .tx_data_1_p (c2m_p[2]), + .tx_data_2_n (c2m_n[1]), + .tx_data_2_p (c2m_p[1]), + .tx_data_3_n (c2m_n[0]), + .tx_data_3_p (c2m_p[0]), + // quad 125 + .tx_data_4_n (c2m_n[5]), + .tx_data_4_p (c2m_p[5]), + .tx_data_5_n (c2m_n[4]), + .tx_data_5_p (c2m_p[4]), + .tx_data_6_n (c2m_n[7]), + .tx_data_6_p (c2m_p[7]), + .tx_data_7_n (c2m_n[6]), + .tx_data_7_p (c2m_p[6]), + // quad 122 + .tx_data_8_n (c2m_n[8]), + .tx_data_8_p (c2m_p[8]), + .tx_data_9_n (c2m_n[11]), + .tx_data_9_p (c2m_p[11]), + .tx_data_10_n (c2m_n[10]), + .tx_data_10_p (c2m_p[10]), + .tx_data_11_n (c2m_n[9]), + .tx_data_11_p (c2m_p[9]), + // quad 120 + .tx_data_12_n (c2m_n[12]), + .tx_data_12_p (c2m_p[12]), + .tx_data_13_n (c2m_n[13]), + .tx_data_13_p (c2m_p[13]), + .tx_data_14_n (c2m_n[14]), + .tx_data_14_p (c2m_p[14]), + .tx_data_15_n (c2m_n[15]), + .tx_data_15_p (c2m_p[15]), + + .selectio_clk_in (selectio_clk_in), + + .hsci_menc_clk_0 (hsci_menc_clk[0]), + .hsci_menc_clk_1 (hsci_menc_clk[1]), + .hsci_menc_clk_2 (hsci_menc_clk[2]), + .hsci_menc_clk_3 (hsci_menc_clk[3]), + .hsci_data_out_0 (hsci_data_out[0]), + .hsci_data_out_1 (hsci_data_out[1]), + .hsci_data_out_2 (hsci_data_out[2]), + .hsci_data_out_3 (hsci_data_out[3]), + .hsci_data_in_0 (hsci_data_in[0]), + .hsci_data_in_1 (hsci_data_in[1]), + .hsci_data_in_2 (hsci_data_in[2]), + .hsci_data_in_3 (hsci_data_in[3]), + .hsci_pclk_0 (hsci_pclk[0]), + .hsci_pclk_1 (hsci_pclk[1]), + .hsci_pll_reset_0 (hsci_pll_reset[0]), + .hsci_pll_reset_1 (hsci_pll_reset[1]), + .hsci_rst_seq_done_0 (hsci_rst_seq_done[0]), + .hsci_rst_seq_done_1 (hsci_rst_seq_done[1]), + .hsci_pll_locked_0 (hsci_pll_locked[0]), + .hsci_pll_locked_1 (hsci_pll_locked[1]), + .hsci_vtc_rdy_bsc_tx_0 (hsci_vtc_rdy_bsc_tx[0]), + .hsci_vtc_rdy_bsc_tx_1 (hsci_vtc_rdy_bsc_tx[1]), + .hsci_vtc_rdy_bsc_tx_2 (hsci_vtc_rdy_bsc_tx[2]), + .hsci_vtc_rdy_bsc_tx_3 (hsci_vtc_rdy_bsc_tx[3]), + .hsci_dly_rdy_bsc_tx_0 (hsci_dly_rdy_bsc_tx[0]), + .hsci_dly_rdy_bsc_tx_1 (hsci_dly_rdy_bsc_tx[1]), + .hsci_dly_rdy_bsc_tx_2 (hsci_dly_rdy_bsc_tx[2]), + .hsci_dly_rdy_bsc_tx_3 (hsci_dly_rdy_bsc_tx[3]), + .hsci_vtc_rdy_bsc_rx_0 (hsci_vtc_rdy_bsc_rx[0]), + .hsci_vtc_rdy_bsc_rx_1 (hsci_vtc_rdy_bsc_rx[1]), + .hsci_vtc_rdy_bsc_rx_2 (hsci_vtc_rdy_bsc_rx[2]), + .hsci_vtc_rdy_bsc_rx_3 (hsci_vtc_rdy_bsc_rx[3]), + .hsci_dly_rdy_bsc_rx_0 (hsci_dly_rdy_bsc_rx[0]), + .hsci_dly_rdy_bsc_rx_1 (hsci_dly_rdy_bsc_rx[1]), + .hsci_dly_rdy_bsc_rx_2 (hsci_dly_rdy_bsc_rx[2]), + .hsci_dly_rdy_bsc_rx_3 (hsci_dly_rdy_bsc_rx[3]), + + .adf4030_bsync_p (sysref_m2c_p), + .adf4030_bsync_n (sysref_m2c_n), + .adf4030_clk (rx_device_clk), + .adf4030_trigger (gp4[0]), + .adf4030_sysref (sysref), + .adf4030_trig_channel (trig_channel), + .adf4030_trig_request_out (trig_request), + + .ext_sync_in (sync_start), + + .ref_clk_q0 (ref_clk_replica), + .ref_clk_q1 (ref_clk_replica), + .ref_clk_q2 (ref_clk), + .ref_clk_q3 (ref_clk), + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref)); + +endmodule diff --git a/projects/ad_xband16_ebz/vcu118/system_top_slave.v b/projects/ad_xband16_ebz/vcu118/system_top_slave.v new file mode 100644 index 0000000000..68a21acdf0 --- /dev/null +++ b/projects/ad_xband16_ebz/vcu118/system_top_slave.v @@ -0,0 +1,593 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2026 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input sys_rst, + input sys_clk_p, + input sys_clk_n, + + input uart_sin, + output uart_sout, + + output ddr4_act_n, + output [16:0] ddr4_addr, + output [ 1:0] ddr4_ba, + output [ 0:0] ddr4_bg, + output ddr4_ck_p, + output ddr4_ck_n, + output [ 0:0] ddr4_cke, + output [ 0:0] ddr4_cs_n, + inout [ 7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [ 7:0] ddr4_dqs_p, + inout [ 7:0] ddr4_dqs_n, + output [ 0:0] ddr4_odt, + output ddr4_reset_n, + + output mdio_mdc, + inout mdio_mdio, + input phy_clk_p, + input phy_clk_n, + output phy_rst_n, + input phy_rx_p, + input phy_rx_n, + output phy_tx_p, + output phy_tx_n, + + inout [16:0] gpio_bd, + + output iic_rstn, + inout iic_scl, + inout iic_sda, + + input vadj_1v8_pgood, + + // FMCp IOs + input [15:0] m2c_p, + input [15:0] m2c_n, + output [15:0] c2m_p, + output [15:0] c2m_n, + + input [2:0] ref_clk_p, + input [2:0] ref_clk_n, + input ref_clk_replica_p, + input ref_clk_replica_n, + + inout sysref_m2c_p, + inout sysref_m2c_n, + + output apollo_sclk, + input apollo_sdo, + output apollo_sdi, + output [3:0] apollo_csb, + + output clk_sclk, + input clk_sdo, + output clk_sdi, + input clk_stat, + + output art_5v_en, + input art_5v_pg, + output [3:0] art_csb, + input art_stat, + + output ltc6953_csn, + output ltc6952_csn, + output ad4030_csn, + output vco_csn, + + output [3:0] hsci_ckin_p, + output [3:0] hsci_ckin_n, + output [3:0] hsci_din_p, + output [3:0] hsci_din_n, + input [3:0] hsci_cko_p, + input [3:0] hsci_cko_n, + input [3:0] hsci_do_p, + input [3:0] hsci_do_n, + + input ext_trig, + + output [3:0] trig0_a, + output [3:0] trig1_a, + output [3:0] trig0_b, + output [3:0] trig1_b, + + output [3:0] resetb, + output [1:0] txen, + output [1:0] rxen, + input [3:0] irqa, + input [3:0] irqb, + output [1:0] txrxn, + output [2:0] slice, + output txrxwe, + output [2:0] fcnsel, + output [4:0] profile, + + output [3:0] hpf_b, + output [3:0] lpf_b, + output admv8913_cs_n, + + input pdn_12v_pg, + input vddd_0p8_pg, + input vdda_1p0_pg, + input vddd_1p8_pg, + input vdda_1p8_pg, + input vneg_m1p0_pg, + + inout [3:0] gp4, + inout [3:0] gp5, + + // PMOD0 for MCS cotrol + output dma_start, + input trig_request, + output sync_start_debug, + output apollo_trig_debug, + + // PMOD1 for calibration board + output pmod1_adc_sync_n, + output pmod1_adc_sdi, + input pmod1_adc_sdo, + output pmod1_adc_sclk, + + output pmod1_5045_v2, + output pmod1_5045_v1, + output pmod1_ctrl_ind, + output pmod1_ctrl_rx_combined +); + + // internal signals + + wire [127:0] gpio_i; + wire [127:0] gpio_o; + wire [127:0] gpio_t; + + wire spi_2_clk; + wire [ 7:0] spi_2_csn; + wire spi_2_mosi; + wire spi_2_miso; + + wire spi_3_clk; + wire [ 7:0] spi_3_csn; + wire spi_3_mosi; + wire spi_3_miso; + + wire ref_clk; + wire ref_clk_replica; + wire sysref; + wire [3:0] link0_tx_syncin; + wire [3:0] link0_rx_syncout; + + wire clkin0; + wire clkin1; + wire rx_device_clk; + wire tx_device_clk; + + wire pll_inclk; + wire [ 0:1] hsci_pll_reset; + wire [ 0:1] hsci_pclk; + wire [ 0:1] hsci_pll_locked; + wire [ 0:3] hsci_vtc_rdy_bsc_tx; + wire [ 0:3] hsci_dly_rdy_bsc_tx; + wire [ 0:3] hsci_vtc_rdy_bsc_rx; + wire [ 0:3] hsci_dly_rdy_bsc_rx; + wire [ 0:1] hsci_rst_seq_done; + + wire selectio_clk_in; + wire [ 7:0] hsci_menc_clk [0:3]; + wire [ 7:0] hsci_data_in [0:3]; + wire [ 7:0] hsci_data_out [0:3]; + + wire [ 4:0] trig_channel; + wire debug_trig_out; + wire trigger_captured; + wire sync_start; + wire sync_start_edge; + + reg trigger_stretched = 1'b0; + reg trigger_sync1 = 1'b0; + reg trigger_sync2 = 1'b0; + + assign iic_rstn = 1'b1; + + // instantiations + IBUFDS_GTE4 i_ibufds_ref_clk ( + .CEB (1'd0), + .I (ref_clk_p[0]), + .IB (ref_clk_n[0]), + .O (ref_clk), + .ODIV2 ()); + + IBUFDS_GTE4 i_ibufds_ref_clk_replica ( + .CEB (1'd0), + .I (ref_clk_replica_p), + .IB (ref_clk_replica_n), + .O (ref_clk_replica), + .ODIV2 ()); + + IBUFDS_GTE4 i_ibufds_tx_device_clk ( + .I (ref_clk_p[1]), + .IB (ref_clk_n[1]), + .CEB(1'b0), + .ODIV2 (clkin0)); + + IBUFDS_GTE4 i_ibufds_rx_device_clk ( + .I (ref_clk_p[2]), + .IB (ref_clk_n[2]), + .CEB(1'b0), + .ODIV2 (clkin1)); + + BUFG_GT i_tx_device_clk ( + .I (clkin0), + .O (tx_device_clk)); + + BUFG_GT i_rx_device_clk ( + .I (clkin1), + .O (rx_device_clk)); + + // spi + assign art_csb = spi_2_csn[3:0]; + assign ad4030_csn = spi_2_csn[4]; + assign vco_csn = spi_2_csn[5]; + assign ltc6952_csn = spi_2_csn[6]; + assign ltc6953_csn = spi_2_csn[7]; + assign clk_sclk = spi_2_clk; + + assign pmod1_adc_sync_n = spi_3_csn[0]; + assign pmod1_adc_sdi = spi_3_mosi; + assign pmod1_adc_sclk = spi_3_clk; + + assign spi_3_miso = ~pmod1_adc_sync_n ? pmod1_adc_sdo : 1'b0; + + // gpios + ad_iobuf #( + .DATA_WIDTH(8) + ) i_iobuf ( + .dio_t (gpio_t[39:32]), + .dio_i (gpio_o[39:32]), + .dio_o (gpio_i[39:32]), + .dio_p ({gp5[3:0], // 39-36 + gp4[3:0]})); // 35-32 + + assign gpio_i[43:40] = irqa; + assign gpio_i[47:44] = irqb; + + assign trig0_a = {4{trig_channel[0]}}; + assign trig1_a = {4{trig_channel[1]}}; + assign trig0_b = {4{trig_channel[2]}}; + assign trig1_b = {4{trig_channel[3]}}; + assign dma_start = trig_channel[4]; + assign resetb = gpio_o[67:64]; + assign txen = gpio_o[69:68]; + assign rxen = gpio_o[71:70]; + assign txrxn = gpio_o[73:72]; + assign slice = gpio_o[76:74]; + assign txrxwe = gpio_o[77]; + assign fcnsel = gpio_o[80:78]; + assign profile = gpio_o[85:81]; + assign hpf_b = gpio_o[89:86]; + assign lpf_b = gpio_o[93:90]; + assign admv8913_cs_n = gpio_o[94]; + assign art_5v_en = gpio_o[95]; + assign pmod1_5045_v2 = gpio_o[96]; + assign pmod1_5045_v1 = gpio_o[97]; + assign pmod1_ctrl_ind = gpio_o[98]; + assign pmod1_ctrl_rx_combined = gpio_o[99]; + assign apollo_trig_debug = trig_channel[0]; + + assign gpio_i[100] = pdn_12v_pg; + assign gpio_i[101] = vddd_0p8_pg; + assign gpio_i[102] = vdda_1p0_pg; + assign gpio_i[103] = vddd_1p8_pg; + assign gpio_i[104] = vdda_1p8_pg; + assign gpio_i[105] = vneg_m1p0_pg; + assign gpio_i[106] = art_5v_pg; + assign gpio_i[107] = art_stat; + assign gpio_i[108] = clk_stat; + + ad_iobuf #( + .DATA_WIDTH(17) + ) i_iobuf_bd ( + .dio_t (gpio_t[16:0]), + .dio_i (gpio_o[16:0]), + .dio_o (gpio_i[16:0]), + .dio_p (gpio_bd)); + + assign gpio_i[127:109] = gpio_o[127:109]; + assign gpio_i[ 31:17] = gpio_o[ 31:17]; + + always @(posedge dma_start or posedge trigger_captured) begin + if (trigger_captured) + trigger_stretched <= 1'b0; + else + trigger_stretched <= 1'b1; + end + + always @(posedge sysref) begin + trigger_sync1 <= trigger_stretched; + trigger_sync2 <= trigger_sync1; + end + + assign trigger_captured = trigger_sync2; + + assign sync_start_edge = trigger_sync1 & ~trigger_sync2; + assign sync_start = sync_start_edge & sysref; + assign sync_start_debug = sync_start; + + hsci_phy_top hsci_phy_top( + .pll_inclk (selectio_clk_in), + .hsci_pll_reset (hsci_pll_reset), + + .hsci_pclk (hsci_pclk), + .hsci_mosi_d_p (hsci_din_p), + .hsci_mosi_d_n (hsci_din_n), + + .hsci_miso_d_p (hsci_do_p), + .hsci_miso_d_n (hsci_do_n), + + .hsci_pll_locked (hsci_pll_locked), + + .hsci_mosi_clk_p (hsci_ckin_p), + .hsci_mosi_clk_n (hsci_ckin_n), + + .hsci_miso_clk_p (hsci_cko_p), + .hsci_miso_clk_n (hsci_cko_n), + + .hsci_menc_clk_0 (hsci_menc_clk[0]), + .hsci_menc_clk_1 (hsci_menc_clk[1]), + .hsci_menc_clk_2 (hsci_menc_clk[2]), + .hsci_menc_clk_3 (hsci_menc_clk[3]), + + .hsci_mosi_data_0 (hsci_data_out[0]), + .hsci_mosi_data_1 (hsci_data_out[1]), + .hsci_mosi_data_2 (hsci_data_out[2]), + .hsci_mosi_data_3 (hsci_data_out[3]), + + .hsci_miso_data_0 (hsci_data_in[0]), + .hsci_miso_data_1 (hsci_data_in[1]), + .hsci_miso_data_2 (hsci_data_in[2]), + .hsci_miso_data_3 (hsci_data_in[3]), + + .vtc_rdy_bsc_tx (hsci_vtc_rdy_bsc_tx), + .dly_rdy_bsc_tx (hsci_dly_rdy_bsc_tx), + .vtc_rdy_bsc_rx (hsci_vtc_rdy_bsc_rx), + .dly_rdy_bsc_rx (hsci_dly_rdy_bsc_rx), + .rst_seq_done (hsci_rst_seq_done) + ); + + system_wrapper i_system_wrapper ( + .sys_rst (sys_rst), + .sys_clk_clk_n (sys_clk_n), + .sys_clk_clk_p (sys_clk_p), + .ddr4_act_n (ddr4_act_n), + .ddr4_adr (ddr4_addr), + .ddr4_ba (ddr4_ba), + .ddr4_bg (ddr4_bg), + .ddr4_ck_c (ddr4_ck_n), + .ddr4_ck_t (ddr4_ck_p), + .ddr4_cke (ddr4_cke), + .ddr4_cs_n (ddr4_cs_n), + .ddr4_dm_n (ddr4_dm_n), + .ddr4_dq (ddr4_dq), + .ddr4_dqs_c (ddr4_dqs_n), + .ddr4_dqs_t (ddr4_dqs_p), + .ddr4_odt (ddr4_odt), + .ddr4_reset_n (ddr4_reset_n), + .phy_sd (1'b1), + .phy_rst_n (phy_rst_n), + .sgmii_rxn (phy_rx_n), + .sgmii_rxp (phy_rx_p), + .sgmii_txn (phy_tx_n), + .sgmii_txp (phy_tx_p), + .mdio_mdc (mdio_mdc), + .mdio_mdio_io (mdio_mdio), + .sgmii_phyclk_clk_n (phy_clk_n), + .sgmii_phyclk_clk_p (phy_clk_p), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .uart_sin (uart_sin), + .uart_sout (uart_sout), + .spi_clk_i (apollo_sclk), + .spi_clk_o (apollo_sclk), + .spi_csn_i (apollo_csb), + .spi_csn_o (apollo_csb), + .spi_sdi_i (apollo_sdo), + .spi_sdo_i (apollo_sdi), + .spi_sdo_o (apollo_sdi), + + .spi_2_clk_i (spi_2_clk), + .spi_2_clk_o (spi_2_clk), + .spi_2_csn_i (spi_2_csn), + .spi_2_csn_o (spi_2_csn), + .spi_2_sdi_i (clk_sdo), + .spi_2_sdo_i (clk_sdi), + .spi_2_sdo_o (clk_sdi), + + .spi_3_clk_i (spi_3_clk), + .spi_3_clk_o (spi_3_clk), + .spi_3_csn_i (spi_3_csn), + .spi_3_csn_o (spi_3_csn), + .spi_3_sdi_i (spi_3_miso), + .spi_3_sdo_i (spi_3_mosi), + .spi_3_sdo_o (spi_3_mosi), + + .gpio0_i (gpio_i[31:0]), + .gpio0_o (gpio_o[31:0]), + .gpio0_t (gpio_t[31:0]), + .gpio1_i (gpio_i[63:32]), + .gpio1_o (gpio_o[63:32]), + .gpio1_t (gpio_t[63:32]), + + .gpio2_i (gpio_i[95:64]), + .gpio2_o (gpio_o[95:64]), + .gpio2_t (gpio_t[95:64]), + .gpio3_i (gpio_i[127:96]), + .gpio3_o (gpio_o[127:96]), + .gpio3_t (gpio_t[127:96]), + // FMCp + // quad 127 + .rx_data_0_n (m2c_n[3]), + .rx_data_0_p (m2c_p[3]), + .rx_data_1_n (m2c_n[2]), + .rx_data_1_p (m2c_p[2]), + .rx_data_2_n (m2c_n[1]), + .rx_data_2_p (m2c_p[1]), + .rx_data_3_n (m2c_n[0]), + .rx_data_3_p (m2c_p[0]), + // quad 125 + .rx_data_4_n (m2c_n[7]), + .rx_data_4_p (m2c_p[7]), + .rx_data_5_n (m2c_n[6]), + .rx_data_5_p (m2c_p[6]), + .rx_data_6_n (m2c_n[5]), + .rx_data_6_p (m2c_p[5]), + .rx_data_7_n (m2c_n[4]), + .rx_data_7_p (m2c_p[4]), + // quad 122 + .rx_data_8_n (m2c_n[10]), + .rx_data_8_p (m2c_p[10]), + .rx_data_9_n (m2c_n[11]), + .rx_data_9_p (m2c_p[11]), + .rx_data_10_n (m2c_n[9]), + .rx_data_10_p (m2c_p[9]), + .rx_data_11_n (m2c_n[8]), + .rx_data_11_p (m2c_p[8]), + // quad 120 + .rx_data_12_n (m2c_n[12]), + .rx_data_12_p (m2c_p[12]), + .rx_data_13_n (m2c_n[13]), + .rx_data_13_p (m2c_p[13]), + .rx_data_14_n (m2c_n[14]), + .rx_data_14_p (m2c_p[14]), + .rx_data_15_n (m2c_n[15]), + .rx_data_15_p (m2c_p[15]), + // quad 127 + .tx_data_0_n (c2m_n[3]), + .tx_data_0_p (c2m_p[3]), + .tx_data_1_n (c2m_n[2]), + .tx_data_1_p (c2m_p[2]), + .tx_data_2_n (c2m_n[1]), + .tx_data_2_p (c2m_p[1]), + .tx_data_3_n (c2m_n[0]), + .tx_data_3_p (c2m_p[0]), + // quad 125 + .tx_data_4_n (c2m_n[5]), + .tx_data_4_p (c2m_p[5]), + .tx_data_5_n (c2m_n[4]), + .tx_data_5_p (c2m_p[4]), + .tx_data_6_n (c2m_n[7]), + .tx_data_6_p (c2m_p[7]), + .tx_data_7_n (c2m_n[6]), + .tx_data_7_p (c2m_p[6]), + // quad 122 + .tx_data_8_n (c2m_n[8]), + .tx_data_8_p (c2m_p[8]), + .tx_data_9_n (c2m_n[11]), + .tx_data_9_p (c2m_p[11]), + .tx_data_10_n (c2m_n[10]), + .tx_data_10_p (c2m_p[10]), + .tx_data_11_n (c2m_n[9]), + .tx_data_11_p (c2m_p[9]), + // quad 120 + .tx_data_12_n (c2m_n[12]), + .tx_data_12_p (c2m_p[12]), + .tx_data_13_n (c2m_n[13]), + .tx_data_13_p (c2m_p[13]), + .tx_data_14_n (c2m_n[14]), + .tx_data_14_p (c2m_p[14]), + .tx_data_15_n (c2m_n[15]), + .tx_data_15_p (c2m_p[15]), + + .selectio_clk_in (selectio_clk_in), + + .hsci_menc_clk_0 (hsci_menc_clk[0]), + .hsci_menc_clk_1 (hsci_menc_clk[1]), + .hsci_menc_clk_2 (hsci_menc_clk[2]), + .hsci_menc_clk_3 (hsci_menc_clk[3]), + .hsci_data_out_0 (hsci_data_out[0]), + .hsci_data_out_1 (hsci_data_out[1]), + .hsci_data_out_2 (hsci_data_out[2]), + .hsci_data_out_3 (hsci_data_out[3]), + .hsci_data_in_0 (hsci_data_in[0]), + .hsci_data_in_1 (hsci_data_in[1]), + .hsci_data_in_2 (hsci_data_in[2]), + .hsci_data_in_3 (hsci_data_in[3]), + .hsci_pclk_0 (hsci_pclk[0]), + .hsci_pclk_1 (hsci_pclk[1]), + .hsci_pll_reset_0 (hsci_pll_reset[0]), + .hsci_pll_reset_1 (hsci_pll_reset[1]), + .hsci_rst_seq_done_0 (hsci_rst_seq_done[0]), + .hsci_rst_seq_done_1 (hsci_rst_seq_done[1]), + .hsci_pll_locked_0 (hsci_pll_locked[0]), + .hsci_pll_locked_1 (hsci_pll_locked[1]), + .hsci_vtc_rdy_bsc_tx_0 (hsci_vtc_rdy_bsc_tx[0]), + .hsci_vtc_rdy_bsc_tx_1 (hsci_vtc_rdy_bsc_tx[1]), + .hsci_vtc_rdy_bsc_tx_2 (hsci_vtc_rdy_bsc_tx[2]), + .hsci_vtc_rdy_bsc_tx_3 (hsci_vtc_rdy_bsc_tx[3]), + .hsci_dly_rdy_bsc_tx_0 (hsci_dly_rdy_bsc_tx[0]), + .hsci_dly_rdy_bsc_tx_1 (hsci_dly_rdy_bsc_tx[1]), + .hsci_dly_rdy_bsc_tx_2 (hsci_dly_rdy_bsc_tx[2]), + .hsci_dly_rdy_bsc_tx_3 (hsci_dly_rdy_bsc_tx[3]), + .hsci_vtc_rdy_bsc_rx_0 (hsci_vtc_rdy_bsc_rx[0]), + .hsci_vtc_rdy_bsc_rx_1 (hsci_vtc_rdy_bsc_rx[1]), + .hsci_vtc_rdy_bsc_rx_2 (hsci_vtc_rdy_bsc_rx[2]), + .hsci_vtc_rdy_bsc_rx_3 (hsci_vtc_rdy_bsc_rx[3]), + .hsci_dly_rdy_bsc_rx_0 (hsci_dly_rdy_bsc_rx[0]), + .hsci_dly_rdy_bsc_rx_1 (hsci_dly_rdy_bsc_rx[1]), + .hsci_dly_rdy_bsc_rx_2 (hsci_dly_rdy_bsc_rx[2]), + .hsci_dly_rdy_bsc_rx_3 (hsci_dly_rdy_bsc_rx[3]), + + .adf4030_bsync_p (sysref_m2c_p), + .adf4030_bsync_n (sysref_m2c_n), + .adf4030_clk (rx_device_clk), + .adf4030_trigger (trig_request), + .adf4030_sysref (sysref), + .adf4030_trig_channel (trig_channel), + .adf4030_trig_request_out (debug_trig_out), + + .ext_sync_in (sync_start), + + .ref_clk_q0 (ref_clk_replica), + .ref_clk_q1 (ref_clk_replica), + .ref_clk_q2 (ref_clk), + .ref_clk_q3 (ref_clk), + .rx_device_clk (rx_device_clk), + .tx_device_clk (tx_device_clk), + .rx_sysref_0 (sysref), + .tx_sysref_0 (sysref)); + +endmodule diff --git a/projects/ad_xband16_ebz/vcu118/timing_constr.xdc b/projects/ad_xband16_ebz/vcu118/timing_constr.xdc new file mode 100644 index 0000000000..a6067e909c --- /dev/null +++ b/projects/ad_xband16_ebz/vcu118/timing_constr.xdc @@ -0,0 +1,73 @@ +############################################################################### +## Copyright (C) 2026 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Primary clock definitions + +# Set clocks depending on the requested LANE_RATE paramter from the util_adxcvr block +# Maximum values for Link clock: +# 204C - 24.75 Gbps /66 = 375MHz + +set link_mode [get_property LINK_MODE [get_cells i_system_wrapper/system_i/util_apollo_xcvr/inst]] + +set rx_lane_rate [get_property RX_LANE_RATE [get_cells i_system_wrapper/system_i/util_apollo_xcvr/inst]] +set tx_lane_rate [get_property TX_LANE_RATE [get_cells i_system_wrapper/system_i/util_apollo_xcvr/inst]] + +set rx_link_clk [expr $rx_lane_rate*1000/[expr {$link_mode==2?66:40}]] +set tx_link_clk [expr $tx_lane_rate*1000/[expr {$link_mode==2?66:40}]] + +set rx_link_clk_period [expr 1000/$rx_link_clk] +set tx_link_clk_period [expr 1000/$tx_link_clk] + +set rx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_jesd/rx/inst]] +set tx_ll_width [get_property DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_jesd/tx/inst]] +set rx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_rx_jesd/rx/inst]] +set tx_tpl_width [get_property TPL_DATA_PATH_WIDTH [get_cells i_system_wrapper/system_i/axi_apollo_tx_jesd/tx/inst]] + +set rx_device_clk [expr $rx_link_clk*$rx_ll_width/$rx_tpl_width] +set tx_device_clk [expr $tx_link_clk*$tx_ll_width/$tx_tpl_width] +set rx_device_clk_period [expr 1000/$rx_device_clk] +set tx_device_clk_period [expr 1000/$tx_device_clk] + +# refclk and refclk_replica are connect to the same source on the PCB +# Set reference clock to same frequency as the link clock, +# this will ease the XCVR out clocks propagation calculation. +# TODO: this restricts RX_LANE_RATE=TX_LANE_RATE +create_clock -name refclk0 -period $rx_link_clk_period [get_ports ref_clk_p[0]] +create_clock -name refclk1 -period $rx_link_clk_period [get_ports ref_clk_replica_p] + +# device clock +create_clock -name tx_device_clk -period $tx_device_clk_period [get_ports ref_clk_p[1]] +create_clock -name rx_device_clk -period $rx_device_clk_period [get_ports ref_clk_p[2]] + +# hsci input clocks +create_clock -name hsci_clk_out_0 -period 1.25 [get_ports hsci_cko_p[0]] +create_clock -name hsci_clk_out_1 -period 1.25 [get_ports hsci_cko_p[1]] +create_clock -name hsci_clk_out_2 -period 1.25 [get_ports hsci_cko_p[2]] +create_clock -name hsci_clk_out_3 -period 1.25 [get_ports hsci_cko_p[3]] + +# Constraint SYSREFs +# Assumption is that REFCLK and SYSREF have similar propagation delay, +# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK +set_input_delay -clock [get_clocks rx_device_clk] \ + [get_property PERIOD [get_clocks rx_device_clk]] \ + [get_ports {sysref_m2c*}] +set_input_delay -clock [get_clocks tx_device_clk] -add_delay\ + [get_property PERIOD [get_clocks tx_device_clk]] \ + [get_ports {sysref_m2c*}] +set_clock_groups -group rx_device_clk -group tx_device_clk -asynchronous + +# For transceiver output clocks use reference clock divided by one +# This will help autoderive the clocks correcly +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXSYSCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/TXOUTCLKSEL[2]] + +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[0]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXSYSCLKSEL[1]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[0]] +set_case_analysis -quiet 1 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[1]] +set_case_analysis -quiet 0 [get_pins -quiet -hier *_channel/RXOUTCLKSEL[2]]