diff --git a/docs/projects/ad5706r/ad5706r_block_diagram.svg b/docs/projects/ad5706r/ad5706r_block_diagram.svg
new file mode 100644
index 00000000000..e7cb304634f
--- /dev/null
+++ b/docs/projects/ad5706r/ad5706r_block_diagram.svg
@@ -0,0 +1,1950 @@
+
+
+
+
diff --git a/docs/projects/ad5706r/index.rst b/docs/projects/ad5706r/index.rst
new file mode 100644
index 00000000000..6f45c4d3475
--- /dev/null
+++ b/docs/projects/ad5706r/index.rst
@@ -0,0 +1,187 @@
+.. _ad5706r:
+
+AD5706R HDL project
+================================================================================
+
+Overview
+--------------------------------------------------------------------------------
+
+The :adi:`AD5706R` devices are 4-channel, 16-/12-/10-bit resolution, low noise,
+programmable current output, digital-to-analog converter (DAC) capable of
+multiple operating modes and output current ranges with high power efficiency.
+These are intended for photonics control and current mode biasing applications.
+The devices incorporate a 2.5V, on-chip voltage reference, die temperature, load
+DAC, and A/B toggle functions, output monitoring functions, and reset functions.
+
+The family provides multiple programmable output current ranges up to 300mA.
+With device addressable pins, an SPI transaction can communicate with up to four
+:adi:`AD5706R` on the same SPI bus. Each DAC operates with an independent
+positive power supply rails PVDDx from 1.65V to 3.6V, for optimizing power
+efficiency and thermal power dissipation. The AD5706R operate from a 2.9V to
+3.6V AVDD supply and are specified over the −40°C to +125°C temperature range.
+
+Applications:
+
+- Photonics Control
+- Optical Communications
+- LED Driver Programmable Current Source
+- Current Mode Biasing
+
+Supported boards
+-------------------------------------------------------------------------------
+
+- :adi:`EVAL-AD5706RARDZ`
+
+Supported devices
+-------------------------------------------------------------------------------
+
+- :adi:`AD5706`
+- :adi:`AD5706R`
+
+Supported carriers
+-------------------------------------------------------------------------------
+
+- :xilinx:`Cora Z7-07S ` on Arduino Header
+
+Block design
+-------------------------------------------------------------------------------
+
+Block diagram
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The data path is depicted in the below diagram:
+
+.. image:: ad5706r_block_diagram.svg
+ :width: 800
+ :align: center
+ :alt: AD5706R block diagram
+
+Hardware setup
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+========= ================= =============
+Signal AD5706R Testpoint Cora Z7s
+========= ================= =============
+SPI_CSB CS CHIPKIT IO 10
+SPI_SDO SDO CHIPKIT IO 11
+SPI_SDI SDI CHIPKIT IO 12
+SPI_SCLK SCK CHIPKIT IO 13
+SHDN PMOD P7 CHIPKIT IO 7
+RESETB RESET CHIPKIT IO 8
+LDACB_TGP PMOD P6 CHIPKIT IO 9
+========= ================= =============
+
+.. important::
+
+ The evaluation board is powered by 5 V voltage from an external USB.
+
+CPU/Memory interconnects addresses
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The addresses are dependent on the architecture of the FPGA, having an offset
+added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`).
+
+=================== ==========
+Instance Zynq
+=================== ==========
+axi_ad5706R_pwm_gen 0x44A00000
+xadc_in 0x44A50000
+spi_ad5706r_dac 0x44B00000
+spi_clkgen 0x44C00000
+=================== ==========
+
+GPIOs
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The Software GPIO number is calculated as follows:
+
+- Zynq-7000: if PS7 is used, then the offset is 54
+
+.. list-table::
+ :widths: 25 25 25 25
+ :header-rows: 2
+
+ * - GPIO signal
+ - Direction
+ - HDL GPIO EMIO
+ - Software GPIO
+ * -
+ - (from FPGA view)
+ -
+ - Zynq-7000
+ * - RESETB
+ - OUT
+ - 32
+ - 86
+ * - SHDN
+ - OUT
+ - 33
+ - 87
+
+Building the HDL project
+-------------------------------------------------------------------------------
+
+The design is built upon ADI's generic HDL reference design framework.
+ADI distributes the bit/elf files of these projects as part of the
+:external+documentation:ref:`kuiper`.
+If you want to build the sources, ADI makes them available on the
+:git-hdl:`HDL repository `. To get the source you must
+`clone `__
+the HDL repository, and then build the project as follows:
+
+**Linux/Cygwin/WSL**
+
+.. shell::
+
+ $cd hdl/projects/ad5706r/coraz7s
+ $make
+
+A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
+
+Resources
+-------------------------------------------------------------------------------
+
+Hardware related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Product datasheet: :adi:`AD5706R`
+- :adi:`EVAL-AD5706R User Guide `
+
+HDL related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- :git-hdl:`AD5706R HDL project source code `
+
+.. list-table::
+ :widths: 30 35 35
+ :header-rows: 1
+
+ * - IP name
+ - Source code link
+ - Documentation link
+ * - AXI_CLKGEN
+ - :git-hdl:`library/axi_clkgen`
+ - :ref:`axi_clkgen`
+ * - AXI_DMAC
+ - :git-hdl:`library/axi_dmac`
+ - :ref:`axi_dmac`
+ * - AXI_HDMI_TX
+ - :git-hdl:`library/axi_hdmi_tx`
+ - :ref:`axi_hdmi_tx`
+ * - AXI_PWM_GEN
+ - :git-hdl:`library/axi_pwm_gen`
+ - :ref:`axi_pwm_gen`
+ * - SPI_ENGINE
+ - :git-hdl:`library/spi_engine`
+ - :ref:`spi_engine`
+
+Software related
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- :git-no-os:`AD5706R No-OS project source code `
+- :git-no-os:`AD5706R No-OS Driver source code `
+- :git-linux:`AD5706R Linux Driver source code `
+
+.. include:: ../common/more_information.rst
+
+.. include:: ../common/support.rst
diff --git a/docs/projects/index.rst b/docs/projects/index.rst
index 4a15f94fead..4104df4cb79 100644
--- a/docs/projects/index.rst
+++ b/docs/projects/index.rst
@@ -34,6 +34,7 @@ Contents
AD485X-FMCZ
AD4880-FMC-EVB
AD5529R-ARDZ
+ AD5706R
AD5758-SDZ
AD5766-SDZ
AD57XX-ARDZ
diff --git a/projects/ad5706r/Makefile b/projects/ad5706r/Makefile
new file mode 100644
index 00000000000..172ebbbe4bd
--- /dev/null
+++ b/projects/ad5706r/Makefile
@@ -0,0 +1,7 @@
+####################################################################################
+## Copyright (c) 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+include ../scripts/project-toplevel.mk
diff --git a/projects/ad5706r/README.md b/projects/ad5706r/README.md
new file mode 100644
index 00000000000..34246783b00
--- /dev/null
+++ b/projects/ad5706r/README.md
@@ -0,0 +1,17 @@
+# AD5706R HDL Project
+
+- Evaluation board product page:
+ - [EVAL-AD5706RARDZ](https://analog.com/eval-ad5706r)
+- System documentation: https://wiki.analog.com/resources/eval/user-guides/ad5706r
+- HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/ad5706r/index.html
+- Evaluation board VADJ: 2.5V
+
+## Supported parts
+
+| Part name | Description |
+|-----------------------------------------------|---------------------------------------|
+| [AD5706R](https://www.analog.com/AD5706R) | 4-channel, 16-bit, current output DAC |
+
+## Building the project
+
+Please enter the folder for the FPGA carrier you want to use and read the README.md.
diff --git a/projects/ad5706r/common/ad5706r_bd.tcl b/projects/ad5706r/common/ad5706r_bd.tcl
new file mode 100644
index 00000000000..209acd4f86c
--- /dev/null
+++ b/projects/ad5706r/common/ad5706r_bd.tcl
@@ -0,0 +1,75 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_bd_port -dir O ldacb_tgp
+create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux1
+create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 spi
+
+# pwm gen
+ad_ip_instance axi_pwm_gen axi_ad5706r_pwm_gen
+ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.ASYNC_CLK_EN 1
+ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.PULSE_0_WIDTH 5
+ad_ip_parameter axi_ad5706r_pwm_gen CONFIG.PULSE_0_PERIOD 10
+
+ad_connect axi_ad5706r_pwm_gen/pwm_0 ldacb_tgp
+ad_connect axi_ad5706r_pwm_gen/ext_clk $sys_cpu_clk
+
+#spi_engine reference clock
+ad_ip_instance axi_clkgen spi_clkgen
+ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 1
+ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 10
+ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 1
+
+ad_connect $sys_cpu_clk spi_clkgen/clk
+ad_connect spi_clk spi_clkgen/clk_0
+
+#spi_engine
+source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+set hier_spi_engine spi_ad5706r_dac
+set data_width 32
+set async_spi_clk 1
+set offload_en 0
+set num_cs 1
+set num_sdi 1
+set sdi_delay 1
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $sdi_delay
+ad_connect $hier_spi_engine/m_spi spi
+
+#clocks and resets
+ad_connect $sys_cpu_clk $hier_spi_engine/clk
+ad_connect spi_clk $hier_spi_engine/spi_clk
+ad_connect $sys_cpu_resetn $hier_spi_engine/resetn
+
+# Xilinx's XADC
+ad_ip_instance xadc_wiz xadc_in
+
+ad_ip_parameter xadc_in CONFIG.TIMING_MODE Continuous
+ad_ip_parameter xadc_in CONFIG.XADC_STARUP_SELECTION channel_sequencer
+ad_ip_parameter xadc_in CONFIG.SEQUENCER_MODE Continuous
+ad_ip_parameter xadc_in CONFIG.ENABLE_VCCDDRO_ALARM false
+ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPAUX_ALARM false
+ad_ip_parameter xadc_in CONFIG.ENABLE_VCCPINT_ALARM false
+ad_ip_parameter xadc_in CONFIG.ENABLE_AXI4STREAM false
+ad_ip_parameter xadc_in CONFIG.ENABLE_EXTERNAL_MUX false
+ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VP_VN false
+ad_ip_parameter xadc_in CONFIG.CHANNEL_ENABLE_VAUXP1_VAUXN1 true
+ad_ip_parameter xadc_in CONFIG.OT_ALARM false
+ad_ip_parameter xadc_in CONFIG.SINGLE_CHANNEL_SELECTION TEMPERATURE
+ad_ip_parameter xadc_in CONFIG.USER_TEMP_ALARM false
+ad_ip_parameter xadc_in CONFIG.VCCAUX_ALARM false
+ad_ip_parameter xadc_in CONFIG.VCCINT_ALARM false
+
+ad_connect xadc_in/Vaux1 xadc_vaux1
+
+# interconnects (cpu)
+ad_cpu_interconnect 0x44a00000 axi_ad5706r_pwm_gen
+ad_cpu_interconnect 0x44a50000 xadc_in
+ad_cpu_interconnect 0x44b00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap
+ad_cpu_interconnect 0x44c00000 spi_clkgen
+
+# interrupts
+ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq
diff --git a/projects/ad5706r/coraz7s/Makefile b/projects/ad5706r/coraz7s/Makefile
new file mode 100644
index 00000000000..24a1d26a26a
--- /dev/null
+++ b/projects/ad5706r/coraz7s/Makefile
@@ -0,0 +1,28 @@
+####################################################################################
+## Copyright (c) 2025 Analog Devices, Inc.
+### SPDX short identifier: BSD-1-Clause
+## Auto-generated, do not modify!
+####################################################################################
+
+PROJECT_NAME := ad5706r_coraz7s
+
+M_DEPS += ../common/ad5706r_bd.tcl
+M_DEPS += ../../scripts/adi_pd.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
+M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
+M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
+M_DEPS += ../../../library/common/ad_iobuf.v
+M_DEPS += ../../../library/spi_engine/scripts/spi_engine.tcl
+
+LIB_DEPS += axi_clkgen
+LIB_DEPS += axi_dmac
+LIB_DEPS += axi_sysid
+LIB_DEPS += axi_pwm_gen
+LIB_DEPS += spi_engine/axi_spi_engine
+LIB_DEPS += spi_engine/spi_axis_reorder
+LIB_DEPS += spi_engine/spi_engine_execution
+LIB_DEPS += spi_engine/spi_engine_interconnect
+LIB_DEPS += spi_engine/spi_engine_offload
+LIB_DEPS += sysid_rom
+
+include ../../scripts/project-xilinx.mk
diff --git a/projects/ad5706r/coraz7s/README.md b/projects/ad5706r/coraz7s/README.md
new file mode 100644
index 00000000000..c64e33f4b4d
--- /dev/null
+++ b/projects/ad5706r/coraz7s/README.md
@@ -0,0 +1,10 @@
+
+
+# AD5706R/CORAZ7S HDL Project
+
+## Building the project
+
+```
+cd projects/ad5706r/coraz7s
+make
+```
diff --git a/projects/ad5706r/coraz7s/system_bd.tcl b/projects/ad5706r/coraz7s/system_bd.tcl
new file mode 100644
index 00000000000..eb99c2ca9b3
--- /dev/null
+++ b/projects/ad5706r/coraz7s/system_bd.tcl
@@ -0,0 +1,17 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
+source $ad_hdl_dir/projects/scripts/adi_pd.tcl
+source ../common/ad5706r_bd.tcl
+
+#system ID
+ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
+ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
+ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
+
+sysid_gen_sys_init_file
+
+set sys_dma_clk [get_bd_nets sys_dma_clk]
diff --git a/projects/ad5706r/coraz7s/system_constr.xdc b/projects/ad5706r/coraz7s/system_constr.xdc
new file mode 100644
index 00000000000..5d08caa80ef
--- /dev/null
+++ b/projects/ad5706r/coraz7s/system_constr.xdc
@@ -0,0 +1,18 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]]
+
+# DAC SPI interface
+set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { spi_csb }] ; #IO_L11N_T1_SRCC_34 Sch=ck_io[10]
+set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { spi_sdo }] ; #IO_L12N_T1_MRCC_35 Sch=ck_io[11]
+set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { spi_sdi }] ; #IO_L14P_T2_AD4P_SRCC_35 Sch=ck_io[12]
+set_property -dict { PACKAGE_PIN G15 IOSTANDARD LVCMOS33 } [get_ports { spi_sclk }] ; #IO_L19N_T3_VREF_35 Sch=ck_io[13]
+
+# DAC GPIO interface
+set_property -dict { PACKAGE_PIN R14 IOSTANDARD LVCMOS33 } [get_ports { shdn }] ; #IO_L6N_T0_VREF_34 Sch=ck_io[7]
+set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { resetb }] ; #IO_L13P_T2_MRCC_34 Sch=ck_io[8]
+set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ldacb_tgp }]; #IO_L8N_T1_AD10N_35 Sch=ck_io[9]
+
diff --git a/projects/ad5706r/coraz7s/system_project.tcl b/projects/ad5706r/coraz7s/system_project.tcl
new file mode 100644
index 00000000000..d520c2b1da9
--- /dev/null
+++ b/projects/ad5706r/coraz7s/system_project.tcl
@@ -0,0 +1,20 @@
+###############################################################################
+## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIBSD
+###############################################################################
+
+source ../../../scripts/adi_env.tcl
+source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
+
+adi_project ad5706r_coraz7s
+
+adi_project_files ad5706r_coraz7s [list \
+ "$ad_hdl_dir/library/common/ad_iobuf.v" \
+ "system_top.v" \
+ "system_constr.xdc" \
+ "$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
+
+set_property PROCESSING_ORDER LATE [get_files system_constr.xdc]
+
+adi_project_run ad5706r_coraz7s
diff --git a/projects/ad5706r/coraz7s/system_top.v b/projects/ad5706r/coraz7s/system_top.v
new file mode 100644
index 00000000000..6a7a4606ac4
--- /dev/null
+++ b/projects/ad5706r/coraz7s/system_top.v
@@ -0,0 +1,161 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright (C) 2026 Analog Devices, Inc. All rights reserved.
+//
+// In this HDL repository, there are many different and unique modules, consisting
+// of various HDL (Verilog or VHDL) components. The individual modules are
+// developed independently, and may be accompanied by separate and unique license
+// terms.
+//
+// The user should read each of these license terms, and understand the
+// freedoms and responsibilities that he or she has by using this source/core.
+//
+// This core is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
+// A PARTICULAR PURPOSE.
+//
+// Redistribution and use of source or resulting binaries, with or without modification
+// of this file, are permitted under one of the following two license terms:
+//
+// 1. The GNU General Public License version 2 as published by the
+// Free Software Foundation, which can be found in the top level directory
+// of this repository (LICENSE_GPL2), and also online at:
+//
+//
+// OR
+//
+// 2. An ADI specific BSD license, which can be found in the top level directory
+// of this repository (LICENSE_ADIBSD), and also on-line at:
+// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
+// This will allow to generate bit files and not release the source code,
+// as long as it attaches to an ADI device.
+//
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module system_top (
+
+ inout [14:0] ddr_addr,
+ inout [ 2:0] ddr_ba,
+ inout ddr_cas_n,
+ inout ddr_ck_n,
+ inout ddr_ck_p,
+ inout ddr_cke,
+ inout ddr_cs_n,
+ inout [ 3:0] ddr_dm,
+ inout [31:0] ddr_dq,
+ inout [ 3:0] ddr_dqs_n,
+ inout [ 3:0] ddr_dqs_p,
+ inout ddr_odt,
+ inout ddr_ras_n,
+ inout ddr_reset_n,
+ inout ddr_we_n,
+
+ inout fixed_io_ddr_vrn,
+ inout fixed_io_ddr_vrp,
+ inout [53:0] fixed_io_mio,
+ inout fixed_io_ps_clk,
+ inout fixed_io_ps_porb,
+ inout fixed_io_ps_srstb,
+
+ inout [ 1:0] btn,
+ inout [ 5:0] led,
+
+ inout iic_ard_scl,
+ inout iic_ard_sda,
+
+ output resetb,
+ output ldacb_tgp,
+ output shdn,
+
+ output spi_sclk,
+ output spi_csb,
+ output spi_sdo,
+ input spi_sdi
+);
+
+ // internal signals
+ wire [63:0] gpio_i;
+ wire [63:0] gpio_o;
+ wire [63:0] gpio_t;
+
+ assign gpio_i[63:34] = gpio_o[63:34];
+
+ //Control
+ assign resetb = gpio_o[32];
+ assign shdn = gpio_o[33];
+
+ // instantiations
+ ad_iobuf #(
+ .DATA_WIDTH (2)
+ ) i_iobuf_buttons (
+ .dio_t (gpio_t[1:0]),
+ .dio_i (gpio_o[1:0]),
+ .dio_o (gpio_i[1:0]),
+ .dio_p (btn));
+
+ ad_iobuf #(
+ .DATA_WIDTH (6)
+ ) i_iobuf_leds (
+ .dio_t (gpio_t[7:2]),
+ .dio_i (gpio_o[7:2]),
+ .dio_o (gpio_i[7:2]),
+ .dio_p (led));
+
+ system_wrapper i_system_wrapper (
+ .ddr_addr (ddr_addr),
+ .ddr_ba (ddr_ba),
+ .ddr_cas_n (ddr_cas_n),
+ .ddr_ck_n (ddr_ck_n),
+ .ddr_ck_p (ddr_ck_p),
+ .ddr_cke (ddr_cke),
+ .ddr_cs_n (ddr_cs_n),
+ .ddr_dm (ddr_dm),
+ .ddr_dq (ddr_dq),
+ .ddr_dqs_n (ddr_dqs_n),
+ .ddr_dqs_p (ddr_dqs_p),
+ .ddr_odt (ddr_odt),
+ .ddr_ras_n (ddr_ras_n),
+ .ddr_reset_n (ddr_reset_n),
+ .ddr_we_n (ddr_we_n),
+
+ .fixed_io_ddr_vrn (fixed_io_ddr_vrn),
+ .fixed_io_ddr_vrp (fixed_io_ddr_vrp),
+ .fixed_io_mio (fixed_io_mio),
+ .fixed_io_ps_clk (fixed_io_ps_clk),
+ .fixed_io_ps_porb (fixed_io_ps_porb),
+ .fixed_io_ps_srstb (fixed_io_ps_srstb),
+
+ .gpio_i (gpio_i),
+ .gpio_o (gpio_o),
+ .gpio_t (gpio_t),
+
+ .spi0_clk_i (1'b0),
+ .spi0_clk_o (),
+ .spi0_csn_0_o (),
+ .spi0_csn_1_o (),
+ .spi0_csn_2_o (),
+ .spi0_csn_i (1'b1),
+ .spi0_sdi_i (1'b0),
+ .spi0_sdo_i (1'b0),
+ .spi0_sdo_o (),
+ .spi1_clk_i (1'b0),
+ .spi1_clk_o (),
+ .spi1_csn_0_o (),
+ .spi1_csn_1_o (),
+ .spi1_csn_2_o (),
+ .spi1_csn_i (1'b1),
+ .spi1_sdi_i (1'b0),
+ .spi1_sdo_i (1'b0),
+ .spi1_sdo_o (),
+ .spi_sdo (spi_sdo),
+ .spi_sdi (spi_sdi),
+ .spi_cs (spi_csb),
+ .spi_sclk (spi_sclk),
+ .iic_ard_scl_io (iic_ard_scl),
+ .iic_ard_sda_io (iic_ard_sda),
+ .ldacb_tgp(ldacb_tgp));
+
+endmodule