diff --git a/library/spi_engine/scripts/spi_engine.tcl b/library/spi_engine/scripts/spi_engine.tcl
index 63007966c2a..c484038de53 100644
--- a/library/spi_engine/scripts/spi_engine.tcl
+++ b/library/spi_engine/scripts/spi_engine.tcl
@@ -5,18 +5,8 @@
 
 ## Unified SPI Engine generation script
 ## This script provides a single implementation that works for both Xilinx and Intel
-## by using the vendor-agnostic ad_* procedures from adi_board.tcl or <intel_carrier>_system_qsys.tcl
-
-proc ad_detect_vendor {} {
-  if {[info commands get_bd_cells] != ""} {
-    return "xilinx"
-  }
-  if {[info commands add_instance] != ""} {
-    return "intel"
-  }
-  # Default to xilinx for backward compatibility
-  return "xilinx"
-}
+## by using the vendor-agnostic ad_* procedures from adi_board.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 proc optional_param {param_list index default_value} {
   if {[llength $param_list] > $index} {
diff --git a/projects/ad4052_ardz/common/ad4052_qsys.tcl b/projects/ad4052_ardz/common/ad4052_qsys.tcl
index 353a68732e9..37da1815cd1 100644
--- a/projects/ad4052_ardz/common/ad4052_qsys.tcl
+++ b/projects/ad4052_ardz/common/ad4052_qsys.tcl
@@ -4,53 +4,53 @@
 ###############################################################################
 
 # receive dma
-add_instance axi_dmac_0 axi_dmac
-set_instance_parameter_value axi_dmac_0 {DMA_TYPE_SRC} {1}
-set_instance_parameter_value axi_dmac_0 {DMA_TYPE_DEST} {0}
-set_instance_parameter_value axi_dmac_0 {CYCLIC} {0}
-set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_SRC} {32}
-set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
+ad_ip_instance axi_dmac axi_adc_dma
+ad_ip_parameter axi_adc_dma CONFIG.DMA_TYPE_SRC {1}
+ad_ip_parameter axi_adc_dma CONFIG.DMA_TYPE_DEST {0}
+ad_ip_parameter axi_adc_dma CONFIG.CYCLIC {0}
+ad_ip_parameter axi_adc_dma CONFIG.DMA_DATA_WIDTH_SRC {32}
+ad_ip_parameter axi_adc_dma CONFIG.DMA_DATA_WIDTH_DEST {128}
 
 # axi_pwm_gen
 
-add_instance pwm_trigger axi_pwm_gen
-set_instance_parameter_value pwm_trigger {PULSE_0_PERIOD} {120}
-set_instance_parameter_value pwm_trigger {PULSE_0_WIDTH} {1}
+ad_ip_instance axi_pwm_gen pwm_trigger
+ad_ip_parameter pwm_trigger CONFIG.PULSE_0_PERIOD {120}
+ad_ip_parameter pwm_trigger CONFIG.PULSE_0_WIDTH {1}
 
 # spi_clk pll
 
-add_instance spi_clk_pll altera_pll
-set_instance_parameter_value spi_clk_pll {gui_feedback_clock} {Global Clock}
-set_instance_parameter_value spi_clk_pll {gui_operation_mode} {direct}
-set_instance_parameter_value spi_clk_pll {gui_number_of_clocks} {1}
-set_instance_parameter_value spi_clk_pll {gui_output_clock_frequency0} {150}
-set_instance_parameter_value spi_clk_pll {gui_phase_shift0} {0}
-set_instance_parameter_value spi_clk_pll {gui_phase_shift1} {0}
-set_instance_parameter_value spi_clk_pll {gui_phase_shift_deg0} {0.0}
-set_instance_parameter_value spi_clk_pll {gui_phase_shift_deg1} {0.0}
-set_instance_parameter_value spi_clk_pll {gui_phout_division} {1}
-set_instance_parameter_value spi_clk_pll {gui_pll_auto_reset} {Off}
-set_instance_parameter_value spi_clk_pll {gui_pll_bandwidth_preset} {Auto}
-set_instance_parameter_value spi_clk_pll {gui_pll_mode} {Fractional-N PLL}
-set_instance_parameter_value spi_clk_pll {gui_ps_units0} {ps}
-set_instance_parameter_value spi_clk_pll {gui_refclk_switch} {0}
-set_instance_parameter_value spi_clk_pll {gui_reference_clock_frequency} {50.0}
-set_instance_parameter_value spi_clk_pll {gui_switchover_delay} {0}
-set_instance_parameter_value spi_clk_pll {gui_en_reconf} {1}
-
-add_instance spi_clk_pll_reconfig altera_pll_reconfig
-set_instance_parameter_value spi_clk_pll_reconfig {ENABLE_BYTEENABLE} {0}
-set_instance_parameter_value spi_clk_pll_reconfig {ENABLE_MIF} {0}
-set_instance_parameter_value spi_clk_pll_reconfig {MIF_FILE_NAME} {}
-
-add_connection spi_clk_pll.reconfig_from_pll spi_clk_pll_reconfig.reconfig_from_pll
+ad_ip_instance altera_pll spi_clk_pll
+ad_ip_parameter spi_clk_pll CONFIG.gui_feedback_clock {Global Clock}
+ad_ip_parameter spi_clk_pll CONFIG.gui_operation_mode {direct}
+ad_ip_parameter spi_clk_pll CONFIG.gui_number_of_clocks {1}
+ad_ip_parameter spi_clk_pll CONFIG.gui_output_clock_frequency0 {150}
+ad_ip_parameter spi_clk_pll CONFIG.gui_phase_shift0 {0}
+ad_ip_parameter spi_clk_pll CONFIG.gui_phase_shift1 {0}
+ad_ip_parameter spi_clk_pll CONFIG.gui_phase_shift_deg0 {0.0}
+ad_ip_parameter spi_clk_pll CONFIG.gui_phase_shift_deg1 {0.0}
+ad_ip_parameter spi_clk_pll CONFIG.gui_phout_division {1}
+ad_ip_parameter spi_clk_pll CONFIG.gui_pll_auto_reset {Off}
+ad_ip_parameter spi_clk_pll CONFIG.gui_pll_bandwidth_preset {Auto}
+ad_ip_parameter spi_clk_pll CONFIG.gui_pll_mode {Fractional-N PLL}
+ad_ip_parameter spi_clk_pll CONFIG.gui_ps_units0 {ps}
+ad_ip_parameter spi_clk_pll CONFIG.gui_refclk_switch {0}
+ad_ip_parameter spi_clk_pll CONFIG.gui_reference_clock_frequency {50.0}
+ad_ip_parameter spi_clk_pll CONFIG.gui_switchover_delay {0}
+ad_ip_parameter spi_clk_pll CONFIG.gui_en_reconf {1}
+
+ad_ip_instance altera_pll_reconfig spi_clk_pll_reconfig
+ad_ip_parameter spi_clk_pll_reconfig CONFIG.ENABLE_BYTEENABLE {0}
+ad_ip_parameter spi_clk_pll_reconfig CONFIG.ENABLE_MIF {0}
+ad_ip_parameter spi_clk_pll_reconfig CONFIG.MIF_FILE_NAME {}
+
+ad_connect spi_clk_pll.reconfig_from_pll spi_clk_pll_reconfig.reconfig_from_pll
 set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll endPort {}
 set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll endPortLSB {0}
 set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll startPort {}
 set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll startPortLSB {0}
 set_connection_parameter_value spi_clk_pll.reconfig_from_pll/spi_clk_pll_reconfig.reconfig_from_pll width {0}
 
-add_connection spi_clk_pll.reconfig_to_pll spi_clk_pll_reconfig.reconfig_to_pll
+ad_connect spi_clk_pll.reconfig_to_pll spi_clk_pll_reconfig.reconfig_to_pll
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll endPort {}
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll endPortLSB {0}
 set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.reconfig_to_pll startPort {}
@@ -76,7 +76,7 @@ set axi_reset sys_clk.clk_reset
 set spi_clk spi_clk_pll.outclk0
 
 spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
-set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
+ad_ip_parameter ${spi_engine_hier}_offload CONFIG.ASYNC_TRIG {1}
 # exported interface
 
 add_interface adc_spi_sclk    clock source
@@ -94,41 +94,41 @@ set_interface_property adc_cnv          EXPORT_OF pwm_trigger.if_pwm_0
 
 # clocks
 
-add_connection sys_clk.clk spi_clk_pll.refclk
-add_connection sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
-add_connection sys_clk.clk axi_dmac_0.s_axi_clock
-add_connection sys_clk.clk pwm_trigger.s_axi_clock
+ad_connect sys_clk.clk spi_clk_pll.refclk
+ad_connect sys_clk.clk spi_clk_pll_reconfig.mgmt_clk
+ad_connect sys_clk.clk axi_adc_dma.s_axi_clock
+ad_connect sys_clk.clk pwm_trigger.s_axi_clock
 
-add_connection spi_clk_pll.outclk0 pwm_trigger.if_ext_clk
-add_connection spi_clk_pll.outclk0 axi_dmac_0.if_s_axis_aclk
+ad_connect spi_clk_pll.outclk0 pwm_trigger.if_ext_clk
+ad_connect spi_clk_pll.outclk0 axi_adc_dma.if_s_axis_aclk
 
-add_connection sys_dma_clk.clk axi_dmac_0.m_dest_axi_clock
+ad_connect sys_dma_clk.clk axi_adc_dma.m_dest_axi_clock
 
 # resets
 
-add_connection sys_clk.clk_reset spi_clk_pll.reset
-add_connection sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
-add_connection sys_clk.clk_reset axi_dmac_0.s_axi_reset
-add_connection sys_clk.clk_reset pwm_trigger.s_axi_reset
+ad_connect sys_clk.clk_reset spi_clk_pll.reset
+ad_connect sys_clk.clk_reset spi_clk_pll_reconfig.mgmt_reset
+ad_connect sys_clk.clk_reset axi_adc_dma.s_axi_reset
+ad_connect sys_clk.clk_reset pwm_trigger.s_axi_reset
 
-add_connection sys_dma_clk.clk_reset axi_dmac_0.m_dest_axi_reset
+ad_connect sys_dma_clk.clk_reset axi_adc_dma.m_dest_axi_reset
 
 # interfaces
 
-add_connection ${spi_engine_hier}_offload.offload_sdi axi_dmac_0.s_axis
+ad_connect ${spi_engine_hier}_offload.offload_sdi axi_adc_dma.s_axis
 
 # cpu interconnects
 
-ad_cpu_interconnect 0x00020000 axi_dmac_0.s_axi
-ad_cpu_interconnect 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
-ad_cpu_interconnect 0x00040000 pwm_trigger.s_axi
-ad_cpu_interconnect 0x00050000 spi_clk_pll_reconfig.mgmt_avalon_slave
+ad_cpu_interconnect_intel 0x00020000 axi_adc_dma.s_axi
+ad_cpu_interconnect_intel 0x00030000 ${spi_engine_hier}_axi_regmap.s_axi
+ad_cpu_interconnect_intel 0x00040000 pwm_trigger.s_axi
+ad_cpu_interconnect_intel 0x00050000 spi_clk_pll_reconfig.mgmt_avalon_slave
 
 # dma interconnect
 
-ad_dma_interconnect axi_dmac_0.m_dest_axi
+ad_dma_interconnect axi_adc_dma.m_dest_axi
 
 #interrupts
 
-ad_cpu_interrupt 4 axi_dmac_0.interrupt_sender
-ad_cpu_interrupt 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
+ad_cpu_interrupt_intel 4 axi_adc_dma.interrupt_sender
+ad_cpu_interrupt_intel 5 ${spi_engine_hier}_axi_regmap.interrupt_sender
diff --git a/projects/ad4052_ardz/de10nano/system_project.tcl b/projects/ad4052_ardz/de10nano/system_project.tcl
index ada0165a62f..5bbe41da23e 100644
--- a/projects/ad4052_ardz/de10nano/system_project.tcl
+++ b/projects/ad4052_ardz/de10nano/system_project.tcl
@@ -7,6 +7,7 @@ set REQUIRED_QUARTUS_VERSION 24.1std.0
 set QUARTUS_PRO_ISUSED 0
 source ../../../scripts/adi_env.tcl
 source ../../scripts/adi_project_intel.tcl
+source $ad_hdl_dir/projects/scripts/adi_board.tcl
 
 adi_project ad4052_ardz_de10nano
 
diff --git a/projects/common/a10gx/a10gx_system_qsys.tcl b/projects/common/a10gx/a10gx_system_qsys.tcl
index 9742770605f..42a5f238010 100644
--- a/projects/common/a10gx/a10gx_system_qsys.tcl
+++ b/projects/common/a10gx/a10gx_system_qsys.tcl
@@ -3,9 +3,6 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
-source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
-
 # a10gx carrier qsys
 set system_type nios
 
@@ -223,19 +220,7 @@ set_connection_parameter_value sys_cpu.instruction_master/sys_flash.uas defaultC
 
 
 
-# cpu/hps handling
-
-proc ad_cpu_interrupt {m_irq m_port} {
-
-  add_connection sys_cpu.irq ${m_port}
-  set_connection_parameter_value sys_cpu.irq/${m_port} irqNumber ${m_irq}
-}
-
-proc ad_cpu_interconnect {m_base m_port} {
-
-  add_connection sys_cpu.data_master ${m_port}
-  set_connection_parameter_value sys_cpu.data_master/${m_port} baseAddress [expr ($m_base + 0x10000000)]
-}
+# carrier-specific cpu/hps handling
 
 proc ad_dma_interconnect {m_port} {
 
diff --git a/projects/common/a10soc/a10soc_system_qsys.tcl b/projects/common/a10soc/a10soc_system_qsys.tcl
index 7128d86cd08..357e46f430e 100644
--- a/projects/common/a10soc/a10soc_system_qsys.tcl
+++ b/projects/common/a10soc/a10soc_system_qsys.tcl
@@ -3,9 +3,6 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
-source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
-
 # a10soc carrier qsys
 set system_type a10soc
 
@@ -194,34 +191,7 @@ set_interface_property sys_hps_ddr_oct EXPORT_OF sys_hps_ddr4_cntrl.oct_conduit_
 add_interface sys_hps_ddr_ref_clk clock sink
 set_interface_property sys_hps_ddr_ref_clk EXPORT_OF sys_hps_ddr4_cntrl.pll_ref_clk_clock_sink
 
-# cpu/hps handling
-
-proc ad_cpu_interrupt {m_irq m_port} {
-
-  add_connection sys_hps.f2h_irq0 ${m_port}
-  set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
-}
-
-proc ad_cpu_interconnect {m_base m_port {avl_bridge ""} {avl_bridge_base 0x00000000} {avl_address_width 18}} {
-
-  if {[string equal ${avl_bridge} ""]} {
-    add_connection sys_hps.h2f_lw_axi_master ${m_port}
-    set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
-  } else {
-    if {[lsearch -exact [get_instances] ${avl_bridge}] == -1} {
-      ## Instantiate the bridge and connect the interfaces
-      add_instance ${avl_bridge} altera_avalon_mm_bridge
-      set_instance_parameter_value ${avl_bridge} {ADDRESS_WIDTH} $avl_address_width
-      set_instance_parameter_value ${avl_bridge} {SYNC_RESET} {1}
-      add_connection sys_hps.h2f_lw_axi_master ${avl_bridge}.s0
-      set_connection_parameter_value sys_hps.h2f_lw_axi_master/${avl_bridge}.s0 baseAddress ${avl_bridge_base}
-      add_connection sys_clk.clk ${avl_bridge}.clk
-      add_connection sys_clk.clk_reset ${avl_bridge}.reset
-    }
-    add_connection ${avl_bridge}.m0 ${m_port}
-    set_connection_parameter_value ${avl_bridge}.m0/${m_port} baseAddress ${m_base}
-  }
-}
+# carrier-specific cpu/hps handling
 
 proc ad_dma_interconnect {m_port} {
 
diff --git a/projects/common/c5soc/c5soc_system_qsys.tcl b/projects/common/c5soc/c5soc_system_qsys.tcl
index 4630960da0e..4864498c8e5 100644
--- a/projects/common/c5soc/c5soc_system_qsys.tcl
+++ b/projects/common/c5soc/c5soc_system_qsys.tcl
@@ -3,9 +3,6 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
-source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
-
 # c5soc carrier qsys
 set system_type c5soc
 
@@ -117,19 +114,7 @@ set_interface_property sys_hps_i2c0_clk EXPORT_OF sys_hps.i2c0_clk
 add_interface sys_hps_i2c0_scl_in clock sink
 set_interface_property sys_hps_i2c0_scl_in EXPORT_OF sys_hps.i2c0_scl_in
 
-# cpu/hps handling
-
-proc ad_cpu_interrupt {m_irq m_port} {
-
-  add_connection sys_hps.f2h_irq0 ${m_port}
-  set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
-}
-
-proc ad_cpu_interconnect {m_base m_port} {
-
-  add_connection sys_hps.h2f_lw_axi_master ${m_port}
-  set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
-}
+# carrier-specific cpu/hps handling
 
 proc ad_dma_interconnect {m_port m_id} {
 
@@ -138,7 +123,7 @@ proc ad_dma_interconnect {m_port m_id} {
     set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram0_data baseAddress {0x0000}
     return
   }
-  
+
   if {${m_id} == 1} {
     add_connection ${m_port} sys_hps.f2h_sdram1_data
     set_connection_parameter_value ${m_port}/sys_hps.f2h_sdram1_data baseAddress {0x0000}
diff --git a/projects/common/de10nano/de10nano_system_qsys.tcl b/projects/common/de10nano/de10nano_system_qsys.tcl
index 378120ae9e5..249633b57a7 100644
--- a/projects/common/de10nano/de10nano_system_qsys.tcl
+++ b/projects/common/de10nano/de10nano_system_qsys.tcl
@@ -3,9 +3,6 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
-source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
-
 # de10nano carrier qsys
 # system clock
 
@@ -125,19 +122,7 @@ set_interface_property sys_hps_i2c1_clk EXPORT_OF sys_hps.i2c1_clk
 add_interface sys_hps_i2c1_scl_in clock sink
 set_interface_property sys_hps_i2c1_scl_in EXPORT_OF sys_hps.i2c1_scl_in
 
-# cpu/hps handling
-
-proc ad_cpu_interrupt {m_irq m_port} {
-
-  add_connection sys_hps.f2h_irq0 ${m_port}
-  set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
-}
-
-proc ad_cpu_interconnect {m_base m_port} {
-
-  add_connection sys_hps.h2f_lw_axi_master ${m_port}
-  set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
-}
+# carrier-specific cpu/hps handling
 
 proc ad_dma_interconnect {m_port} {
 
diff --git a/projects/common/fm87/fm87_system_qsys.tcl b/projects/common/fm87/fm87_system_qsys.tcl
index 6cec89e234c..881bc22ab72 100644
--- a/projects/common/fm87/fm87_system_qsys.tcl
+++ b/projects/common/fm87/fm87_system_qsys.tcl
@@ -3,9 +3,6 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
-source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
-
 # fm87 carrier qsys
 
 set system_type "Agilex 7"
@@ -316,7 +313,7 @@ add_connection hps_m.master sys_hps.f2h_axi_slave
 set_domain_assignment {$system} {qsys_mm.enableEccProtection} {FALSE}
 set_domain_assignment {$system} {qsys_mm.insertDefaultSlave} {FALSE}
 
-# cpu/hps handling
+# carrier-specific  cpu/hps handling
 
 proc ad_dma_interconnect {m_port} {
 
@@ -324,32 +321,6 @@ proc ad_dma_interconnect {m_port} {
     set_connection_parameter_value ${m_port}/sys_hps.f2h_axi_slave baseAddress {0x0}
 }
 
-proc ad_cpu_interrupt {m_irq m_port} {
-
-    add_connection sys_hps.f2h_irq0 ${m_port}
-    set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
-}
-
-proc ad_cpu_interconnect {m_base m_port {avl_bridge ""} {avl_bridge_base 0x00000000} {avl_address_width 18}} {
-  if {[string equal ${avl_bridge} ""]} {
-    add_connection sys_hps.h2f_axi_master ${m_port}
-    set_connection_parameter_value sys_hps.h2f_axi_master/${m_port} baseAddress ${m_base}
-  } else {
-    if {[lsearch -exact [get_instances] ${avl_bridge}] == -1} {
-      ## Instantiate the bridge and connect the interfaces
-      add_instance ${avl_bridge} altera_avalon_mm_bridge
-      set_instance_parameter_value ${avl_bridge} {ADDRESS_WIDTH} $avl_address_width
-      set_instance_parameter_value ${avl_bridge} {SYNC_RESET} {1}
-      add_connection sys_hps.h2f_axi_master ${avl_bridge}.s0
-      set_connection_parameter_value sys_hps.h2f_axi_master/${avl_bridge}.s0 baseAddress ${avl_bridge_base}
-      add_connection sys_clk.clk ${avl_bridge}.clk
-      add_connection sys_clk.clk_reset ${avl_bridge}.reset
-    }
-    add_connection ${avl_bridge}.m0 ${m_port}
-    set_connection_parameter_value ${avl_bridge}.m0/${m_port} baseAddress ${m_base}
-  }
-}
-
 # gpio-bd
 
 add_instance sys_gpio_bd altera_avalon_pio
diff --git a/projects/common/s10soc/s10soc_system_qsys.tcl b/projects/common/s10soc/s10soc_system_qsys.tcl
index ec611869054..2ffb9fe30fd 100644
--- a/projects/common/s10soc/s10soc_system_qsys.tcl
+++ b/projects/common/s10soc/s10soc_system_qsys.tcl
@@ -3,9 +3,6 @@
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-# Intel specific helper proc/ compatibility with xilinx procs on adi_board.tcl
-source $ad_hdl_dir/projects/scripts/adi_board_intel.tcl
-
 # stratix10soc carrier qsys
 
 set system_type s10soc
@@ -239,34 +236,7 @@ set_interface_property sys_hps_ddr_oct EXPORT_OF sys_hps_ddr4_cntrl.oct
 add_interface sys_hps_ddr_ref_clk clock sink
 set_interface_property sys_hps_ddr_ref_clk EXPORT_OF sys_hps_ddr4_cntrl.pll_ref_clk
 
-# cpu/hps handling
-
-proc ad_cpu_interrupt {m_irq m_port} {
-
-  add_connection sys_hps.f2h_irq0 ${m_port}
-  set_connection_parameter_value sys_hps.f2h_irq0/${m_port} irqNumber ${m_irq}
-}
-
-proc ad_cpu_interconnect {m_base m_port {avl_bridge ""} {avl_bridge_base 0x00000000} {avl_address_width 18}} {
-
-  if {[string equal ${avl_bridge} ""]} {
-    add_connection sys_hps.h2f_lw_axi_master ${m_port}
-    set_connection_parameter_value sys_hps.h2f_lw_axi_master/${m_port} baseAddress ${m_base}
-  } else {
-    if {[lsearch -exact [get_instances] ${avl_bridge}] == -1} {
-      ## Instantiate the bridge and connect the interfaces
-      add_instance ${avl_bridge} altera_avalon_mm_bridge
-      set_instance_parameter_value ${avl_bridge} {ADDRESS_WIDTH} $avl_address_width
-      set_instance_parameter_value ${avl_bridge} {SYNC_RESET} {1}
-      add_connection sys_hps.h2f_lw_axi_master ${avl_bridge}.s0
-      set_connection_parameter_value sys_hps.h2f_lw_axi_master/${avl_bridge}.s0 baseAddress ${avl_bridge_base}
-      add_connection sys_clk.clk ${avl_bridge}.clk
-      add_connection sys_clk.clk_reset ${avl_bridge}.reset
-    }
-    add_connection ${avl_bridge}.m0 ${m_port}
-    set_connection_parameter_value ${avl_bridge}.m0/${m_port} baseAddress ${m_base}
-  }
- }
+# carrier-specific  cpu/hps handling
 
 ## Connect the memory mapped interface of an ADI DMAC to the hps.f2sdram0 interface
 #  Use an altera_axi_bridge to isolate the bridging logic, which will be generated
diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl
index 614c821d7c4..2447d8fe855 100644
--- a/projects/scripts/adi_board.tcl
+++ b/projects/scripts/adi_board.tcl
@@ -21,6 +21,18 @@ set xcvr_instance NONE
 
 set use_smartconnect 1
 
+proc ad_detect_vendor {} {
+  if {[info commands get_bd_cells] != ""} {
+    return "xilinx"
+  }
+  if {[info commands add_instance] != ""} {
+    return "intel"
+  }
+  # Default to xilinx for backward compatibility
+  return "xilinx"
+}
+
+
 ## Add an instance of an IP or inline_hdl to the block design.
 #
 # \param[i_ip] - name of the IP
@@ -29,6 +41,18 @@ set use_smartconnect 1
 # pairs
 #
 proc ad_ip_instance {i_ip i_name {i_params {}}} {
+
+  set vendor [ad_detect_vendor]
+  if {$vendor == "xilinx"} {
+    ad_ip_instance_xilinx $i_ip $i_name $i_params
+  } elseif {$vendor == "intel"} {
+    ad_ip_instance_intel $i_ip $i_name $i_params
+  }
+}
+
+## Add an instance of an IP or inline_hdl to the block design (Xilinx implementation).
+proc ad_ip_instance_xilinx {i_ip i_name {i_params {}}} {
+
   set ip_type ip
   set ip_def [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
     design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""]
@@ -46,6 +70,17 @@ proc ad_ip_instance {i_ip i_name {i_params {}}} {
   }
 }
 
+## Add an instance of an IP to the block design (Intel implementation).
+proc ad_ip_instance_intel {i_ip i_name {i_params {}}} {
+  add_instance ${i_name} ${i_ip}
+  # Set parameters if provided
+  if {$i_params != {}} {
+    foreach {k v} $i_params {
+      set_instance_parameter_value ${i_name} $k $v
+    }
+  }
+}
+
 ## Define a parameter value of an IP instance.
 #
 # \param[i_name] - name of the instance
@@ -53,8 +88,14 @@ proc ad_ip_instance {i_ip i_name {i_params {}}} {
 # \param[i_value] - value of the parameter
 #
 proc ad_ip_parameter {i_name i_param i_value} {
-
-  set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
+  set vendor [ad_detect_vendor]
+  if {$vendor == "xilinx"} {
+    set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
+  } elseif {$vendor == "intel"} {
+    # Remove CONFIG. prefix if present for Intel
+    regsub {^CONFIG\.} $i_param {} param_name
+    set_instance_parameter_value ${i_name} ${param_name} ${i_value}
+  }
 }
 
 ## Define the type of an IPI interface object, in general these objects an be:
@@ -158,7 +199,7 @@ proc ad_connect_int_width {obj} {
 }
 
 
-## Connect two IPI interface object together.
+## Connect two IPI/Platform Designer interface objects together.
 #
 # \param[p_name_1] - first object name
 # \param[p_name_2] - second object name
@@ -168,6 +209,16 @@ proc ad_connect_int_width {obj} {
 # \return - N/A
 #
 proc ad_connect {name_a name_b} {
+  set vendor [ad_detect_vendor]
+  if {$vendor == "xilinx"} {
+    ad_connect_xilinx $name_a $name_b
+  } elseif {$vendor == "intel"} {
+    ad_connect_intel $name_a $name_b
+  }
+}
+
+## Connect two IPI interface objects together. (Xilinx implementation)
+proc ad_connect_xilinx {name_a name_b} {
   set type_a [ad_connect_int_class $name_a]
   set type_b [ad_connect_int_class $name_b]
 
@@ -255,7 +306,13 @@ proc ad_connect {name_a name_b} {
   puts "connect_bd_net [get_bd_pin $cell/dout] $obj_b"
 }
 
-## Disconnect two IPI interface object together.
+## Connect two Platform Designer interface objects together. (Intel implementation)
+proc ad_connect_intel {name_a name_b} {
+
+    add_connection $name_a $name_b
+}
+
+## Disconnect two IPI interface objects.
 #
 # \param[p_name_1] - first object name
 # \param[p_name_2] - second object name
@@ -1204,6 +1261,39 @@ proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
   }
 }
 
+proc ad_cpu_interconnect_intel {m_base m_port {avl_bridge ""} {avl_bridge_base 0x00000000} {avl_address_width 18}} {
+
+  global sys_intel_soc
+
+  if {$sys_intel_soc == 0} { # a10gx only
+    set soc_master sys_cpu
+    set soc_port   data_master
+    set soc_base   0x10000000
+  } elseif {$sys_intel_soc == 1} {
+    set soc_master sys_hps
+    set soc_port   h2f_lw_axi_master
+    set soc_base   0x00000000
+  }
+
+  if {[string equal ${avl_bridge} ""]} {
+    add_connection $soc_master.$soc_port ${m_port}
+    set_connection_parameter_value $soc_master.$soc_port/${m_port} baseAddress [expr ($m_base + $soc_base)]
+  } else {
+    if {[lsearch -exact [get_instances] ${avl_bridge}] == -1} {
+      ## Instantiate the bridge and connect the interfaces
+      add_instance ${avl_bridge} altera_avalon_mm_bridge
+      set_instance_parameter_value ${avl_bridge} {ADDRESS_WIDTH} $avl_address_width
+      set_instance_parameter_value ${avl_bridge} {SYNC_RESET} {1}
+      add_connection $soc_master.$soc_port ${avl_bridge}.s0
+      set_connection_parameter_value $soc_master.$soc_port/${avl_bridge}.s0 baseAddress ${avl_bridge_base}
+      add_connection sys_clk.clk ${avl_bridge}.clk
+      add_connection sys_clk.clk_reset ${avl_bridge}.reset
+    }
+    add_connection ${avl_bridge}.m0 ${m_port}
+    set_connection_parameter_value ${avl_bridge}.m0/${m_port} baseAddress ${m_base}
+  }
+}
+
 ## Connects an IP interrupt port to the system's interrupt controller interface.
 #
 #  \param[p_ps_index] - interrupt index used in PSx based architecture
@@ -1255,3 +1345,19 @@ proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
     ad_connect sys_concat_intc/In$p_index $p_name
   }
 }
+
+proc ad_cpu_interrupt_intel {m_irq m_port} {
+
+  global sys_intel_soc
+
+  if {$sys_intel_soc == 0} { # a10gx only
+    set soc_master  sys_cpu
+    set soc_irq     irq
+  } elseif {$sys_intel_soc == 1} {
+    set soc_master  sys_hps
+    set soc_irq     f2h_irq0
+  }
+
+    add_connection $soc_master.$soc_irq ${m_port}
+    set_connection_parameter_value $soc_master.$soc_irq/${m_port} irqNumber ${m_irq}
+}
diff --git a/projects/scripts/adi_board_intel.tcl b/projects/scripts/adi_board_intel.tcl
deleted file mode 100644
index 7ecc889a371..00000000000
--- a/projects/scripts/adi_board_intel.tcl
+++ /dev/null
@@ -1,26 +0,0 @@
-###############################################################################
-## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
-### SPDX short identifier: ADIBSD
-###############################################################################
-
-proc ad_ip_instance {i_ip i_name {i_params {}}} {
-  add_instance ${i_name} ${i_ip}
-  # Set parameters if provided
-  if {$i_params != {}} {
-    foreach {k v} $i_params {
-      set_instance_parameter_value ${i_name} $k $v
-    }
-  }
-}
-
-proc ad_ip_parameter {i_name i_param i_value} {
-
-    # Remove CONFIG. prefix if present for Intel
-    regsub {^CONFIG\.} $i_param {} param_name
-    set_instance_parameter_value ${i_name} ${param_name} ${i_value}
-}
-
-proc ad_connect {name_a name_b} {
-
-    add_connection $name_a $name_b
-}
diff --git a/projects/scripts/adi_project_intel.tcl b/projects/scripts/adi_project_intel.tcl
index 61d5a946e1a..a006af728c3 100644
--- a/projects/scripts/adi_project_intel.tcl
+++ b/projects/scripts/adi_project_intel.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2017-2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -13,7 +13,7 @@ set device "none"
 # \param[parameter_list] - a list of global parameters (parameters of the
 # system_top module)
 #
-# Supported carrier names are: a10gx, a10soc, c5soc, de10nano, a5soc, a5gt.
+# Supported carrier names are: a10gx, a10soc, c5soc, de10nano, s10soc, fm87
 #
 proc adi_project {project_name {parameter_list {}}} {
 
@@ -21,6 +21,7 @@ proc adi_project {project_name {parameter_list {}}} {
   global ad_ghdl_dir
   global family
   global device
+  global sys_intel_soc
   global REQUIRED_QUARTUS_VERSION
   global quartus
   global IGNORE_VERSION_CHECK
@@ -52,45 +53,40 @@ proc adi_project {project_name {parameter_list {}}} {
   if [regexp "_a10gx" $project_name] {
     set family "Arria 10"
     set device 10AX115S2F45I1SG
+    # a10gx alone uses nios
+    set sys_intel_soc 0
   }
 
   if [regexp "_a10soc" $project_name] {
     set family "Arria 10"
     set device 10AS066N3F40E2SG
+    set sys_intel_soc 1
   }
 
   if [regexp "_s10soc" $project_name] {
     set family "Stratix 10"
     set device 1SX280HU2F50E1VGAS
+    set sys_intel_soc 1
   }
 
   if [regexp "_c5soc" $project_name] {
     set family "Cyclone V"
     set device 5CSXFC6D6F31C8ES
+    set sys_intel_soc 1
     set system_qip_file ${ad_project_dir}/system_bd/synthesis/system_bd.qip
   }
 
   if [regexp "_de10nano" $project_name] {
     set family "Cyclone V"
     set device 5CSEBA6U23I7DK
-    set system_qip_file ${ad_project_dir}/system_bd/synthesis/system_bd.qip
-  }
-
-  if [regexp "_a5soc" $project_name] {
-    set family "Arria V"
-    set device 5ASTFD5K3F40I3ES
-    set system_qip_file ${ad_project_dir}/system_bd/synthesis/system_bd.qip
-  }
-
-  if [regexp "_a5gt" $project_name] {
-    set family "Arria V"
-    set device 5AGTFD7K3F40I3
+    set sys_intel_soc 1
     set system_qip_file ${ad_project_dir}/system_bd/synthesis/system_bd.qip
   }
 
   if [regexp "fm87" $project_name] {
     set family "Agilex 7"
     set device AGIB027R31B1E1V
+    set sys_intel_soc 1
     set system_qip_file ${ad_project_dir}/system_bd/synthesis/system_bd.qip
   }
 
diff --git a/projects/scripts/project-intel.mk b/projects/scripts/project-intel.mk
index 15027ce4a99..28e7c74f906 100644
--- a/projects/scripts/project-intel.mk
+++ b/projects/scripts/project-intel.mk
@@ -101,6 +101,7 @@ M_DEPS += system_constr.sdc
 M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_tquest.tcl
 M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_project_intel.tcl
 M_DEPS += $(HDL_PROJECT_PATH)../scripts/adi_env.tcl
+M_DEPS += $(HDL_PROJECT_PATH)scripts/adi_board.tcl
 
 M_DEPS += $(foreach dep,$(LIB_DEPS),$(HDL_LIBRARY_PATH)$(dep)/.timestamp_intel)