diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/Makefile b/library/intel/jesd204c/jesd204_f_tile_adapter_rx/Makefile
index 2e81c080c15..1c5decca141 100644
--- a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/Makefile
+++ b/library/intel/jesd204c/jesd204_f_tile_adapter_rx/Makefile
@@ -8,8 +8,8 @@ LIBRARY_NAME := jesd204_f_tile_adapter_rx
 
 INTEL_DEPS += ../../../util_cdc/sync_bits.v
 INTEL_DEPS += ../../../jesd204/jesd204_common/sync_header_align.v
-INTEL_DEPS += bitslip.v
-INTEL_DEPS += gearbox_64b66b.v
+INTEL_DEPS += ../../../jesd204/jesd204_common/bitslip.v
+INTEL_DEPS += ../../../jesd204/jesd204_common/gearbox_64b66b.v
 INTEL_DEPS += jesd204_f_tile_adapter_rx.v
 INTEL_DEPS += jesd204_f_tile_adapter_rx_constr.sdc
 
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx_hw.tcl b/library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx_hw.tcl
index 582985f7c97..02ba1bd86f6 100644
--- a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx_hw.tcl
+++ b/library/intel/jesd204c/jesd204_f_tile_adapter_rx/jesd204_f_tile_adapter_rx_hw.tcl
@@ -19,8 +19,8 @@ ad_ip_parameter DEVICE STRING "Agilex 7" false
 ad_ip_files jesd204_f_tile_adapter_rx [list \
   $ad_hdl_dir/library/util_cdc/sync_bits.v \
   $ad_hdl_dir/library/jesd204/jesd204_common/sync_header_align.v \
-  bitslip.v \
-  gearbox_64b66b.v \
+  $ad_hdl_dir/library/jesd204/jesd204_common/bitslip.v \
+  $ad_hdl_dir/library/jesd204/jesd204_common/gearbox_64b66b.v \
   jesd204_f_tile_adapter_rx.v \
   jesd204_f_tile_adapter_rx_constr.sdc \
 ]
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/Makefile b/library/intel/jesd204c/jesd204_f_tile_adapter_tx/Makefile
index bba3e6ea5d2..82527ca0b61 100644
--- a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/Makefile
+++ b/library/intel/jesd204c/jesd204_f_tile_adapter_tx/Makefile
@@ -7,7 +7,7 @@
 LIBRARY_NAME := jesd204_f_tile_adapter_tx
 
 INTEL_DEPS += ../../../util_cdc/sync_bits.v
-INTEL_DEPS += gearbox_66b64b.v
+INTEL_DEPS += ../../../jesd204/jesd204_common/gearbox_66b64b.v
 INTEL_DEPS += jesd204_f_tile_adapter_tx.v
 INTEL_DEPS += jesd204_f_tile_adapter_tx_constr.sdc
 
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx_hw.tcl b/library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx_hw.tcl
index ec3850e3460..67e3217e2b7 100644
--- a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx_hw.tcl
+++ b/library/intel/jesd204c/jesd204_f_tile_adapter_tx/jesd204_f_tile_adapter_tx_hw.tcl
@@ -18,7 +18,7 @@ ad_ip_parameter DEVICE STRING "Agilex 7" false
 
 ad_ip_files jesd204_f_tile_adapter_tx [list \
   $ad_hdl_dir/library/util_cdc/sync_bits.v \
-  gearbox_66b64b.v \
+  $ad_hdl_dir/library/jesd204/jesd204_common/gearbox_66b64b.v \
   jesd204_f_tile_adapter_tx.v \
   jesd204_f_tile_adapter_tx_constr.sdc \
 ]
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/bitslip.v b/library/jesd204/jesd204_common/bitslip.v
similarity index 100%
rename from library/intel/jesd204c/jesd204_f_tile_adapter_rx/bitslip.v
rename to library/jesd204/jesd204_common/bitslip.v
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_rx/gearbox_64b66b.v b/library/jesd204/jesd204_common/gearbox_64b66b.v
similarity index 100%
rename from library/intel/jesd204c/jesd204_f_tile_adapter_rx/gearbox_64b66b.v
rename to library/jesd204/jesd204_common/gearbox_64b66b.v
diff --git a/library/intel/jesd204c/jesd204_f_tile_adapter_tx/gearbox_66b64b.v b/library/jesd204/jesd204_common/gearbox_66b64b.v
similarity index 100%
rename from library/intel/jesd204c/jesd204_f_tile_adapter_tx/gearbox_66b64b.v
rename to library/jesd204/jesd204_common/gearbox_66b64b.v
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile b/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile
index 6979a6606ff..a1a713654c6 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/Makefile
@@ -8,8 +8,13 @@ LIBRARY_NAME := jesd204_versal_gt_adapter_rx
 
 GENERIC_DEPS += jesd204_versal_gt_adapter_rx.v
 GENERIC_DEPS += lane_align.v
+GENERIC_DEPS += ../jesd204_common/sync_header_align.v
+GENERIC_DEPS += ../jesd204_common/gearbox_64b66b.v
+GENERIC_DEPS += ../jesd204_common/bitslip.v
+GENERIC_DEPS += ../jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v
+GENERIC_DEPS += ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v
+GENERIC_DEPS += ../jesd204_soft_pcs_rx/jesd204_pattern_align.v
 
-XILINX_DEPS += ../jesd204_common/sync_header_align.v
 XILINX_DEPS += jesd204_versal_gt_adapter_rx_ip.tcl
 
 include ../../scripts/library.mk
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
index f49278fd2f8..3f86e204317 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2017, 2018, 2020-2022, 2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2017, 2018, 2020-2022, 2024-2026 Analog Devices, Inc. All rights reserved.
 // SPDX short identifier: ADIJESD204
 // ***************************************************************************
 // ***************************************************************************
@@ -8,6 +8,7 @@
 `timescale 1ns/100ps
 
 module  jesd204_versal_gt_adapter_rx #(
+  parameter TRANSCEIVER = "GTY",
   parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
 ) (
   // Interface to Physical Layer
@@ -21,83 +22,236 @@ module  jesd204_versal_gt_adapter_rx #(
   input  [  1 : 0] rxheadervalid,
   output           rxslide,
 
+  input            phy_clk,
+  input            phy_rstn,
+
   // Interface to Link layer core
-  output [ 63 : 0]  rx_data,
-  output [  3 : 0]  rx_charisk,
-  output [  3 : 0]  rx_disperr,
-  output [  3 : 0]  rx_notintable,
-  output [  1 : 0]  rx_header,
-  output            rx_block_sync,
-  input             en_char_align,
-
-  input             usr_clk
+  output [ 63 : 0] rx_data,
+  output [  3 : 0] rx_charisk,
+  output [  3 : 0] rx_disperr,
+  output [  3 : 0] rx_notintable,
+  output [  1 : 0] rx_header,
+  output           rx_block_sync,
+  input            en_char_align,
+
+  input            usr_clk
 );
 
-  reg [63:0] rxdata_d;
-  reg [ 1:0] rxheader_d;
-  reg        rxgearboxslip_d;
-  reg [ 1:0] rxheadervalid_d;
-  reg [15:0] rxctrl0_d;
-  reg [15:0] rxctrl1_d;
-  reg [ 7:0] rxctrl3_d;
-  wire       rxgearboxslip_s;
-
-  always @(posedge usr_clk) begin
-    rxdata_d <= rxdata[63:0];
-    rxheader_d <= rxheader[1:0];
-    rxgearboxslip_d <= rxgearboxslip_s;
-    rxheadervalid_d <= rxheadervalid;
-    rxctrl0_d <= rxctrl0;
-    rxctrl1_d <= rxctrl1;
-    rxctrl3_d <= rxctrl3;
-  end
+  wire i_reset;
+  wire o_reset;
 
-  generate if (LINK_MODE == 2) begin
-    // Sync header alignment
-    wire rx_bitslip_req_s;
-    reg [5:0] rx_bitslip_done_cnt = 'h0;
-    always @(posedge usr_clk) begin
-      if (rx_bitslip_done_cnt[5]) begin
-        rx_bitslip_done_cnt <= 'b0;
-      end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin
-        rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(1)
+  ) i_sync_i_reset (
+    .in_bits(~phy_rstn),
+    .out_clk(phy_clk),
+    .out_resetn(1'b1),
+    .out_bits(i_reset));
+
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(1)
+  ) i_sync_o_reset (
+    .in_bits(~phy_rstn),
+    .out_clk(usr_clk),
+    .out_resetn(1'b1),
+    .out_bits(o_reset));
+
+  generate if (TRANSCEIVER == "GTM") begin
+    if (LINK_MODE == 2) begin
+      reg  [63:0] i_data;
+      wire        rd_rst_busy;
+      wire        wr_rst_busy;
+      wire        fifo_wr_en;
+      wire        i_fifo_full;
+      wire [65:0] fifo_rd_data;
+      wire        fifo_rd_en;
+      wire        fifo_empty;
+
+      wire [65:0] i_gb_data;
+      wire        i_gb_valid;
+
+      wire [63:0] o_data_aligned;
+      wire [ 1:0] o_header_aligned;
+      wire [63:0] o_data_rev;
+      wire [ 1:0] o_header_rev;
+      wire        o_bitslip;
+      wire        o_bitslip_done;
+
+      always @(posedge phy_clk) begin
+        i_data <= rxdata[63:0];
       end
-    end
 
-    reg rx_bitslip_req_s_d = 1'b0;
-    always @(posedge usr_clk) begin
-      rx_bitslip_req_s_d <= rx_bitslip_req_s;
-    end
+      gearbox_64b66b i_gearbox (
+        .clk (phy_clk),
+        .reset (i_reset),
+        .i_data (i_data),
+        .o_data (i_gb_data),
+        .o_valid (i_gb_valid));
 
-    assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
-    assign rxgearboxslip = rxgearboxslip_d;
+      // CDC from LR / 64 to LR / 66
+      assign fifo_wr_en = i_gb_valid & ~i_fifo_full & ~wr_rst_busy;
+      assign fifo_rd_en = ~fifo_empty & ~rd_rst_busy;
 
-    wire [63:0] rxdata_flip;
-    wire [ 1:0] rxheader_flip;
-    genvar i;
-    for (i = 0; i < 64; i=i+1) begin
-      assign rxdata_flip[63-i] = rxdata_d[i];
-    end
-    assign rxheader_flip = {rxheader_d[0], rxheader_d[1]};
-
-    // Sync header alignment
-    sync_header_align i_sync_header_align (
-      .clk(usr_clk),
-      .reset(~rxheadervalid_d[0]),
-      // Flip header bits and data
-      .i_data({rxheader_flip, rxdata_flip}),
-      .i_slip(rx_bitslip_req_s),
-      .i_slip_done(rx_bitslip_done_cnt[5]),
-      .o_data(rx_data),
-      .o_header(rx_header),
-      .o_block_sync(rx_block_sync));
+      xpm_fifo_async #(
+        .CASCADE_HEIGHT(0),
+        .CDC_SYNC_STAGES(2),
+        .DOUT_RESET_VALUE("0"),
+        .ECC_MODE("no_ecc"),
+        .EN_SIM_ASSERT_ERR("warning"),
+        .FIFO_MEMORY_TYPE("auto"),
+        .FIFO_READ_LATENCY(1),
+        .FIFO_WRITE_DEPTH(32),
+        .FULL_RESET_VALUE(0),
+        .PROG_EMPTY_THRESH(10),
+        .PROG_FULL_THRESH(10),
+        .RD_DATA_COUNT_WIDTH(1),
+        .READ_DATA_WIDTH(66),
+        .READ_MODE("std"),
+        .RELATED_CLOCKS(0),
+        .SIM_ASSERT_CHK(0),
+        .USE_ADV_FEATURES("0707"),
+        .WAKEUP_TIME(0),
+        .WRITE_DATA_WIDTH(66),
+        .WR_DATA_COUNT_WIDTH(1)
+      ) i_async_fifo (
+        .sleep (1'b0),
+        .injectdbiterr (1'b0),
+        .injectsbiterr (1'b0),
+        .rd_rst_busy (rd_rst_busy),
+        .rd_clk (usr_clk),
+        .rd_en (fifo_rd_en),
+        .dout (fifo_rd_data),
+        .empty (fifo_empty),
+        .wr_rst_busy (wr_rst_busy),
+        .wr_clk (phy_clk),
+        .wr_en (fifo_wr_en),
+        .din (i_gb_data),
+        .full (i_fifo_full),
+        .rst (i_reset));
+
+      // In LR / 66 domain
+      bitslip i_bitslip (
+        .clk (usr_clk),
+        .reset (o_reset),
+        .bitslip (o_bitslip),
+        .data_in (fifo_rd_data),
+        .bitslip_done (o_bitslip_done),
+        .data_out ({o_data_aligned, o_header_aligned}));
+
+      genvar i;
+      for (i=0; i < 64; i=i+1) begin
+        assign o_data_rev[63-i] = o_data_aligned[i];
+      end
+      assign o_header_rev = {o_header_aligned[0], o_header_aligned[1]};
+
+      sync_header_align i_header_align (
+        .clk (usr_clk),
+        .reset (o_reset),
+        .i_data ({o_header_rev, o_data_rev}),
+        .i_slip (o_bitslip),
+        .i_slip_done (o_bitslip_done),
+        .o_data (rx_data),
+        .o_header (rx_header),
+        .o_block_sync (rx_block_sync));
 
       assign rx_disperr    = 4'b0;
       assign rx_charisk    = 4'b0;
       assign rx_notintable = 4'b0;
       assign rxslide       = 1'b0;
+      assign rxgearboxslip = 1'b0;
     end else begin
-      assign rx_data       = {32'b0, rxdata_d[31:0]};
+      wire [31:0] rx_data_pcs;
+
+      jesd204_soft_pcs_rx #(
+        .NUM_LANES (1),
+        .DATA_PATH_WIDTH (4),
+        .REGISTER_INPUTS (1),
+        .INVERT_INPUTS (0),
+        .IFC_TYPE (0)
+      ) i_jesd204_soft_pcs_rx (
+        .clk (usr_clk),
+        .reset (o_reset),
+        .patternalign_en (en_char_align),
+        .data (rxdata[39:0]),
+        .char (rx_data_pcs),
+        .charisk (rx_charisk),
+        .notintable (rx_notintable),
+        .disperr (rx_disperr));
+
+      assign rx_data       = {32'b0, rx_data_pcs};
+      assign rx_block_sync = 'b0;
+      assign rx_header     = 2'b00;
+      assign rxslide       = 1'b0;
+      assign rxgearboxslip = 1'b0;
+    end
+  end else begin
+    reg [63:0] rxdata_d;
+    reg [ 1:0] rxheader_d;
+    reg        rxgearboxslip_d;
+    reg [ 1:0] rxheadervalid_d;
+    reg [15:0] rxctrl0_d;
+    reg [15:0] rxctrl1_d;
+    reg [ 7:0] rxctrl3_d;
+    wire       rxgearboxslip_s;
+
+    always @(posedge usr_clk) begin
+      rxdata_d <= rxdata[63:0];
+      rxheader_d <= rxheader[1:0];
+      rxgearboxslip_d <= rxgearboxslip_s;
+      rxheadervalid_d <= rxheadervalid;
+      rxctrl0_d <= rxctrl0;
+      rxctrl1_d <= rxctrl1;
+      rxctrl3_d <= rxctrl3;
+    end
+
+    if (LINK_MODE == 2) begin
+      // Sync header alignment
+      wire rx_bitslip_req_s;
+      reg [5:0] rx_bitslip_done_cnt = 'h0;
+      always @(posedge usr_clk) begin
+        if (rx_bitslip_done_cnt[5]) begin
+          rx_bitslip_done_cnt <= 'b0;
+        end else if (rx_bitslip_req_s & ~rx_bitslip_done_cnt[5]) begin
+          rx_bitslip_done_cnt <= rx_bitslip_done_cnt + 1;
+        end
+      end
+
+      reg rx_bitslip_req_s_d = 1'b0;
+      always @(posedge usr_clk) begin
+        rx_bitslip_req_s_d <= rx_bitslip_req_s;
+      end
+
+      assign rxgearboxslip_s = rx_bitslip_req_s & ~rx_bitslip_req_s_d;
+      assign rxgearboxslip = rxgearboxslip_d;
+
+      wire [63:0] rxdata_flip;
+      wire [ 1:0] rxheader_flip;
+      genvar i;
+      for (i = 0; i < 64; i=i+1) begin
+        assign rxdata_flip[63-i] = rxdata_d[i];
+      end
+      assign rxheader_flip = {rxheader_d[0], rxheader_d[1]};
+
+      // Sync header alignment
+      sync_header_align i_sync_header_align (
+        .clk(usr_clk),
+        .reset(~rxheadervalid_d[0]),
+        // Flip header bits and data
+        .i_data({rxheader_flip, rxdata_flip}),
+        .i_slip(rx_bitslip_req_s),
+        .i_slip_done(rx_bitslip_done_cnt[5]),
+        .o_data(rx_data),
+        .o_header(rx_header),
+        .o_block_sync(rx_block_sync));
+
+        assign rx_disperr    = 4'b0;
+        assign rx_charisk    = 4'b0;
+        assign rx_notintable = 4'b0;
+        assign rxslide       = 1'b0;
+    end else begin
+      assign rx_data       = {32'd0, rxdata_d[31:0]};
       assign rx_header     = rxheader_d[1:0];
 
       assign rx_charisk    = rxctrl0_d[3:0];
@@ -112,6 +266,7 @@ module  jesd204_versal_gt_adapter_rx #(
         .rx_slide (rxslide),
         .en_char_align (en_char_align));
     end
+  end
   endgenerate
 
 endmodule
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_constr.ttcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_constr.ttcl
new file mode 100644
index 00000000000..d0e0d87d536
--- /dev/null
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_constr.ttcl
@@ -0,0 +1,41 @@
+###############################################################################
+## Copyright (C) 2026 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+
+set usr_clk [get_clocks -of_objects [get_ports -quiet {usr_clk}]]
+set phy_clk [get_clocks -of_objects [get_ports -quiet {phy_clk}]]
+
+# sync bits i_reset
+set_false_path \
+  -from $phy_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+# sync bits o_reset
+set_false_path \
+  -from $usr_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
index 97e945cbd03..ed816d902a0 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2017-2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIJESD204
 ###############################################################################
 
@@ -11,9 +11,19 @@ adi_ip_files jesd204_versal_gt_adapter_rx [list \
   jesd204_versal_gt_adapter_rx.v \
   lane_align.v \
   ../jesd204_common/sync_header_align.v \
-  ]
+  ../jesd204_common/gearbox_64b66b.v \
+  ../jesd204_common/bitslip.v \
+  ../jesd204_soft_pcs_rx/jesd204_soft_pcs_rx.v \
+  ../jesd204_soft_pcs_rx/jesd204_8b10b_decoder.v \
+  ../jesd204_soft_pcs_rx/jesd204_pattern_align.v \
+  $ad_hdl_dir/library/util_cdc/sync_bits.v \
+  jesd204_versal_gt_adapter_rx_constr.ttcl \
+  jesd204_versal_gt_adapter_rx_ooc.ttcl \
+]
 
 adi_ip_properties_lite jesd204_versal_gt_adapter_rx
+adi_ip_ttcl jesd204_versal_gt_adapter_rx "jesd204_versal_gt_adapter_rx_constr.ttcl"
+adi_ip_ttcl jesd204_versal_gt_adapter_rx "jesd204_versal_gt_adapter_rx_ooc.ttcl"
 
 set_property display_name "ADI JESD204 Versal Transceiver Rx Lane Adapter" [ipx::current_core]
 set_property description "ADI JESD204 Versal Transceiver Rx Lane Adapter" [ipx::current_core]
@@ -45,4 +55,23 @@ adi_add_bus "RX_GT_IP_Interface" "master" \
    { "rxgearboxslip" "ch_rxgearboxslip" } \
   }
 
+set_property -dict [list \
+  value_validation_type list \
+  value_validation_list {GTY GTYP GTM} \
+] [ipx::get_user_parameters TRANSCEIVER -of_objects [ipx::current_core]]
+
+set_property -dict [list \
+  value_validation_type pairs \
+  value_validation_pairs {64B66B 2 8B10B 1} \
+] [ipx::get_user_parameters LINK_MODE -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {$LINK_MODE == 1} \
+  [ipx::get_ports en_char_align -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {$TRANSCEIVER == "GTM" && $LINK_MODE == 2} \
+  [ipx::get_ports phy_clk -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {$TRANSCEIVER == "GTM"} \
+  [ipx::get_ports phy_rstn -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ooc.ttcl b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ooc.ttcl
new file mode 100644
index 00000000000..48a4f94dce6
--- /dev/null
+++ b/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ooc.ttcl
@@ -0,0 +1,21 @@
+###############################################################################
+## Copyright (C) 2026 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name usr_clk -period 2.5000 [get_ports usr_clk]
+create_clock -name phy_clk -period 2.4242 [get_ports phy_clk]
+
+################################################################################
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile b/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile
index 0baea0f93e9..12dd475e3e0 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/Makefile
@@ -7,6 +7,9 @@
 LIBRARY_NAME := jesd204_versal_gt_adapter_tx
 
 GENERIC_DEPS += jesd204_versal_gt_adapter_tx.v
+GENERIC_DEPS += ../jesd204_common/gearbox_66b64b.v
+GENERIC_DEPS += ../jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v
+GENERIC_DEPS += ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v
 
 XILINX_DEPS += jesd204_versal_gt_adapter_tx_ip.tcl
 
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
index 0f71804d0fb..6d1788bd691 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2017-2019, 2021, 2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2017-2019, 2021, 2024-2026 Analog Devices, Inc. All rights reserved.
 // SPDX short identifier: ADIJESD204
 // ***************************************************************************
 // ***************************************************************************
@@ -8,6 +8,7 @@
 `timescale 1ns/100ps
 
 module  jesd204_versal_gt_adapter_tx #(
+  parameter TRANSCEIVER = "GTY",
   parameter LINK_MODE = 2 // 1 - 8B10B, 2 - 64B66B
 ) (
   output  [127 : 0] txdata,
@@ -15,6 +16,10 @@ module  jesd204_versal_gt_adapter_tx #(
   output  [ 15 : 0] txctrl0,
   output  [ 15 : 0] txctrl1,
   output  [  7 : 0] txctrl2,
+
+  input             phy_clk,
+  input             phy_rstn,
+
   // Interface to Link layer core
   input   [ 63 : 0] tx_data,
   input   [  1 : 0] tx_header,
@@ -22,39 +27,180 @@ module  jesd204_versal_gt_adapter_tx #(
 
   input             usr_clk
 );
+  wire i_reset;
+  wire o_reset;
 
-  reg [63:0]   txdata_d;
-  reg [ 1:0]   txheader_d;
-  reg [ 3:0]   txcharisk_d;
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(1)
+  ) i_sync_i_reset (
+    .in_bits(~phy_rstn),
+    .out_clk(phy_clk),
+    .out_resetn(1'b1),
+    .out_bits(i_reset));
 
-  always @(posedge usr_clk) begin
-    txdata_d <= tx_data;
-    txheader_d <= tx_header;
-    txcharisk_d <= tx_charisk;
-  end
+  sync_bits #(
+    .NUM_OF_BITS(1),
+    .ASYNC_CLK(1)
+  ) i_sync_o_reset (
+    .in_bits(~phy_rstn),
+    .out_clk(usr_clk),
+    .out_resetn(1'b1),
+    .out_bits(o_reset));
 
-  generate if (LINK_MODE == 2) begin
-    wire [63:0] tx_data_flip;
-    wire [ 1:0] tx_header_flip;
-    genvar i;
-    for (i = 0; i < 64; i=i+1) begin
-      assign tx_data_flip[63-i] = txdata_d[i];
-    end
-    assign tx_header_flip = {txheader_d[0], txheader_d[1]};
+  generate if (TRANSCEIVER == "GTM") begin
+    if (LINK_MODE == 2) begin
+      wire        i_fifo_empty;
+      wire        i_gb_read;
+      wire [63:0] o_gb_data;
+
+      wire        o_fifo_full;
+      reg  [63:0] o_phy_data_r;
+      reg  [ 1:0] o_phy_header_r;
+      wire [63:0] o_phy_data_rev;
+      wire [ 1:0] o_phy_header_rev;
+
+      wire         wr_rst_busy;
+      wire         rd_rst_busy;
+      wire  [65:0] rd_data;
+
+      wire  [65:0] wr_data;
+      wire         wr_en;
+      wire         rd_en;
+
+      reg   [63:0] txdata_d;
+
+      // Register the input data to ease timing
+      always @(posedge usr_clk) begin
+        o_phy_data_r <= tx_data;
+        o_phy_header_r <= tx_header;
+      end
+
+      genvar i;
+      for (i=0; i < 64; i=i+1) begin
+        assign o_phy_data_rev[63-i] = o_phy_data_r[i];
+      end
+      assign o_phy_header_rev = {o_phy_header_r[0], o_phy_header_r[1]};
+
+      // CDC from LR / 66 to LR / 64
+      assign wr_en = ~o_fifo_full & ~wr_rst_busy;
+      assign rd_en = i_gb_read & ~i_fifo_empty & ~rd_rst_busy;
+
+      xpm_fifo_async #(
+        .CASCADE_HEIGHT(0),
+        .CDC_SYNC_STAGES(2),
+        .DOUT_RESET_VALUE("0"),
+        .ECC_MODE("no_ecc"),
+        .EN_SIM_ASSERT_ERR("warning"),
+        .FIFO_MEMORY_TYPE("auto"),
+        .FIFO_READ_LATENCY(1),
+        .FIFO_WRITE_DEPTH(32),
+        .FULL_RESET_VALUE(0),
+        .PROG_EMPTY_THRESH(10),
+        .PROG_FULL_THRESH(10),
+        .RD_DATA_COUNT_WIDTH(1),
+        .READ_DATA_WIDTH(66),
+        .READ_MODE("std"),
+        .RELATED_CLOCKS(0),
+        .SIM_ASSERT_CHK(0),
+        .USE_ADV_FEATURES("0707"),
+        .WAKEUP_TIME(0),
+        .WRITE_DATA_WIDTH(66),
+        .WR_DATA_COUNT_WIDTH(1)
+      ) i_async_fifo (
+        .sleep (1'b0),
+        .injectdbiterr (1'b0),
+        .injectsbiterr (1'b0),
+        .rd_rst_busy (rd_rst_busy),
+        .rd_clk (phy_clk),
+        .rd_en (rd_en),
+        .dout(rd_data),
+        .empty (i_fifo_empty),
+        .wr_rst_busy (wr_rst_busy),
+        .wr_clk (usr_clk),
+        .wr_en (wr_en),
+        .din ({o_phy_data_rev, o_phy_header_rev}),
+        .full (o_fifo_full),
+        .rst (o_reset));
 
-    // Flip header bits and data
-    assign txdata   = {64'b0, tx_data_flip};
-    assign txheader = {4'b0, tx_header_flip};
+      // In LR / 64 domain
+      gearbox_66b64b i_gearbox (
+        .clk (phy_clk),
+        .reset (i_reset),
+        .i_data (rd_data),
+        .i_valid (~i_fifo_empty & i_gb_read),
+        .o_data (o_gb_data),
+        .o_rd_en (i_gb_read));
 
-    assign txctrl0  = 16'b0;
-    assign txctrl1  = 16'b0;
-    assign txctrl2  = 16'b0;
+      always @(posedge phy_clk) begin
+        txdata_d <= o_gb_data;
+      end
+
+      assign txdata   = {64'b0, txdata_d};
+      assign txheader = 'b0;
+      assign txctrl0  = 'b0;
+      assign txctrl1  = 'b0;
+      assign txctrl2  = 'b0;
+    end else begin
+      wire [39:0] tx_data_40b;
+      reg  [39:0] txdata_d;
+
+      jesd204_soft_pcs_tx #(
+        .NUM_LANES (1),
+        .DATA_PATH_WIDTH (4),
+        .INVERT_OUTPUTS (0),
+        .IFC_TYPE (0)
+      ) i_jesd204_soft_pcs_tx (
+        .clk (usr_clk),
+        .reset (o_reset),
+        .char (tx_data[31:0]),
+        .charisk (tx_charisk),
+        .data (tx_data_40b));
+
+      always @(posedge usr_clk) begin
+        txdata_d <= tx_data_40b;
+      end
+
+      assign txdata   = {88'b0, txdata_d};
+      assign txheader = 'b0;
+      assign txctrl0  = 'b0;
+      assign txctrl1  = 'b0;
+      assign txctrl2  = 'b0;
+    end
   end else begin
-    assign txdata   = {96'b0, txdata_d[31:0]};
-    assign txheader = {4'b0, txheader_d};
-    assign txctrl2  = {4'b0, txcharisk_d};
-    assign txctrl0  = 16'b0;
-    assign txctrl1  = 16'b0;
+    reg [63:0]   txdata_d;
+    reg [ 1:0]   txheader_d;
+    reg [ 3:0]   txcharisk_d;
+
+    always @(posedge usr_clk) begin
+      txdata_d <= tx_data;
+      txheader_d <= tx_header;
+      txcharisk_d <= tx_charisk;
+    end
+
+    if (LINK_MODE == 2) begin
+      wire [63:0] tx_data_flip;
+      wire [ 1:0] tx_header_flip;
+      genvar i;
+      for (i = 0; i < 64; i=i+1) begin
+        assign tx_data_flip[63-i] = txdata_d[i];
+      end
+      assign tx_header_flip = {txheader_d[0], txheader_d[1]};
+
+      // Flip header bits and data
+      assign txdata   = {64'b0, tx_data_flip};
+      assign txheader = {4'b0, tx_header_flip};
+
+      assign txctrl0  = 16'b0;
+      assign txctrl1  = 16'b0;
+      assign txctrl2  = 16'b0;
+    end else begin
+      assign txdata   = {96'b0, txdata_d[31:0]};
+      assign txheader = {4'b0, txheader_d};
+      assign txctrl2  = {4'b0, txcharisk_d};
+      assign txctrl0  = 16'b0;
+      assign txctrl1  = 16'b0;
+    end
   end
   endgenerate
 
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_constr.ttcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_constr.ttcl
new file mode 100644
index 00000000000..d0e0d87d536
--- /dev/null
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_constr.ttcl
@@ -0,0 +1,41 @@
+###############################################################################
+## Copyright (C) 2026 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName [ttcl_add $ComponentName "_constr"] :>
+<: setFileExtension ".xdc" :>
+<: setFileProcessingOrder late :>
+
+set usr_clk [get_clocks -of_objects [get_ports -quiet {usr_clk}]]
+set phy_clk [get_clocks -of_objects [get_ports -quiet {phy_clk}]]
+
+# sync bits i_reset
+set_false_path \
+  -from $phy_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_i_reset* && IS_SEQUENTIAL}]
+
+# sync bits o_reset
+set_false_path \
+  -from $usr_clk \
+  -to [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage1_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
+
+set_property ASYNC_REG TRUE \
+      [get_cells -quiet -hier *cdc_sync_stage2_reg* \
+    -filter {NAME =~ *i_sync_o_reset* && IS_SEQUENTIAL}]
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
index 91ce07e6c1d..287d8dde62b 100644
--- a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2017-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2017-2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIJESD204
 ###############################################################################
 
@@ -8,10 +8,18 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
 
 adi_ip_create jesd204_versal_gt_adapter_tx
 adi_ip_files jesd204_versal_gt_adapter_tx [list \
-  jesd204_versal_gt_adapter_tx.v
-  ]
+  jesd204_versal_gt_adapter_tx.v \
+  ../jesd204_common/gearbox_66b64b.v \
+  ../jesd204_soft_pcs_tx/jesd204_soft_pcs_tx.v \
+  ../jesd204_soft_pcs_tx/jesd204_8b10b_encoder.v \
+  $ad_hdl_dir/library/util_cdc/sync_bits.v \
+  jesd204_versal_gt_adapter_tx_constr.ttcl \
+  jesd204_versal_gt_adapter_tx_ooc.ttcl \
+]
 
 adi_ip_properties_lite jesd204_versal_gt_adapter_tx
+adi_ip_ttcl jesd204_versal_gt_adapter_tx "jesd204_versal_gt_adapter_tx_constr.ttcl"
+adi_ip_ttcl jesd204_versal_gt_adapter_tx "jesd204_versal_gt_adapter_tx_ooc.ttcl"
 
 set_property display_name "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core]
 set_property description "ADI JESD204 Versal Transceiver Tx Lane Adapter" [ipx::current_core]
@@ -36,4 +44,20 @@ adi_add_bus "TX" "slave" \
    { "tx_charisk" "txcharisk" } \
   }
 
+set_property -dict [list \
+  value_validation_type list \
+  value_validation_list {GTY GTYP GTM} \
+] [ipx::get_user_parameters TRANSCEIVER -of_objects [ipx::current_core]]
+
+set_property -dict [list \
+  value_validation_type pairs \
+  value_validation_pairs {64B66B 2 8B10B 1} \
+] [ipx::get_user_parameters LINK_MODE -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {$TRANSCEIVER == "GTM" && $LINK_MODE == 2} \
+  [ipx::get_ports phy_clk -of_objects [ipx::current_core]]
+
+set_property enablement_dependency {$TRANSCEIVER == "GTM"} \
+  [ipx::get_ports phy_rstn -of_objects [ipx::current_core]]
+
 ipx::save_core [ipx::current_core]
diff --git a/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ooc.ttcl b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ooc.ttcl
new file mode 100644
index 00000000000..48a4f94dce6
--- /dev/null
+++ b/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ooc.ttcl
@@ -0,0 +1,21 @@
+###############################################################################
+## Copyright (C) 2026 Analog Devices, Inc. All rights reserved.
+### SPDX short identifier: ADIJESD204
+###############################################################################
+
+<: setFileUsedIn { out_of_context synthesis implementation } :>
+<: ;#Component and file information :>
+<: set ComponentName [getComponentNameString] :>
+<: setOutputDirectory "./" :>
+<: setFileName $ComponentName :>
+<: setFileExtension "_ooc.xdc" :>
+
+# This XDC is used only for OOC mode of synthesis, implementation.
+# These are default values for timing driven synthesis during OOC flow.
+# These values will be overwritten during implementation with information
+# from top level.
+
+create_clock -name usr_clk -period 2.5000 [get_ports usr_clk]
+create_clock -name phy_clk -period 2.4242 [get_ports phy_clk]
+
+################################################################################
diff --git a/library/xilinx/scripts/versal_xcvr_subsystem.tcl b/library/xilinx/scripts/versal_xcvr_subsystem.tcl
index f3c17035cff..2585b5f5888 100644
--- a/library/xilinx/scripts/versal_xcvr_subsystem.tcl
+++ b/library/xilinx/scripts/versal_xcvr_subsystem.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2025-2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -19,7 +19,6 @@ set ::LANES_PER_QUAD 4
 #       RXTX : Duplex mode
 #       RX   : Rx link only
 #       TX   : Tx link only
-#
 # Returns: Nothing. Creates and configures a gtwiz_versal IP instance.
 proc create_xcvr_subsystem {
   {ip_name xcvr}
@@ -41,11 +40,12 @@ proc create_xcvr_subsystem {
   if {$direction ni {RXTX RX TX}} {
     error "Invalid direction '$direction'. Must be RXTX, RX, or TX."
   }
-  if {$transceiver ni {GTY GTYP}} {
+  if {$transceiver ni {GTY GTYP GTM}} {
     error "Invalid transceiver '$transceiver'. Must be GTY or GTYP."
   }
 
-  set is_64b66b [expr {$jesd_mode == "64B66B"}]
+  set preset                   ${transceiver}-JESD204_${jesd_mode}
+  set is_64b66b                [expr {$jesd_mode == "64B66B"}]
   set clk_divider              [expr {$is_64b66b ? 66 : 40}]
   set datapath_width           [expr {$is_64b66b ? 64 : 32}]
   set internal_datapath_width  [expr {$is_64b66b ? 64 : 40}]
@@ -53,6 +53,11 @@ proc create_xcvr_subsystem {
   set comma_mask               [expr {$is_64b66b ? "0000000000" : "1111111111"}]
   set comma_p_enable           [expr {$is_64b66b ? false : false}]
   set comma_m_enable           [expr {$is_64b66b ? false : false}]
+  if {$transceiver == "GTM"} {
+    set preset                 ${transceiver}-NRZ_JESD
+    set clk_divider            [expr {$jesd_mode == "64B66B" ? 64 : 40}]
+  }
+
   set rx_progdiv_clock         [format %.3f [expr {$rx_lane_rate * 1000.0 / $clk_divider}]]
   set tx_progdiv_clock         [format %.3f [expr {$tx_lane_rate * 1000.0 / $clk_divider}]]
 
@@ -71,10 +76,12 @@ proc create_xcvr_subsystem {
 
   # RX parameters
   dict set xcvr_param RX_LINE_RATE ${rx_lane_rate}
-  dict set xcvr_param RX_DATA_DECODING ${data_encoding}
+  dict set xcvr_param RX_DATA_DECODING [expr {$transceiver != "GTM" ? $data_encoding : "RAW"}]
+  dict set xcvr_param RX_USER_DATA_WIDTH [expr {$transceiver != "GTM" ? $datapath_width : $internal_datapath_width}]
   dict set xcvr_param RX_REFCLK_FREQUENCY ${ref_clock}
-  dict set xcvr_param RX_USER_DATA_WIDTH ${datapath_width}
-  dict set xcvr_param RX_INT_DATA_WIDTH ${internal_datapath_width}
+  if {$transceiver != "GTM"} {
+    dict set xcvr_param RX_INT_DATA_WIDTH ${internal_datapath_width}
+  }
   dict set xcvr_param RX_OUTCLK_SOURCE {RXPROGDIVCLK}
   dict set xcvr_param RXRECCLK_FREQ_VAL ${rx_progdiv_clock}
   dict set xcvr_param RXPROGDIV_FREQ_VAL ${rx_progdiv_clock}
@@ -88,21 +95,24 @@ proc create_xcvr_subsystem {
 
   # TX parameters
   dict set xcvr_param TX_LINE_RATE ${tx_lane_rate}
-  dict set xcvr_param TX_DATA_ENCODING ${data_encoding}
+  dict set xcvr_param TX_DATA_ENCODING [expr {$transceiver != "GTM" ? $data_encoding : "RAW"}]
+  dict set xcvr_param TX_USER_DATA_WIDTH [expr {$transceiver != "GTM" ? $datapath_width : $internal_datapath_width}]
   dict set xcvr_param TX_REFCLK_FREQUENCY ${ref_clock}
-  dict set xcvr_param TX_USER_DATA_WIDTH ${datapath_width}
-  dict set xcvr_param TX_INT_DATA_WIDTH ${internal_datapath_width}
-  dict set xcvr_param TXPROGDIV_FREQ_VAL ${tx_progdiv_clock}
+  if {$transceiver != "GTM"} {
+    dict set xcvr_param TX_INT_DATA_WIDTH ${internal_datapath_width}
+  }
   dict set xcvr_param TX_OUTCLK_SOURCE {TXPROGDIVCLK}
+  dict set xcvr_param TXPROGDIV_FREQ_VAL ${tx_progdiv_clock}
   dict set xcvr_param TX_PLL_TYPE {LCPLL}
 
   set phy_params [dict create]
   dict set phy_params CONFIG.ENABLE_REG_INTERFACE {true}
   dict set phy_params CONFIG.REG_CONF_INTF {AXI_LITE}
+  dict set phy_params CONFIG.GT_TYPE ${transceiver}
   dict set phy_params CONFIG.NO_OF_QUADS ${num_quads}
   dict set phy_params CONFIG.NO_OF_INTERFACE {1}
   dict set phy_params CONFIG.LOCATE_BUFG {EXAMPLE_DESIGN}
-  dict set phy_params CONFIG.INTF0_PRESET ${transceiver}-JESD204_${jesd_mode}
+  dict set phy_params CONFIG.INTF0_PRESET ${preset}
   dict set phy_params CONFIG.INTF0_GT_SETTINGS(LR0_SETTINGS) ${xcvr_param}
   if {$direction != "RXTX"} {
     dict set phy_params CONFIG.INTF0_GT_DIRECTION SIMPLEX_${direction}
@@ -117,7 +127,7 @@ proc create_xcvr_subsystem {
     dict set phy_params CONFIG.INTF1_GT_DIRECTION {SIMPLEX_TX}
     dict set phy_params CONFIG.INTF0_NO_OF_LANES $rx_no_lanes
     dict set phy_params CONFIG.INTF1_NO_OF_LANES $tx_no_lanes
-    dict set phy_params CONFIG.INTF1_PRESET ${transceiver}-JESD204_${jesd_mode}
+    dict set phy_params CONFIG.INTF1_PRESET ${preset}
     dict set phy_params CONFIG.INTF1_GT_SETTINGS(LR0_SETTINGS) ${xcvr_param}
   }
 
@@ -205,15 +215,18 @@ proc create_xcvr_subsystem {
 # Parameter description:
 #   ip_name : The name of the created ip
 #   xcvr : The name of the transceiver instance inside the ip
+#   transceiver: Transceiver type (GTY / GTYP / GTM)
 #   intf : Interface number
 #   num_lanes : Number of lanes
 #   link_mode : 1 for 8b10b, 2 for 64b66b
-#   usrclk : The usrclk signal to use as the link clock
+#   usrclk : The usrclk signal to use as the link clock (LR / 66)
 #   rx_or_tx : "RX" or "TX"
 #   lane_offset : Offset to apply to lane numbering (default 0)
+#   phy_clk: The clock signals use as the PHY clk (GTM only) (LR / 64)
+#   phy_rstn: The signal used to reset the 64b/66b gearboxes (GTM only)
 #
 # Returns: Nothing. Creates pins and connections for the datapath.
-proc xcvr_connect_datapath {ip_name xcvr intf num_lanes link_mode usrclk rx_or_tx {lane_offset 0}} {
+proc xcvr_connect_datapath {ip_name transceiver xcvr intf num_lanes link_mode usrclk rx_or_tx {lane_offset 0} {phy_clk {}} {phy_rstn {}}} {
   global LANES_PER_QUAD
 
   if {$rx_or_tx ni {RX TX}} {
@@ -222,6 +235,7 @@ proc xcvr_connect_datapath {ip_name xcvr intf num_lanes link_mode usrclk rx_or_t
 
   set is_rx [expr {$rx_or_tx == "RX"}]
   set dir_lower [string tolower $rx_or_tx]
+  set quad_usrclk [expr {($transceiver != "GTM" || $link_mode == 1)? ${usrclk} : ${phy_clk}}]
 
   # Connect differential pairs (grouped by quad)
   for {set j 0} {$j < $num_lanes} {incr j $LANES_PER_QUAD} {
@@ -248,15 +262,19 @@ proc xcvr_connect_datapath {ip_name xcvr intf num_lanes link_mode usrclk rx_or_t
     if {$is_rx} {
       ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/${dir_lower}_adapt_${idx} [list \
         LINK_MODE $link_mode \
+        TRANSCEIVER $transceiver \
       ]
       ad_connect ${ip_name}/${dir_lower}_adapt_${idx}/RX_GT_IP_Interface ${ip_name}/${xcvr}/INTF${intf}_RX${j}_GT_IP_Interface
 
       create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/${dir_lower}${idx}
       ad_connect ${ip_name}/${dir_lower}${idx} ${ip_name}/${dir_lower}_adapt_${idx}/RX
-      ad_connect ${ip_name}/${dir_lower}_adapt_${idx}/en_char_align ${ip_name}/en_char_align
+      if {$link_mode == 1} {
+        ad_connect ${ip_name}/${dir_lower}_adapt_${idx}/en_char_align ${ip_name}/en_char_align
+      }
     } else {
       ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/${dir_lower}_adapt_${idx} [list \
         LINK_MODE $link_mode \
+        TRANSCEIVER $transceiver \
       ]
       ad_connect ${ip_name}/${dir_lower}_adapt_${idx}/TX_GT_IP_Interface ${ip_name}/${xcvr}/INTF${intf}_TX${j}_GT_IP_Interface
 
@@ -264,8 +282,15 @@ proc xcvr_connect_datapath {ip_name xcvr intf num_lanes link_mode usrclk rx_or_t
       ad_connect ${ip_name}/${dir_lower}${idx} ${ip_name}/${dir_lower}_adapt_${idx}/TX
     }
 
-    ad_connect ${ip_name}/${dir_lower}_adapt_${idx}/usr_clk ${usrclk}
-    ad_connect ${ip_name}/${xcvr}/QUAD${quad_idx}_${rx_or_tx}${lane_idx}_usrclk ${usrclk}
+    ad_connect ${usrclk} ${ip_name}/${dir_lower}_adapt_${idx}/usr_clk
+    ad_connect ${quad_usrclk} ${ip_name}/${xcvr}/QUAD${quad_idx}_${rx_or_tx}${lane_idx}_usrclk
+
+    if {$phy_clk != {} && $transceiver == "GTM"} {
+      ad_connect ${phy_clk} ${ip_name}/${dir_lower}_adapt_${idx}/phy_clk
+    }
+    if {$phy_rstn != {} && $transceiver == "GTM"} {
+      ad_connect ${phy_rstn} ${ip_name}/${dir_lower}_adapt_${idx}/phy_rstn
+    }
   }
 }
 
@@ -371,6 +396,9 @@ proc xcvr_create_resetdone_logic {ip_name xcvr_list intf dir} {
 #   transceiver : Type of transceiver to use (GTY or GTYP)
 #   intf_cfg : Direction of the transceivers (RXTX, RX, or TX)
 #   consecutive_quad_mode : true to use consecutive quads for RX and TX, false to split RX and TX across different quads
+#   external_link_clk : applies to GTM and JESD204C:
+#       - when not set a clk_wizard is added to generate the LR / 66 clock for the gearbox
+#       - when set the LR / 66 clock is expected to be external to the subsystem and connected from the BD
 #
 # Returns: Nothing. Creates a hierarchical block with the complete transceiver subsystem.
 proc create_versal_jesd_xcvr_subsystem {
@@ -384,6 +412,7 @@ proc create_versal_jesd_xcvr_subsystem {
   {transceiver GTY}
   {intf_cfg RXTX}
   {consecutive_quad_mode true}
+  {external_link_clk 0}
 } {
   global LANES_PER_QUAD
 
@@ -392,14 +421,14 @@ proc create_versal_jesd_xcvr_subsystem {
     error "Invalid intf_cfg '$intf_cfg'. Must be RXTX, RX, or TX."
   }
 
-  set rx_quads     [expr {int(ceil(1.0 * $rx_no_lanes / $LANES_PER_QUAD))}]
-  set tx_quads     [expr {int(ceil(1.0 * $tx_no_lanes / $LANES_PER_QUAD))}]
-  set num_quads    [expr {max($rx_quads, $tx_quads)}]
-  set link_mode    [expr {$jesd_mode == "64B66B" ? 2 : 1}]
-  set max_no_lanes [expr {max($rx_no_lanes, $tx_no_lanes)}]
-
-  set has_rx [expr {$intf_cfg != "TX"}]
-  set has_tx [expr {$intf_cfg != "RX"}]
+  set rx_quads          [expr {int(ceil(1.0 * $rx_no_lanes / $LANES_PER_QUAD))}]
+  set tx_quads          [expr {int(ceil(1.0 * $tx_no_lanes / $LANES_PER_QUAD))}]
+  set num_quads         [expr {max($rx_quads, $tx_quads)}]
+  set link_mode         [expr {$jesd_mode == "64B66B" ? 2 : 1}]
+  set max_no_lanes      [expr {max($rx_no_lanes, $tx_no_lanes)}]
+  set has_rx            [expr {$intf_cfg != "TX"}]
+  set has_tx            [expr {$intf_cfg != "RX"}]
+  set has_single_clock  [expr {$transceiver != "GTM" || $link_mode == 1}]
 
   if {$intf_cfg == "RXTX"} {
     set rx_intf 0
@@ -423,11 +452,13 @@ proc create_versal_jesd_xcvr_subsystem {
   create_bd_pin -dir I ${ip_name}/s_axi_clk
   create_bd_pin -dir I ${ip_name}/s_axi_resetn
   if {$has_rx} {
-    create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
-    create_bd_pin -dir I ${ip_name}/en_char_align
+    create_bd_pin -dir O ${ip_name}/rxusrclk_out
+    if {$link_mode == 1} {
+      create_bd_pin -dir I ${ip_name}/en_char_align
+    }
   }
   if {$has_tx} {
-    create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk
+    create_bd_pin -dir O ${ip_name}/txusrclk_out
   }
 
   # Create transceiver subsystem(s)
@@ -456,33 +487,99 @@ proc create_versal_jesd_xcvr_subsystem {
 
   # RX datapath
   if {$has_rx} {
+    # This shouldn't be necessary, we could use the INTF_out_clk but there is a bug
+    # where the divider is not properly set in the generated code.
     ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx
     ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rx_clr_out ${ip_name}/bufg_gt_rx/gt_bufgtclr
     ad_connect ${ip_name}/xcvr/QUAD0_RX0_outclk          ${ip_name}/bufg_gt_rx/outclk
-    ad_connect ${ip_name}/bufg_gt_rx/usrclk              ${ip_name}/rxusrclk_out
+    if {$has_single_clock} {
+      ad_connect ${ip_name}/bufg_gt_rx/usrclk            ${ip_name}/rxusrclk_out
+    } elseif {$external_link_clk} {
+        create_bd_pin -dir I ${ip_name}/rx_usrclk_in
+        ad_connect ${ip_name}/rx_usrclk_in ${ip_name}/rxusrclk_out
+    } else {
+      ad_ip_instance clk_wizard ${ip_name}/rx_clkwiz
+      ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY [format %.5f [expr $rx_lane_rate * 1000.0 / 66]]
+      ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.USE_PHASE_ALIGNMENT {true}
+      ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.USE_LOCKED {true}
+      ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.JITTER_SEL {Min_O_Jitter}
+      ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.PRIMITIVE_TYPE {Auto}
+      ad_ip_parameter ${ip_name}/rx_clkwiz CONFIG.PRIM_SOURCE {Global_buffer}
+
+      ad_connect ${ip_name}/bufg_gt_rx/usrclk   ${ip_name}/rx_clkwiz/clk_in1
+      ad_connect ${ip_name}/rx_clkwiz/clk_out1  ${ip_name}/rxusrclk_out
+    }
+
+    set rx_usrclk   ${ip_name}/bufg_gt_rx/usrclk
+    set rx_phy_clk  {}
+    set rx_phy_rstn ${ip_name}/xcvr/INTF${rx_intf}_rst_rx_done_out
+
+    if {!$has_single_clock} {
+      if {$external_link_clk} {
+        set rx_phy_clk  ${ip_name}/bufg_gt_rx/usrclk
+        set rx_usrclk   ${ip_name}/rx_usrclk_in
+      } else {
+        set rx_phy_clk  ${ip_name}/bufg_gt_rx/usrclk
+        set rx_usrclk   ${ip_name}/rx_clkwiz/clk_out1
+        set rx_phy_rstn ${ip_name}/rx_clkwiz/locked
+      }
+    }
 
     if {$consecutive_quad_mode} {
-      xcvr_connect_datapath ${ip_name} xcvr $rx_intf $rx_no_lanes $link_mode ${ip_name}/bufg_gt_rx/usrclk RX
+      xcvr_connect_datapath ${ip_name} $transceiver xcvr $rx_intf $rx_no_lanes $link_mode $rx_usrclk RX 0 $rx_phy_clk $rx_phy_rstn
     } else {
       set half_lanes [expr {int(ceil($rx_no_lanes / 2.0))}]
-      xcvr_connect_datapath ${ip_name} xcvr   $rx_intf $half_lanes $link_mode ${ip_name}/bufg_gt_rx/usrclk RX 0
-      xcvr_connect_datapath ${ip_name} xcvr_b $rx_intf $half_lanes $link_mode ${ip_name}/bufg_gt_rx/usrclk RX $half_lanes
+      xcvr_connect_datapath ${ip_name} $transceiver xcvr   $rx_intf $half_lanes $link_mode $rx_usrclk RX 0           $rx_phy_clk $rx_phy_rstn
+      xcvr_connect_datapath ${ip_name} $transceiver xcvr_b $rx_intf $half_lanes $link_mode $rx_usrclk RX $half_lanes $rx_phy_clk $rx_phy_rstn
     }
   }
 
   # TX datapath
   if {$has_tx} {
+    # This shouldn't be necessary, we could use the INTF_out_clk but there is a bug
+    # where the divider is not properly set in the generated code.
     ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx
     ad_connect ${ip_name}/xcvr/INTF${tx_intf}_tx_clr_out ${ip_name}/bufg_gt_tx/gt_bufgtclr
     ad_connect ${ip_name}/xcvr/QUAD0_TX0_outclk          ${ip_name}/bufg_gt_tx/outclk
-    ad_connect ${ip_name}/bufg_gt_tx/usrclk              ${ip_name}/txusrclk_out
+    if {$has_single_clock} {
+      ad_connect ${ip_name}/bufg_gt_tx/usrclk            ${ip_name}/txusrclk_out
+    } elseif {$external_link_clk} {
+      create_bd_pin -dir I ${ip_name}/tx_usrclk_in
+      ad_connect ${ip_name}/tx_usrclk_in ${ip_name}/txusrclk_out
+    } else {
+      ad_ip_instance clk_wizard ${ip_name}/tx_clkwiz
+      ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.CLKOUT_REQUESTED_OUT_FREQUENCY [format %.5f [expr $tx_lane_rate * 1000.0 / 66]]
+      ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.USE_PHASE_ALIGNMENT {true}
+      ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.USE_LOCKED {true}
+      ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.JITTER_SEL {Min_O_Jitter}
+      ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.PRIMITIVE_TYPE {Auto}
+      ad_ip_parameter ${ip_name}/tx_clkwiz CONFIG.PRIM_SOURCE {Global_buffer}
+
+      ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/tx_clkwiz/clk_in1
+      ad_connect ${ip_name}/tx_clkwiz/clk_out1 ${ip_name}/txusrclk_out
+    }
+
+    set tx_usrclk   ${ip_name}/bufg_gt_tx/usrclk
+    set tx_phy_clk  {}
+    set tx_phy_rstn ${ip_name}/xcvr/INTF${tx_intf}_rst_tx_done_out
+
+    if {!$has_single_clock} {
+      if {$external_link_clk} {
+        set tx_phy_clk  ${ip_name}/bufg_gt_tx/usrclk
+        set rx_usrclk   ${ip_name}/tx_usrclk_in
+      } else {
+        set tx_phy_clk  ${ip_name}/bufg_gt_tx/usrclk
+        set tx_usrclk   ${ip_name}/tx_clkwiz/clk_out1
+        set tx_phy_rstn ${ip_name}/tx_clkwiz/locked
+      }
+    }
 
     if {$consecutive_quad_mode} {
-      xcvr_connect_datapath ${ip_name} xcvr $tx_intf $tx_no_lanes $link_mode ${ip_name}/bufg_gt_tx/usrclk TX
+      xcvr_connect_datapath ${ip_name} $transceiver xcvr $tx_intf $tx_no_lanes $link_mode $tx_usrclk TX 0 $tx_phy_clk $tx_phy_rstn
     } else {
       set half_lanes [expr {int(ceil($tx_no_lanes / 2.0))}]
-      xcvr_connect_datapath ${ip_name} xcvr   $tx_intf $half_lanes $link_mode ${ip_name}/bufg_gt_tx/usrclk TX 0
-      xcvr_connect_datapath ${ip_name} xcvr_b $tx_intf $half_lanes $link_mode ${ip_name}/bufg_gt_tx/usrclk TX $half_lanes
+      xcvr_connect_datapath ${ip_name} $transceiver xcvr   $tx_intf $half_lanes $link_mode $tx_usrclk TX 0           $tx_phy_clk $tx_phy_rstn
+      xcvr_connect_datapath ${ip_name} $transceiver xcvr_b $tx_intf $half_lanes $link_mode $tx_usrclk TX $half_lanes $tx_phy_clk $tx_phy_rstn
     }
   }
 
diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
index 24c57910a8b..144375470cc 100644
--- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
+++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2019-2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -36,6 +36,10 @@ if {![info exists TRANSCEIVER_TYPE]} {
   set TRANSCEIVER_TYPE GTY
 }
 
+if {![info exists EXTERNAL_LINK_CLK]} {
+  set EXTERNAL_LINK_CLK 0
+}
+
 # Common parameter for TX and RX
 set JESD_MODE  $ad_project_params(JESD_MODE)
 set RX_LANE_RATE $ad_project_params(RX_LANE_RATE)
@@ -157,6 +161,8 @@ if {!$ADI_PHY_SEL} {
   create_bd_port -dir I tx_sysref_0
   create_bd_port -dir O rx_sync_0
   create_bd_port -dir I tx_sync_0
+  create_bd_port -dir I rx_usrclk_in
+  create_bd_port -dir I tx_usrclk_in
 }
 
 # common xcvr
@@ -209,7 +215,7 @@ if {$ADI_PHY_SEL == 1} {
 
   switch $INTF_CFG {
     "RXTX" {
-      create_versal_jesd_xcvr_subsystem jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
+      create_versal_jesd_xcvr_subsystem jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG true $EXTERNAL_LINK_CLK
       set rx_phy jesd204_phy_rxtx
       set tx_phy jesd204_phy_rxtx
       ad_connect ref_clk_q0      ${rx_phy}/GT_REFCLK
@@ -223,9 +229,13 @@ if {$ADI_PHY_SEL == 1} {
       ad_connect ${rx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
       ad_connect ${rx_phy}/rx_resetdone rx_resetdone
       ad_connect ${rx_phy}/tx_resetdone tx_resetdone
+      if {$EXTERNAL_LINK_CLK && $JESD_MODE == "64B66B"} {
+        ad_connect rx_usrclk_in     ${rx_phy}/rx_usrclk_in
+        ad_connect tx_usrclk_in     ${tx_phy}/tx_usrclk_in
+      }
     }
     "RX" {
-      create_versal_jesd_xcvr_subsystem jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES 0 $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
+      create_versal_jesd_xcvr_subsystem jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES 0 $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG true $EXTERNAL_LINK_CLK
       set rx_phy jesd204_phy_rx
       ad_connect ref_clk_q0      ${rx_phy}/GT_REFCLK
       ad_connect gt_reset        ${rx_phy}/gtreset_in
@@ -235,9 +245,12 @@ if {$ADI_PHY_SEL == 1} {
       ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath
       ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath
       ad_connect ${rx_phy}/rx_resetdone rx_resetdone
+      if {$EXTERNAL_LINK_CLK && $JESD_MODE == "64B66B"} {
+        ad_connect rx_usrclk_in     ${rx_phy}/rx_usrclk_in
+      }
     }
     "TX" {
-      create_versal_jesd_xcvr_subsystem jesd204_phy_tx $JESD_MODE 0 $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
+      create_versal_jesd_xcvr_subsystem jesd204_phy_tx $JESD_MODE 0 $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG true $EXTERNAL_LINK_CLK
       set tx_phy jesd204_phy_tx
       ad_connect ref_clk_q0      ${tx_phy}/GT_REFCLK
       ad_connect gt_reset        ${tx_phy}/gtreset_in
@@ -247,6 +260,9 @@ if {$ADI_PHY_SEL == 1} {
       ad_connect ${tx_phy}/gtreset_tx_datapath gt_reset_tx_datapath
       ad_connect ${tx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
       ad_connect ${tx_phy}/tx_resetdone tx_resetdone
+      if {$EXTERNAL_LINK_CLK && $JESD_MODE == "64B66B"} {
+        ad_connect tx_usrclk_in     ${tx_phy}/tx_usrclk_in
+      }
     }
   }
 }
@@ -422,8 +438,6 @@ if {$ADI_PHY_SEL == 1} {
     if {$JESD_MODE == "8B10B"} {
       ad_connect axi_mxfe_rx_jesd/phy_en_char_align ${rx_phy}/en_char_align
       ad_connect axi_mxfe_rx_jesd/sync rx_sync_0
-    } else {
-      ad_connect GND ${rx_phy}/en_char_align
     }
   }
   if {$INTF_CFG != "RX"} {
diff --git a/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl b/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
deleted file mode 100644
index 93cb17029b7..00000000000
--- a/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
+++ /dev/null
@@ -1,896 +0,0 @@
-###############################################################################
-## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
-### SPDX short identifier: ADIBSD
-###############################################################################
-
-# Parameter description:
-#   ip_name : The name of the versal phy ip
-#   rx_num_lanes : The number of used RX lanes for the JESD mode
-#   tx_num_lanes : The number of used TX lanes for the JESD mode
-proc create_reset_logic {
-  {ip_name versal_phy}
-  {rx_num_lanes 4}
-  {tx_num_lanes 4}
-  {intf_cfg RXTX}
-} {
-  set rx_bridge gt_bridge_ip_0
-  set asymmetric_mode [expr {$intf_cfg == "RXTX" && $rx_num_lanes != $tx_num_lanes}]
-  set tx_bridge [expr {$asymmetric_mode == 0 ? "gt_bridge_ip_0" : "gt_bridge_ip_1"}]
-
-  create_bd_pin -dir I ${ip_name}/gtreset_in
-  create_bd_pin -dir O ${ip_name}/gtpowergood
-  if {$intf_cfg != "TX"} {
-    create_bd_pin -dir I ${ip_name}/gtreset_rx_pll_and_datapath
-    create_bd_pin -dir I ${ip_name}/gtreset_rx_datapath
-    create_bd_pin -dir O ${ip_name}/rx_resetdone
-  }
-  if {$intf_cfg != "RX"} {
-    create_bd_pin -dir I ${ip_name}/gtreset_tx_pll_and_datapath
-    create_bd_pin -dir I ${ip_name}/gtreset_tx_datapath
-    create_bd_pin -dir O ${ip_name}/tx_resetdone
-  }
-  # Sync resets to apb3clk
-
-  create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_sync
-  ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_sync/out_clk
-  ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_sync/out_resetn
-  ad_connect ${ip_name}/gtreset_in ${ip_name}/gtreset_sync/in_bits
-  ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${rx_bridge}/gtreset_in
-  if {$asymmetric_mode} {
-    ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/${tx_bridge}/gtreset_in
-  }
-
-  foreach port {pll_and_datapath datapath} {
-    foreach rx_tx {rx tx} {
-      if {($rx_tx == "rx" && $intf_cfg == "TX") || ($rx_tx == "tx" && $intf_cfg == "RX")} {
-        continue
-      }
-      set bridge [expr {$rx_tx == "rx" ? $rx_bridge : $tx_bridge}]
-      create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_${rx_tx}_${port}_sync
-      ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_clk
-      ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_resetn
-      ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/gtreset_${rx_tx}_${port}_sync/in_bits
-      ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/${bridge}/reset_${rx_tx}_${port}_in
-    }
-  }
-
-  set max_lanes [expr max($rx_num_lanes, $tx_num_lanes)]
-  set num_quads [expr int(ceil(1.0 * $max_lanes / 4))]
-
-  ad_ip_instance ilconcat ${ip_name}/concat_powergood [list \
-   NUM_PORTS $num_quads \
- ]
-
-  ad_ip_instance ilreduced_logic ${ip_name}/and_powergood [list \
-    C_SIZE $num_quads \
-  ]
-
-  for {set j 0} {$j < $num_quads} {incr j} {
-    ad_connect ${ip_name}/concat_powergood/In${j} ${ip_name}/gt_quad_base_${j}/gtpowergood
-  }
-
-  ad_connect ${ip_name}/concat_powergood/dout ${ip_name}/and_powergood/Op1
-  ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${rx_bridge}/gtpowergood
-  if {$asymmetric_mode} {
-    ad_connect ${ip_name}/and_powergood/Res ${ip_name}/${tx_bridge}/gtpowergood
-  }
-
-  for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
-    set quad_index [expr int($j / 4)]
-    set ch_index [expr $j % 4]
-    ad_connect ${ip_name}/${rx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset
-  }
-  if {$asymmetric_mode} {
-    for {set j ${rx_num_lanes}} {$j < ${tx_num_lanes}} {incr j} {
-      set quad_index [expr int($j / 4)]
-      set ch_index [expr $j % 4]
-      ad_connect ${ip_name}/${tx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset
-    }
-  }
-  ad_ip_instance ilconcat ${ip_name}/xlconcat_iloresetdone [list \
-      NUM_PORTS ${rx_num_lanes} \
-  ]
-  ad_ip_instance ilreduced_logic ${ip_name}/and_iloresetdone [list \
-      C_SIZE ${rx_num_lanes} \
-  ]
-  for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
-    set quad_index [expr int($j / 4)]
-    set ch_index [expr $j % 4]
-    ad_connect ${ip_name}/xlconcat_iloresetdone/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone
-  }
-  ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/and_iloresetdone/Op1
-  ad_connect ${ip_name}/and_iloresetdone/Res ${ip_name}/${rx_bridge}/ilo_resetdone
-  if {$asymmetric_mode} {
-    ad_ip_instance ilconcat ${ip_name}/xlconcat_iloresetdone_tx [list \
-      NUM_PORTS ${tx_num_lanes} \
-    ]
-    ad_ip_instance ilreduced_logic ${ip_name}/and_iloresetdone_tx [list \
-        C_SIZE ${tx_num_lanes} \
-    ]
-    for {set j 0} {$j < ${tx_num_lanes}} {incr j} {
-      set quad_index [expr int($j / 4)]
-      set ch_index [expr $j % 4]
-      ad_connect ${ip_name}/xlconcat_iloresetdone_tx/In${j} ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloresetdone
-    }
-    ad_connect ${ip_name}/xlconcat_iloresetdone_tx/dout ${ip_name}/and_iloresetdone_tx/Op1
-    ad_connect ${ip_name}/and_iloresetdone_tx/Res ${ip_name}/${tx_bridge}/ilo_resetdone
-  }
-
-  for {set j 0} {$j < ${num_quads}} {incr j} {
-    ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk0_lcpllreset
-    ad_connect ${ip_name}/${rx_bridge}/gt_pll_reset ${ip_name}/gt_quad_base_${j}/hsclk1_lcpllreset
-  }
-
-  set num_cplllocks [expr 2 * ${num_quads}]
-  ad_ip_instance ilconcat ${ip_name}/concat_cplllock [list \
-      NUM_PORTS ${num_cplllocks} \
-  ]
-  ad_ip_instance ilreduced_logic ${ip_name}/and_cplllock [list \
-      C_SIZE ${num_cplllocks} \
-  ]
-
-  for {set j 0} {$j < ${num_quads}} {incr j} {
-    set in_index_0 [expr $j * 2 + 0]
-    set in_index_1 [expr $j * 2 + 1]
-    ad_connect ${ip_name}/concat_cplllock/In${in_index_0} ${ip_name}/gt_quad_base_${j}/hsclk0_lcplllock
-    ad_connect ${ip_name}/concat_cplllock/In${in_index_1} ${ip_name}/gt_quad_base_${j}/hsclk1_lcplllock
-  }
-
-  ad_connect ${ip_name}/concat_cplllock/dout ${ip_name}/and_cplllock/Op1
-  ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${rx_bridge}/gt_lcpll_lock
-  if {$asymmetric_mode} {
-    ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${tx_bridge}/gt_lcpll_lock
-  }
-
-  ad_ip_instance ilconcat ${ip_name}/concat_phystatus [list \
-    NUM_PORTS ${rx_num_lanes} \
-  ]
-  for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
-    set quad_index [expr int($j / 4)]
-    set ch_index [expr $j % 4]
-
-    ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus/In${j}
-  }
-  ad_connect ${ip_name}/concat_phystatus/dout ${ip_name}/${rx_bridge}/ch_phystatus_in
-  if {$asymmetric_mode} {
-    ad_ip_instance ilconcat ${ip_name}/concat_phystatus_tx [list \
-      NUM_PORTS ${rx_num_lanes} \
-    ]
-    for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
-      set quad_index [expr int($j / 4)]
-      set ch_index [expr $j % 4]
-
-      ad_connect ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_phystatus ${ip_name}/concat_phystatus_tx/In${j}
-    }
-    ad_connect ${ip_name}/concat_phystatus_tx/dout ${ip_name}/${tx_bridge}/ch_phystatus_in
-  }
-
-  # Outputs
-  ad_connect ${ip_name}/and_powergood/Res ${ip_name}/gtpowergood
-  if {$intf_cfg != "TX"} {
-    ad_connect ${ip_name}/${rx_bridge}/rx_resetdone_out ${ip_name}/rx_resetdone
-  }
-  if {$intf_cfg != "RX"} {
-    ad_connect ${ip_name}/${tx_bridge}/tx_resetdone_out ${ip_name}/tx_resetdone
-  }
-}
-
-# Parameter description:
-#   ip_name : The name of the created ip
-#   jesd_mode : Used physical layer encoder mode
-#   rx_num_lanes :  Number of RX lanes
-#   tx_num_lanes :  Number of TX lanes
-#   ref_clock : Frequency of reference clock in MHz used in 64B66B mode (LANE_RATE/66) or 8B10B mode (LANE_RATE/40)
-#   rx_lane_rate : Line rate of the Rx link ( e.g. MxFE to FPGA ) in GHz
-#   tx_lane_rate : Line rate of the Tx link ( e.g. FPGA to MxFE ) in GHz
-#   intf_cfg : Direction of the transceivers
-#       RXTX : Duplex mode
-#       RX   : Rx link only
-#       TX   : Tx link only
-proc create_versal_phy {
-  {ip_name versal_phy}
-  {jesd_mode 64B66B}
-  {rx_num_lanes 4}
-  {tx_num_lanes 4}
-  {rx_lane_rate 24.75}
-  {tx_lane_rate 24.75}
-  {ref_clock 375}
-  {transceiver GTY}
-  {intf_cfg RXTX}
-} {
-
-  set clk_divider              [expr { $jesd_mode == "64B66B" ? 66 : 40} ]
-  set datapath_width           [expr { $jesd_mode == "64B66B" ? 64 : 32} ]
-  set internal_datapath_width  [expr { $jesd_mode == "64B66B" ? 64 : 40} ]
-  set data_encoding            [expr { $jesd_mode == "64B66B" ? "64B66B_ASYNC" : "8B10B"} ]
-  set link_mode                [expr { $jesd_mode == "64B66B" ? 2 : 1} ]
-  set comma_mask               [expr { $jesd_mode == "64B66B" ? "0000000000" : "1111111111"} ]
-  set comma_p_enable           [expr { $jesd_mode == "64B66B" ? false : false} ]
-  set comma_m_enable           [expr { $jesd_mode == "64B66B" ? false : false} ]
-  set num_quads                [expr int(ceil(1.0 * max($rx_num_lanes, $tx_num_lanes) / 4))]
-  set asymmetric_mode          [expr { $intf_cfg == "RXTX" && $rx_num_lanes != $tx_num_lanes ? true : false } ]
-  # When asymmetric_mode is true it means that the number of lanes on the Rx side is different from the number of lanes on the Tx side
-  # The 'gt_bridge_ip' can only be configured with the same number of lanes so we need to instantiate two ips, one for the Rx and one for the Tx
-  # Both 'gt_bridge_ip' will still share the same quad
-  puts "intf_cfg: ${intf_cfg}"
-  puts "assymmetric_mode: ${asymmetric_mode}"
-
-  set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000.0 / ${clk_divider}]]
-  set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000.0 / ${clk_divider}]]
-  set preset ${transceiver}-JESD204_64B66B
-
-  if {$intf_cfg == "RX"} {
-    set gt_direction "SIMPLEX_RX"
-    set no_lanes_property "CONFIG.IP_NO_OF_RX_LANES"
-  } elseif {$intf_cfg == "TX"} {
-    set gt_direction "SIMPLEX_TX"
-    set no_lanes_property "CONFIG.IP_NO_OF_TX_LANES"
-  } else {
-    set gt_direction "DUPLEX"
-    set no_lanes_property "CONFIG.IP_NO_OF_LANES"
-  }
-
-  create_bd_cell -type hier ${ip_name}
-
-  # Common interface
-  create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk
-  create_bd_pin -dir I ${ip_name}/s_axi_clk
-  create_bd_pin -dir I ${ip_name}/s_axi_resetn
-  if {$intf_cfg != "TX"} {
-    create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
-    create_bd_pin -dir I ${ip_name}/en_char_align
-  }
-  if {$intf_cfg != "RX"} {
-    create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk
-  }
-
-  ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_0
-  set rx_bridge gt_bridge_ip_0
-  set tx_bridge gt_bridge_ip_0
-  if {$asymmetric_mode} {
-    ad_ip_instance gt_bridge_ip ${ip_name}/gt_bridge_ip_1
-    set tx_bridge gt_bridge_ip_1
-  }
-  if {!$asymmetric_mode} {
-    set num_lanes [expr max($rx_num_lanes, $tx_num_lanes)]
-    set_property -dict [list \
-      CONFIG.BYPASS_MODE {true} \
-      CONFIG.REG_CONF_INTF {AXI_LITE} \
-      CONFIG.IP_PRESET ${preset} \
-      CONFIG.IP_GT_DIRECTION ${gt_direction} \
-      ${no_lanes_property} ${num_lanes} \
-      CONFIG.IP_LR0_SETTINGS [list \
-        PRESET $preset \
-        INTERNAL_PRESET JESD204_${jesd_mode} \
-        GT_TYPE $transceiver \
-        GT_DIRECTION $gt_direction \
-        TX_LINE_RATE $tx_lane_rate \
-        TX_PLL_TYPE LCPLL \
-        TX_REFCLK_FREQUENCY $ref_clock \
-        TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
-        TX_FRACN_ENABLED true \
-        TX_FRACN_NUMERATOR 0 \
-        TX_REFCLK_SOURCE R0 \
-        TX_DATA_ENCODING $data_encoding \
-        TX_USER_DATA_WIDTH $datapath_width \
-        TX_INT_DATA_WIDTH $internal_datapath_width \
-        TX_BUFFER_MODE 1 \
-        TX_BUFFER_BYPASS_MODE Fast_Sync \
-        TX_PIPM_ENABLE false \
-        TX_OUTCLK_SOURCE TXPROGDIVCLK \
-        TXPROGDIV_FREQ_ENABLE true \
-        TXPROGDIV_FREQ_SOURCE LCPLL \
-        TXPROGDIV_FREQ_VAL $tx_progdiv_clock \
-        TX_DIFF_SWING_EMPH_MODE CUSTOM \
-        TX_64B66B_SCRAMBLER false \
-        TX_64B66B_ENCODER false \
-        TX_64B66B_CRC false \
-        TX_RATE_GROUP A \
-        RX_LINE_RATE $rx_lane_rate \
-        RX_PLL_TYPE LCPLL \
-        RX_REFCLK_FREQUENCY $ref_clock \
-        RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
-        RX_FRACN_ENABLED true \
-        RX_FRACN_NUMERATOR 0 \
-        RX_REFCLK_SOURCE R0 \
-        RX_DATA_DECODING $data_encoding \
-        RX_USER_DATA_WIDTH $datapath_width \
-        RX_INT_DATA_WIDTH $internal_datapath_width \
-        RX_BUFFER_MODE 1 \
-        RX_OUTCLK_SOURCE RXPROGDIVCLK \
-        RXPROGDIV_FREQ_ENABLE true \
-        RXPROGDIV_FREQ_SOURCE LCPLL \
-        RXPROGDIV_FREQ_VAL $rx_progdiv_clock \
-        INS_LOSS_NYQ 12 \
-        RX_EQ_MODE LPM \
-        RX_COUPLING AC \
-        RX_TERMINATION PROGRAMMABLE \
-        RX_RATE_GROUP A \
-        RX_TERMINATION_PROG_VALUE 800 \
-        RX_PPM_OFFSET 0 \
-        RX_64B66B_DESCRAMBLER false \
-        RX_64B66B_DECODER false \
-        RX_64B66B_CRC false \
-        OOB_ENABLE false \
-        RX_COMMA_ALIGN_WORD 1 \
-        RX_COMMA_SHOW_REALIGN_ENABLE false \
-        PCIE_ENABLE false \
-        RX_COMMA_P_ENABLE $comma_p_enable \
-        RX_COMMA_M_ENABLE $comma_m_enable \
-        RX_COMMA_DOUBLE_ENABLE false \
-        RX_COMMA_P_VAL 0101111100 \
-        RX_COMMA_M_VAL 1010000011 \
-        RX_COMMA_MASK $comma_mask \
-        RX_SLIDE_MODE PCS \
-        RX_SSC_PPM 0 \
-        RX_CB_NUM_SEQ 0 \
-        RX_CB_LEN_SEQ 1 \
-        RX_CB_MAX_SKEW 1 \
-        RX_CB_MAX_LEVEL 1 \
-        RX_CB_MASK_0_0 false \
-        RX_CB_VAL_0_0 00000000 \
-        RX_CB_K_0_0 false \
-        RX_CB_DISP_0_0 false \
-        RX_CB_MASK_0_1 false \
-        RX_CB_VAL_0_1 00000000 \
-        RX_CB_K_0_1 false \
-        RX_CB_DISP_0_1 false \
-        RX_CB_MASK_0_2 false \
-        RX_CB_VAL_0_2 00000000 \
-        RX_CB_K_0_2 false \
-        RX_CB_DISP_0_2 false \
-        RX_CB_MASK_0_3 false \
-        RX_CB_VAL_0_3 00000000 \
-        RX_CB_K_0_3 false \
-        RX_CB_DISP_0_3 false \
-        RX_CB_MASK_1_0 false \
-        RX_CB_VAL_1_0 00000000 \
-        RX_CB_K_1_0 false \
-        RX_CB_DISP_1_0 false \
-        RX_CB_MASK_1_1 false \
-        RX_CB_VAL_1_1 00000000 \
-        RX_CB_K_1_1 false \
-        RX_CB_DISP_1_1 false \
-        RX_CB_MASK_1_2 false \
-        RX_CB_VAL_1_2 00000000 \
-        RX_CB_K_1_2 false \
-        RX_CB_DISP_1_2 false \
-        RX_CB_MASK_1_3 false \
-        RX_CB_VAL_1_3 00000000 \
-        RX_CB_K_1_3 false \
-        RX_CB_DISP_1_3 false \
-        RX_CC_NUM_SEQ 0 \
-        RX_CC_LEN_SEQ 1 \
-        RX_CC_PERIODICITY 5000 \
-        RX_CC_KEEP_IDLE DISABLE \
-        RX_CC_PRECEDENCE ENABLE \
-        RX_CC_REPEAT_WAIT 0 \
-        RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \
-        RX_CC_MASK_0_0 false \
-        RX_CC_VAL_0_0 00000000 \
-        RX_CC_K_0_0 false \
-        RX_CC_DISP_0_0 false \
-        RX_CC_MASK_0_1 false \
-        RX_CC_VAL_0_1 00000000 \
-        RX_CC_K_0_1 false \
-        RX_CC_DISP_0_1 false \
-        RX_CC_MASK_0_2 false \
-        RX_CC_VAL_0_2 00000000 \
-        RX_CC_K_0_2 false \
-        RX_CC_DISP_0_2 false \
-        RX_CC_MASK_0_3 false \
-        RX_CC_VAL_0_3 00000000 \
-        RX_CC_K_0_3 false \
-        RX_CC_DISP_0_3 false \
-        RX_CC_MASK_1_0 false \
-        RX_CC_VAL_1_0 00000000 \
-        RX_CC_K_1_0 false \
-        RX_CC_DISP_1_0 false \
-        RX_CC_MASK_1_1 false \
-        RX_CC_VAL_1_1 00000000 \
-        RX_CC_K_1_1 false \
-        RX_CC_DISP_1_1 false \
-        RX_CC_MASK_1_2 false \
-        RX_CC_VAL_1_2 00000000 \
-        RX_CC_K_1_2 false \
-        RX_CC_DISP_1_2 false \
-        RX_CC_MASK_1_3 false \
-        RX_CC_VAL_1_3 00000000 \
-        RX_CC_K_1_3 false \
-        RX_CC_DISP_1_3 false \
-        PCIE_USERCLK2_FREQ 250 \
-        PCIE_USERCLK_FREQ 250 \
-        RX_JTOL_FC 10 \
-        RX_JTOL_LF_SLOPE -20 \
-        RX_BUFFER_BYPASS_MODE Fast_Sync \
-        RX_BUFFER_BYPASS_MODE_LANE MULTI \
-        RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \
-        RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \
-        RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
-        TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
-        RESET_SEQUENCE_INTERVAL 0 \
-        RX_COMMA_PRESET NONE \
-        RX_COMMA_VALID_ONLY 0 \
-        ] \
-    ] [get_bd_cells ${ip_name}/${rx_bridge}]
-  } else {
-    set_property -dict [list \
-        CONFIG.BYPASS_MODE {true} \
-        CONFIG.REG_CONF_INTF {AXI_LITE} \
-        CONFIG.IP_PRESET ${preset} \
-        CONFIG.IP_GT_DIRECTION {SIMPLEX_RX} \
-        CONFIG.IP_NO_OF_RX_LANES ${rx_num_lanes} \
-        CONFIG.IP_LR0_SETTINGS [list \
-          PRESET $preset \
-          INTERNAL_PRESET JESD204_${jesd_mode} \
-          GT_TYPE $transceiver \
-          GT_DIRECTION SIMPLEX_RX \
-          TX_LINE_RATE $tx_lane_rate \
-          TX_PLL_TYPE LCPLL \
-          TX_REFCLK_FREQUENCY $ref_clock \
-          TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
-          TX_FRACN_ENABLED true \
-          TX_FRACN_NUMERATOR 0 \
-          TX_REFCLK_SOURCE R0 \
-          TX_DATA_ENCODING $data_encoding \
-          TX_USER_DATA_WIDTH $datapath_width \
-          TX_INT_DATA_WIDTH $internal_datapath_width \
-          TX_BUFFER_MODE 1 \
-          TX_BUFFER_BYPASS_MODE Fast_Sync \
-          TX_PIPM_ENABLE false \
-          TX_OUTCLK_SOURCE TXPROGDIVCLK \
-          TXPROGDIV_FREQ_ENABLE true \
-          TXPROGDIV_FREQ_SOURCE LCPLL \
-          TXPROGDIV_FREQ_VAL $tx_progdiv_clock \
-          TX_DIFF_SWING_EMPH_MODE CUSTOM \
-          TX_64B66B_SCRAMBLER false \
-          TX_64B66B_ENCODER false \
-          TX_64B66B_CRC false \
-          TX_RATE_GROUP A \
-          RX_LINE_RATE $rx_lane_rate \
-          RX_PLL_TYPE LCPLL \
-          RX_REFCLK_FREQUENCY $ref_clock \
-          RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
-          RX_FRACN_ENABLED true \
-          RX_FRACN_NUMERATOR 0 \
-          RX_REFCLK_SOURCE R0 \
-          RX_DATA_DECODING $data_encoding \
-          RX_USER_DATA_WIDTH $datapath_width \
-          RX_INT_DATA_WIDTH $internal_datapath_width \
-          RX_BUFFER_MODE 1 \
-          RX_OUTCLK_SOURCE RXPROGDIVCLK \
-          RXPROGDIV_FREQ_ENABLE true \
-          RXPROGDIV_FREQ_SOURCE LCPLL \
-          RXPROGDIV_FREQ_VAL $rx_progdiv_clock \
-          INS_LOSS_NYQ 12 \
-          RX_EQ_MODE LPM \
-          RX_COUPLING AC \
-          RX_TERMINATION PROGRAMMABLE \
-          RX_RATE_GROUP A \
-          RX_TERMINATION_PROG_VALUE 800 \
-          RX_PPM_OFFSET 0 \
-          RX_64B66B_DESCRAMBLER false \
-          RX_64B66B_DECODER false \
-          RX_64B66B_CRC false \
-          OOB_ENABLE false \
-          RX_COMMA_ALIGN_WORD 1 \
-          RX_COMMA_SHOW_REALIGN_ENABLE false \
-          PCIE_ENABLE false \
-          RX_COMMA_P_ENABLE $comma_p_enable \
-          RX_COMMA_M_ENABLE $comma_m_enable \
-          RX_COMMA_DOUBLE_ENABLE false \
-          RX_COMMA_P_VAL 0101111100 \
-          RX_COMMA_M_VAL 1010000011 \
-          RX_COMMA_MASK $comma_mask \
-          RX_SLIDE_MODE PCS \
-          RX_SSC_PPM 0 \
-          RX_CB_NUM_SEQ 0 \
-          RX_CB_LEN_SEQ 1 \
-          RX_CB_MAX_SKEW 1 \
-          RX_CB_MAX_LEVEL 1 \
-          RX_CB_MASK_0_0 false \
-          RX_CB_VAL_0_0 00000000 \
-          RX_CB_K_0_0 false \
-          RX_CB_DISP_0_0 false \
-          RX_CB_MASK_0_1 false \
-          RX_CB_VAL_0_1 00000000 \
-          RX_CB_K_0_1 false \
-          RX_CB_DISP_0_1 false \
-          RX_CB_MASK_0_2 false \
-          RX_CB_VAL_0_2 00000000 \
-          RX_CB_K_0_2 false \
-          RX_CB_DISP_0_2 false \
-          RX_CB_MASK_0_3 false \
-          RX_CB_VAL_0_3 00000000 \
-          RX_CB_K_0_3 false \
-          RX_CB_DISP_0_3 false \
-          RX_CB_MASK_1_0 false \
-          RX_CB_VAL_1_0 00000000 \
-          RX_CB_K_1_0 false \
-          RX_CB_DISP_1_0 false \
-          RX_CB_MASK_1_1 false \
-          RX_CB_VAL_1_1 00000000 \
-          RX_CB_K_1_1 false \
-          RX_CB_DISP_1_1 false \
-          RX_CB_MASK_1_2 false \
-          RX_CB_VAL_1_2 00000000 \
-          RX_CB_K_1_2 false \
-          RX_CB_DISP_1_2 false \
-          RX_CB_MASK_1_3 false \
-          RX_CB_VAL_1_3 00000000 \
-          RX_CB_K_1_3 false \
-          RX_CB_DISP_1_3 false \
-          RX_CC_NUM_SEQ 0 \
-          RX_CC_LEN_SEQ 1 \
-          RX_CC_PERIODICITY 5000 \
-          RX_CC_KEEP_IDLE DISABLE \
-          RX_CC_PRECEDENCE ENABLE \
-          RX_CC_REPEAT_WAIT 0 \
-          RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \
-          RX_CC_MASK_0_0 false \
-          RX_CC_VAL_0_0 00000000 \
-          RX_CC_K_0_0 false \
-          RX_CC_DISP_0_0 false \
-          RX_CC_MASK_0_1 false \
-          RX_CC_VAL_0_1 00000000 \
-          RX_CC_K_0_1 false \
-          RX_CC_DISP_0_1 false \
-          RX_CC_MASK_0_2 false \
-          RX_CC_VAL_0_2 00000000 \
-          RX_CC_K_0_2 false \
-          RX_CC_DISP_0_2 false \
-          RX_CC_MASK_0_3 false \
-          RX_CC_VAL_0_3 00000000 \
-          RX_CC_K_0_3 false \
-          RX_CC_DISP_0_3 false \
-          RX_CC_MASK_1_0 false \
-          RX_CC_VAL_1_0 00000000 \
-          RX_CC_K_1_0 false \
-          RX_CC_DISP_1_0 false \
-          RX_CC_MASK_1_1 false \
-          RX_CC_VAL_1_1 00000000 \
-          RX_CC_K_1_1 false \
-          RX_CC_DISP_1_1 false \
-          RX_CC_MASK_1_2 false \
-          RX_CC_VAL_1_2 00000000 \
-          RX_CC_K_1_2 false \
-          RX_CC_DISP_1_2 false \
-          RX_CC_MASK_1_3 false \
-          RX_CC_VAL_1_3 00000000 \
-          RX_CC_K_1_3 false \
-          RX_CC_DISP_1_3 false \
-          PCIE_USERCLK2_FREQ 250 \
-          PCIE_USERCLK_FREQ 250 \
-          RX_JTOL_FC 10 \
-          RX_JTOL_LF_SLOPE -20 \
-          RX_BUFFER_BYPASS_MODE Fast_Sync \
-          RX_BUFFER_BYPASS_MODE_LANE MULTI \
-          RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \
-          RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \
-          RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
-          TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
-          RESET_SEQUENCE_INTERVAL 0 \
-          RX_COMMA_PRESET NONE \
-          RX_COMMA_VALID_ONLY 0 \
-          ] \
-      ] [get_bd_cells ${ip_name}/${rx_bridge}]
-
-    set_property -dict [list \
-      CONFIG.BYPASS_MODE {true} \
-      CONFIG.REG_CONF_INTF {AXI_LITE} \
-      CONFIG.IP_PRESET ${preset} \
-      CONFIG.IP_GT_DIRECTION {SIMPLEX_TX} \
-      CONFIG.IP_NO_OF_TX_LANES ${tx_num_lanes} \
-      CONFIG.IP_LR0_SETTINGS [list \
-        PRESET $preset \
-        INTERNAL_PRESET JESD204_${jesd_mode} \
-        GT_TYPE $transceiver \
-        GT_DIRECTION SIMPLEX_TX \
-        TX_LINE_RATE $tx_lane_rate \
-        TX_PLL_TYPE LCPLL \
-        TX_REFCLK_FREQUENCY $ref_clock \
-        TX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
-        TX_FRACN_ENABLED true \
-        TX_FRACN_NUMERATOR 0 \
-        TX_REFCLK_SOURCE R0 \
-        TX_DATA_ENCODING $data_encoding \
-        TX_USER_DATA_WIDTH $datapath_width \
-        TX_INT_DATA_WIDTH $internal_datapath_width \
-        TX_BUFFER_MODE 1 \
-        TX_BUFFER_BYPASS_MODE Fast_Sync \
-        TX_PIPM_ENABLE false \
-        TX_OUTCLK_SOURCE TXPROGDIVCLK \
-        TXPROGDIV_FREQ_ENABLE true \
-        TXPROGDIV_FREQ_SOURCE LCPLL \
-        TXPROGDIV_FREQ_VAL $tx_progdiv_clock \
-        TX_DIFF_SWING_EMPH_MODE CUSTOM \
-        TX_64B66B_SCRAMBLER false \
-        TX_64B66B_ENCODER false \
-        TX_64B66B_CRC false \
-        TX_RATE_GROUP A \
-        RX_LINE_RATE $rx_lane_rate \
-        RX_PLL_TYPE LCPLL \
-        RX_REFCLK_FREQUENCY $ref_clock \
-        RX_ACTUAL_REFCLK_FREQUENCY $ref_clock \
-        RX_FRACN_ENABLED true \
-        RX_FRACN_NUMERATOR 0 \
-        RX_REFCLK_SOURCE R0 \
-        RX_DATA_DECODING $data_encoding \
-        RX_USER_DATA_WIDTH $datapath_width \
-        RX_INT_DATA_WIDTH $internal_datapath_width \
-        RX_BUFFER_MODE 1 \
-        RX_OUTCLK_SOURCE RXPROGDIVCLK \
-        RXPROGDIV_FREQ_ENABLE true \
-        RXPROGDIV_FREQ_SOURCE LCPLL \
-        RXPROGDIV_FREQ_VAL $rx_progdiv_clock \
-        INS_LOSS_NYQ 12 \
-        RX_EQ_MODE LPM \
-        RX_COUPLING AC \
-        RX_TERMINATION PROGRAMMABLE \
-        RX_RATE_GROUP A \
-        RX_TERMINATION_PROG_VALUE 800 \
-        RX_PPM_OFFSET 0 \
-        RX_64B66B_DESCRAMBLER false \
-        RX_64B66B_DECODER false \
-        RX_64B66B_CRC false \
-        OOB_ENABLE false \
-        RX_COMMA_ALIGN_WORD 1 \
-        RX_COMMA_SHOW_REALIGN_ENABLE false \
-        PCIE_ENABLE false \
-        RX_COMMA_P_ENABLE $comma_p_enable \
-        RX_COMMA_M_ENABLE $comma_m_enable \
-        RX_COMMA_DOUBLE_ENABLE false \
-        RX_COMMA_P_VAL 0101111100 \
-        RX_COMMA_M_VAL 1010000011 \
-        RX_COMMA_MASK $comma_mask \
-        RX_SLIDE_MODE PCS \
-        RX_SSC_PPM 0 \
-        RX_CB_NUM_SEQ 0 \
-        RX_CB_LEN_SEQ 1 \
-        RX_CB_MAX_SKEW 1 \
-        RX_CB_MAX_LEVEL 1 \
-        RX_CB_MASK_0_0 false \
-        RX_CB_VAL_0_0 00000000 \
-        RX_CB_K_0_0 false \
-        RX_CB_DISP_0_0 false \
-        RX_CB_MASK_0_1 false \
-        RX_CB_VAL_0_1 00000000 \
-        RX_CB_K_0_1 false \
-        RX_CB_DISP_0_1 false \
-        RX_CB_MASK_0_2 false \
-        RX_CB_VAL_0_2 00000000 \
-        RX_CB_K_0_2 false \
-        RX_CB_DISP_0_2 false \
-        RX_CB_MASK_0_3 false \
-        RX_CB_VAL_0_3 00000000 \
-        RX_CB_K_0_3 false \
-        RX_CB_DISP_0_3 false \
-        RX_CB_MASK_1_0 false \
-        RX_CB_VAL_1_0 00000000 \
-        RX_CB_K_1_0 false \
-        RX_CB_DISP_1_0 false \
-        RX_CB_MASK_1_1 false \
-        RX_CB_VAL_1_1 00000000 \
-        RX_CB_K_1_1 false \
-        RX_CB_DISP_1_1 false \
-        RX_CB_MASK_1_2 false \
-        RX_CB_VAL_1_2 00000000 \
-        RX_CB_K_1_2 false \
-        RX_CB_DISP_1_2 false \
-        RX_CB_MASK_1_3 false \
-        RX_CB_VAL_1_3 00000000 \
-        RX_CB_K_1_3 false \
-        RX_CB_DISP_1_3 false \
-        RX_CC_NUM_SEQ 0 \
-        RX_CC_LEN_SEQ 1 \
-        RX_CC_PERIODICITY 5000 \
-        RX_CC_KEEP_IDLE DISABLE \
-        RX_CC_PRECEDENCE ENABLE \
-        RX_CC_REPEAT_WAIT 0 \
-        RX_CC_VAL 00000000000000000000000000000000000000000000000000000000000000000000000000000000 \
-        RX_CC_MASK_0_0 false \
-        RX_CC_VAL_0_0 00000000 \
-        RX_CC_K_0_0 false \
-        RX_CC_DISP_0_0 false \
-        RX_CC_MASK_0_1 false \
-        RX_CC_VAL_0_1 00000000 \
-        RX_CC_K_0_1 false \
-        RX_CC_DISP_0_1 false \
-        RX_CC_MASK_0_2 false \
-        RX_CC_VAL_0_2 00000000 \
-        RX_CC_K_0_2 false \
-        RX_CC_DISP_0_2 false \
-        RX_CC_MASK_0_3 false \
-        RX_CC_VAL_0_3 00000000 \
-        RX_CC_K_0_3 false \
-        RX_CC_DISP_0_3 false \
-        RX_CC_MASK_1_0 false \
-        RX_CC_VAL_1_0 00000000 \
-        RX_CC_K_1_0 false \
-        RX_CC_DISP_1_0 false \
-        RX_CC_MASK_1_1 false \
-        RX_CC_VAL_1_1 00000000 \
-        RX_CC_K_1_1 false \
-        RX_CC_DISP_1_1 false \
-        RX_CC_MASK_1_2 false \
-        RX_CC_VAL_1_2 00000000 \
-        RX_CC_K_1_2 false \
-        RX_CC_DISP_1_2 false \
-        RX_CC_MASK_1_3 false \
-        RX_CC_VAL_1_3 00000000 \
-        RX_CC_K_1_3 false \
-        RX_CC_DISP_1_3 false \
-        PCIE_USERCLK2_FREQ 250 \
-        PCIE_USERCLK_FREQ 250 \
-        RX_JTOL_FC 10 \
-        RX_JTOL_LF_SLOPE -20 \
-        RX_BUFFER_BYPASS_MODE Fast_Sync \
-        RX_BUFFER_BYPASS_MODE_LANE MULTI \
-        RX_BUFFER_RESET_ON_CB_CHANGE ENABLE \
-        RX_BUFFER_RESET_ON_COMMAALIGN DISABLE \
-        RX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
-        TX_BUFFER_RESET_ON_RATE_CHANGE ENABLE \
-        RESET_SEQUENCE_INTERVAL 0 \
-        RX_COMMA_PRESET NONE \
-        RX_COMMA_VALID_ONLY 0 \
-        ] \
-    ] [get_bd_cells ${ip_name}/${tx_bridge}]
-  }
-  set quad_num_rx_lane $rx_num_lanes
-  set quad_num_tx_lane $tx_num_lanes
-  for {set j 0} {$j < $num_quads} {incr j} {
-    set rx_num [expr min($quad_num_rx_lane, 4)]
-    set tx_num [expr min($quad_num_tx_lane, 4)]
-    ad_ip_instance gt_quad_base ${ip_name}/gt_quad_base_${j}
-    set_property -dict [list \
-      CONFIG.REG_CONF_INTF.VALUE_MODE {MANUAL} \
-      CONFIG.REG_CONF_INTF {AXI_LITE} \
-      CONFIG.PROT0_GT_DIRECTION ${gt_direction} \
-    ] [get_bd_cells ${ip_name}/gt_quad_base_${j}]
-    if {$asymmetric_mode} {
-      # When we have multiple protocols (different number of lanes on Rx and Tx) we have to manually set the protocols to pass design validation
-      set_property -dict [list \
-        CONFIG.GT_TYPE.VALUE_MODE AUTO \
-        CONFIG.PROT0_RX_MASTERCLK_SRC.VALUE_MODE RX0 \
-        CONFIG.PROT1_TX_MASTERCLK_SRC.VALUE_MODE TX0 \
-        CONFIG.PROT1_ENABLE.VALUE_MODE MANUAL \
-        CONFIG.PROT0_GT_DIRECTION.VALUE_MODE MANUAL \
-        CONFIG.TX0_LANE_SEL.VALUE_MODE AUTO \
-        CONFIG.PROT0_NO_OF_RX_LANES.VALUE_MODE MANUAL \
-        CONFIG.PROT1_NO_OF_TX_LANES.VALUE_MODE MANUAL \
-        CONFIG.PROT1_GT_DIRECTION.VALUE_MODE MANUAL \
-      ] [get_bd_cells ${ip_name}/gt_quad_base_${j}]
-
-      if {$rx_num > 0} {
-        set_property -dict [list \
-          CONFIG.PROT0_GT_DIRECTION {SIMPLEX_RX} \
-          CONFIG.PROT0_NO_OF_RX_LANES $rx_num \
-        ] [get_bd_cells ${ip_name}/gt_quad_base_${j}]
-        for {set i 0} {$i < $rx_num} {incr i} {
-          set_property -dict [list \
-            CONFIG.RX${i}_LANE_SEL.VALUE_MODE MANUAL \
-          ] [get_bd_cells ${ip_name}/gt_quad_base_${j}]
-        }
-      }
-      if {$tx_num > 0} {
-        set_property -dict [list \
-          CONFIG.PROT1_ENABLE {true} \
-          CONFIG.PROT1_GT_DIRECTION {SIMPLEX_TX} \
-          CONFIG.PROT1_NO_OF_TX_LANES $tx_num \
-        ] [get_bd_cells ${ip_name}/gt_quad_base_${j}]
-        for {set i 0} {$i < $tx_num} {incr i} {
-          set_property -dict [list \
-            CONFIG.TX${i}_LANE_SEL.VALUE_MODE MANUAL \
-          ] [get_bd_cells ${ip_name}/gt_quad_base_${j}]
-        }
-      }
-
-      set quad_num_rx_lane [expr $quad_num_rx_lane - $rx_num]
-      set quad_num_tx_lane [expr $quad_num_tx_lane - $tx_num]
-    }
-
-    if {$intf_cfg != "TX"} {
-      # Share the link clock generated by the first quad
-      if {$j == 0} {
-        ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx
-        ad_connect ${ip_name}/gt_quad_base_0/ch0_rxoutclk ${ip_name}/bufg_gt_rx/outclk
-        ad_connect ${ip_name}/${rx_bridge}/rx_clr_out ${ip_name}/bufg_gt_rx/gt_bufgtclr
-        ad_connect ${ip_name}/${rx_bridge}/rxusrclk_out ${ip_name}/rxusrclk_out
-        ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/${rx_bridge}/gt_rxusrclk
-      }
-      create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_p
-      create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_n
-      ad_connect ${ip_name}/gt_quad_base_${j}/rxp ${ip_name}/rx_${j}_p
-      ad_connect ${ip_name}/gt_quad_base_${j}/rxn ${ip_name}/rx_${j}_n
-    }
-    if {$intf_cfg != "RX"} {
-      # Share the link clock generated by the first quad
-      if {$j == 0} {
-        ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx
-        ad_connect ${ip_name}/gt_quad_base_0/ch0_txoutclk ${ip_name}/bufg_gt_tx/outclk
-        ad_connect ${ip_name}/${tx_bridge}/tx_clr_out ${ip_name}/bufg_gt_tx/gt_bufgtclr
-        ad_connect ${ip_name}/${tx_bridge}/txusrclk_out ${ip_name}/txusrclk_out
-        ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/${tx_bridge}/gt_txusrclk
-      }
-      create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_p
-      create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_n
-      ad_connect ${ip_name}/gt_quad_base_${j}/txp ${ip_name}/tx_${j}_p
-      ad_connect ${ip_name}/gt_quad_base_${j}/txn ${ip_name}/tx_${j}_n
-    }
-  }
-
-  if {$intf_cfg != "TX"} {
-    for {set j 0} {$j < $rx_num_lanes} {incr j} {
-      set quad_index [expr int($j / 4)]
-      set rx_index [expr $j % 4]
-
-      ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/gt_quad_base_${quad_index}/ch${rx_index}_rxusrclk
-
-      ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} [list \
-        LINK_MODE $link_mode \
-      ]
-      ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/${rx_bridge}/GT_RX${j}_EXT
-      ad_connect ${ip_name}/${rx_bridge}/GT_RX${j} ${ip_name}/gt_quad_base_${quad_index}/RX${rx_index}_GT_IP_Interface
-
-      create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
-      ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
-      ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_rx/usrclk
-      ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align
-
-      if {$asymmetric_mode} {
-        set_property CONFIG.RX${rx_index}_LANE_SEL {PROT0} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}]
-      }
-    }
-  }
-  if {$intf_cfg != "RX"} {
-    for {set j 0} {$j < $tx_num_lanes} {incr j} {
-      set quad_index [expr int($j / 4)]
-      set tx_index [expr $j % 4]
-
-      ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/gt_quad_base_${quad_index}/ch${tx_index}_txusrclk
-
-      ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} [list \
-        LINK_MODE $link_mode \
-      ]
-      ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/${tx_bridge}/GT_TX${j}_EXT
-      ad_connect ${ip_name}/${tx_bridge}/GT_TX${j} ${ip_name}/gt_quad_base_${quad_index}/TX${tx_index}_GT_IP_Interface
-
-      create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
-      ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
-      ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_tx/usrclk
-
-      if {$asymmetric_mode} {
-        set_property CONFIG.TX${tx_index}_LANE_SEL {PROT1} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}]
-      }
-    }
-  }
-
-  if {$asymmetric_mode} {
-    # Map unused quad lanes as unconnected
-    set max_num_of_lanes [expr $num_quads * 4]
-    for {set j $rx_num_lanes} {$intf_cfg != "TX" && $j < $max_num_of_lanes} {incr j} {
-      set quad_index [expr $j / 4]
-      set lane_index [expr $j % 4]
-      set_property CONFIG.RX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}]
-    }
-    for {set j $tx_num_lanes} {$intf_cfg != "RX" && $j < $max_num_of_lanes} {incr j} {
-      set quad_index [expr $j / 4]
-      set lane_index [expr $j % 4]
-      set_property CONFIG.TX${lane_index}_LANE_SEL {unconnected} [get_bd_cells ${ip_name}/gt_quad_base_${quad_index}]
-    }
-  }
-
-  # Clocks
-  ad_connect ${ip_name}/s_axi_clk ${ip_name}/${rx_bridge}/apb3clk
-  if {$asymmetric_mode} {
-    ad_connect ${ip_name}/s_axi_clk ${ip_name}/${tx_bridge}/apb3clk
-  }
-  for {set j 0} {$j < $num_quads} {incr j} {
-    ad_connect ${ip_name}/GT_REFCLK    ${ip_name}/gt_quad_base_${j}/GT_REFCLK0
-    ad_connect ${ip_name}/s_axi_clk    ${ip_name}/gt_quad_base_${j}/s_axi_lite_clk
-    ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gt_quad_base_${j}/s_axi_lite_resetn
-  }
-
-  # Instantiate reset helper logic
-  create_reset_logic $ip_name $rx_num_lanes $tx_num_lanes $intf_cfg
-}
diff --git a/projects/ad9081_fmca_ebz/vck190/system_bd.tcl b/projects/ad9081_fmca_ebz/vck190/system_bd.tcl
index dc13abf18a0..88388c6fba0 100644
--- a/projects/ad9081_fmca_ebz/vck190/system_bd.tcl
+++ b/projects/ad9081_fmca_ebz/vck190/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2024, 2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -15,10 +15,7 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 # use versal transceiver wizard
 set ADI_PHY_SEL 0
 set TRANSCEIVER_TYPE GTY
-
-adi_project_files ad9081_fmca_ebz_vck190 [list \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
+set EXTERNAL_LINK_CLK 0
 
 source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
diff --git a/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl b/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl
index 0ca977c8004..5c3b56a6b14 100644
--- a/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl
+++ b/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2024-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024, 2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -15,10 +15,7 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 # use versal transceiver wizard
 set ADI_PHY_SEL 0
 set TRANSCEIVER_TYPE GTYP
-
-adi_project_files ad9081_fmca_ebz_vpk180 [list \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
+set EXTERNAL_LINK_CLK 0
 
 source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
 source $ad_hdl_dir/projects/scripts/adi_pd.tcl
diff --git a/projects/ad9082_fmca_ebz/vck190/system_bd.tcl b/projects/ad9082_fmca_ebz/vck190/system_bd.tcl
index 5e4e898b05a..430f5aae509 100644
--- a/projects/ad9082_fmca_ebz/vck190/system_bd.tcl
+++ b/projects/ad9082_fmca_ebz/vck190/system_bd.tcl
@@ -1,10 +1,6 @@
 ###############################################################################
-## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2023-2024, 2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-adi_project_files ad9082_fmca_ebz_vck190 [list \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
-
 source $ad_hdl_dir/projects/ad9081_fmca_ebz/vck190/system_bd.tcl
diff --git a/projects/ad9082_fmca_ebz/vpk180/system_bd.tcl b/projects/ad9082_fmca_ebz/vpk180/system_bd.tcl
index 4381e8052b9..a1b2d964f18 100644
--- a/projects/ad9082_fmca_ebz/vpk180/system_bd.tcl
+++ b/projects/ad9082_fmca_ebz/vpk180/system_bd.tcl
@@ -1,10 +1,6 @@
 ###############################################################################
-## Copyright (C) 2024-2024 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2024-2024, 2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
-adi_project_files ad9082_fmca_ebz_vpk180 [list \
-  "$ad_hdl_dir/library/util_cdc/sync_bits.v" \
-]
-
 source $ad_hdl_dir/projects/ad9081_fmca_ebz/vpk180/system_bd.tcl
diff --git a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl
index 786695bc955..c32548dd385 100755
--- a/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl
+++ b/projects/ad9084_ebz/common/ad9084_ebz_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2025-2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -7,6 +7,10 @@ if {![info exists ADI_PHY_SEL]} {
   set ADI_PHY_SEL 1
 }
 
+if {![info exists EXTERNAL_LINK_CLK]} {
+  set EXTERNAL_LINK_CLK 0
+}
+
 source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
 source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
 
@@ -379,8 +383,9 @@ if {$ADI_PHY_SEL} {
   create_bd_port -dir I -from [expr $RX_NUM_LINKS - 1] -to 0 tx_sync_0
 
   set REF_CLK_RATE $ad_project_params(REF_CLK_RATE)
+  set CONSECUTIVE_QUAD_MODE [expr { $ASYMMETRIC_A_B_MODE == 1 ? true : false }]
   # instantiate versal phy
-  create_versal_jesd_xcvr_subsystem jesd204_phy $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX false
+  create_versal_jesd_xcvr_subsystem jesd204_phy $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX $CONSECUTIVE_QUAD_MODE $EXTERNAL_LINK_CLK
   # reset generator
   ad_ip_instance proc_sys_reset rx_device_clk_rstgen
   ad_connect rx_device_clk rx_device_clk_rstgen/slowest_sync_clk
@@ -433,7 +438,7 @@ if {$ASYMMETRIC_A_B_MODE} {
     ad_ip_parameter axi_apollo_tx_b_xcvr CONFIG.SYS_CLK_SEL 0x2 ; # QPLL1
   } else {
     # instantiate versal phy
-    create_versal_jesd_xcvr_subsystem jesd204_phy_b $JESD_MODE $RX_B_NUM_OF_LANES $TX_B_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX
+    create_versal_jesd_xcvr_subsystem jesd204_phy_b $JESD_MODE $RX_B_NUM_OF_LANES $TX_B_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX $CONSECUTIVE_QUAD_MODE $EXTERNAL_LINK_CLK
 
     ad_connect gt_b_reset jesd204_phy_b/gtreset_in
     ad_connect gt_b_reset_rx_datapath jesd204_phy_b/gtreset_rx_datapath
@@ -712,10 +717,6 @@ if {$ADI_PHY_SEL} {
   if {$JESD_MODE == "8B10B"} {
     ad_connect axi_apollo_rx_jesd/phy_en_char_align jesd204_phy/en_char_align
     ad_connect axi_apollo_rx_jesd/sync rx_sync_0
-  } else {
-    ad_connect GND jesd204_phy/en_char_align
-  }
-  if {$JESD_MODE == "8B10B"} {
     ad_connect axi_apollo_tx_jesd/sync tx_sync_0
   }
 
@@ -741,11 +742,7 @@ if {$ADI_PHY_SEL} {
     if {$JESD_MODE == "8B10B"} {
     ad_connect axi_apollo_rx_b_jesd/phy_en_char_align jesd204_phy_b/en_char_align
     ad_connect axi_apollo_rx_b_jesd/sync rx_sync_12
-    } else {
-      ad_connect GND jesd204_phy_b/en_char_align
-    }
-    if {$JESD_MODE == "8B10B"} {
-      ad_connect axi_apollo_tx_b_jesd/sync tx_sync_0
+    ad_connect axi_apollo_tx_b_jesd/sync tx_sync_0
     }
   }
 
@@ -1267,4 +1264,4 @@ if {$TDD_SUPPORT} {
     ad_connect GND $dac_b_data_offload_name/sync_ext
     ad_connect GND $adc_b_data_offload_name/sync_ext
   }
-}
\ No newline at end of file
+}
diff --git a/projects/ad9084_ebz/vck190/system_bd.tcl b/projects/ad9084_ebz/vck190/system_bd.tcl
index 6d7c575c65b..5b4b6b90c6b 100755
--- a/projects/ad9084_ebz/vck190/system_bd.tcl
+++ b/projects/ad9084_ebz/vck190/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2025-2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -38,6 +38,7 @@ if {!$SIDE_B_ONLY} {
 set ADI_PHY_SEL 0
 set MAX_NUMBER_OF_QUADS 3
 set TRANSCEIVER_TYPE GTY
+set EXTERNAL_LINK_CLK 0
 set HSCI_BANKS 2
 set HSCI_ENABLE [ expr { [info exists ad_project_params(HSCI_ENABLE)] \
                           ? $ad_project_params(HSCI_ENABLE) : 1 } ]
diff --git a/projects/ad9084_ebz/vpk180/system_bd.tcl b/projects/ad9084_ebz/vpk180/system_bd.tcl
index 1b1087d1124..83cd565ccfd 100755
--- a/projects/ad9084_ebz/vpk180/system_bd.tcl
+++ b/projects/ad9084_ebz/vpk180/system_bd.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2025-2026 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
@@ -25,6 +25,7 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
 set ADI_PHY_SEL 0
 set MAX_NUMBER_OF_QUADS 2
 set TRANSCEIVER_TYPE GTYP
+set EXTERNAL_LINK_CLK 0
 set HSCI_BANKS 1
 set HSCI_ENABLE [ expr { [info exists ad_project_params(HSCI_ENABLE)] \
                           ? $ad_project_params(HSCI_ENABLE) : 1 } ]