diff --git a/README.md b/README.md
index 3315cb2..8182c4d 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
 ![pynq_logo](https://github.com/Xilinx/PYNQ/raw/master/logo.png)
-### version 0.1.7
+### version 0.1.8
 
 PYNQ-Metadata is an open-source project from Xilinx and is part of the PYNQ ecosystem. It's aims are to provide an abstract description of reconfigurable system designs. It is currently used internally within PYNQ to represent the hardware design currently configured in the Programmable Logic of Zynq-based devices. It is currently in pre-release.  
 
@@ -37,6 +37,7 @@ All python code for the ``PYNQ-Metadata`` package can be found in the `/pynqmeta
 
 
 ## Changelog
+* v0.1.8 : Add parsing of CLKSRC
 * v0.1.7 : Relaxing constraint on address mapping due to issues with rfsoc4x2_base parsing. 
 * v0.1.6 : Python3.11 support added (Thanks @modularizer) 
 * v0.1.5 : Prevent parsing error when external AXI ports are present in the design. 
diff --git a/pynqmetadata/__init__.py b/pynqmetadata/__init__.py
index 90ad861..f22307b 100644
--- a/pynqmetadata/__init__.py
+++ b/pynqmetadata/__init__.py
@@ -29,4 +29,4 @@
 from .models.clk_port import ClkPort
 from .models.rst_port import RstPort
 
-__version__ = "0.1.7"
+__version__ = "0.1.8"
diff --git a/pynqmetadata/models/proc_sys_core.py b/pynqmetadata/models/proc_sys_core.py
index 6bca28f..bc280ac 100644
--- a/pynqmetadata/models/proc_sys_core.py
+++ b/pynqmetadata/models/proc_sys_core.py
@@ -65,6 +65,25 @@ def gpio(self) -> Dict[str, object]:
 
             return ret
 
+    def srcsel_param_name(self, clk_id: int) -> str:
+        """Returns the name of the clock SRCSEL parameter for this PS.
+        Default is the same format as Ultrascale."""
+        return f"PSU__CRL_APB__PL{clk_id}_REF_CTRL__SRCSEL"
+
+    def find_srcsel(self, clk_id: int) -> bool:
+        """For a given clock id return the SRCSEL value"""
+        srcsel = self.srcsel_param_name(clk_id)
+        if srcsel in self.parameters:
+            value = self.parameters[srcsel].value
+            if value is not None:
+                return value
+            else:
+                return None
+        else:
+            raise ParameterNotFound(
+                f"Unable to find srcsel {srcsel} for ps {self.ref}"
+            )
+
     def clk_div_param_name(self, clk_id: int, div_id: int) -> str:
         """Returns the name of the clock div parameter for this PS.
         Default is the same format as Ultrascale."""
diff --git a/pynqmetadata/models/ultrascale_proc_sys_core.py b/pynqmetadata/models/ultrascale_proc_sys_core.py
index c0c3275..26c54f3 100644
--- a/pynqmetadata/models/ultrascale_proc_sys_core.py
+++ b/pynqmetadata/models/ultrascale_proc_sys_core.py
@@ -18,6 +18,10 @@ class UltrascaleProcSysCore(ProcSysCore):
         default_factory=lambda: ({"pl_ps_irq0": ((121, 8),), "pl_ps_irq1": ((136, 8),)})
     )
 
+    def srcsel_param_name(self, clk_id: int) -> str:
+        """Returns the name of the clock SRCSEL parameter for this PS"""
+        return f"PSU__CRL_APB__PL{clk_id}_REF_CTRL__SRCSEL"
+
     def clk_div_param_name(self, clk_id: int, div_id: int) -> str:
         """Returns the name of the clock div parameter for this PS"""
         return f"PSU__CRL_APB__PL{clk_id}_REF_CTRL__DIVISOR{div_id}"
diff --git a/pynqmetadata/models/zynq_proc_sys_core.py b/pynqmetadata/models/zynq_proc_sys_core.py
index 062de0a..8384282 100644
--- a/pynqmetadata/models/zynq_proc_sys_core.py
+++ b/pynqmetadata/models/zynq_proc_sys_core.py
@@ -22,6 +22,10 @@ class ZynqProcSysCore(ProcSysCore):
         )
     )
 
+    def srcsel_param_name(self, clk_id: int) -> str:
+        """Returns the name of the clock SRCSEL parameter for this PS"""
+        return f"PCW_FCLK{clk_id}_PERIPHERAL_CLKSRC"
+
     def clk_div_param_name(self, clk_id: int, div_id: int) -> str:
         """Returns the name of the clock div parameters for this PS"""
         return f"PCW_FCLK{clk_id}_PERIPHERAL_DIVISOR{div_id}"
diff --git a/pynqmetadata/version.txt b/pynqmetadata/version.txt
index 1180819..699c6c6 100644
--- a/pynqmetadata/version.txt
+++ b/pynqmetadata/version.txt
@@ -1 +1 @@
-0.1.7
+0.1.8
diff --git a/pynqmetadata/views/runtime/clock_dict_view.py b/pynqmetadata/views/runtime/clock_dict_view.py
index 3ce7ed7..e7a4bb1 100644
--- a/pynqmetadata/views/runtime/clock_dict_view.py
+++ b/pynqmetadata/views/runtime/clock_dict_view.py
@@ -20,6 +20,7 @@ class ClockDictView:
         * 'enable' : int whether the clock is enabled
         * 'divisor0' : int divisor value for the clock
         * 'divisor1' : int divisor value for the clock
+        * 'srcsel' : str PLL available for selection
     """
 
     def __init__(self, module: Module) -> None:
@@ -34,6 +35,7 @@ def clock_dict(self) -> Dict:
                 for i in range(4):
                     repr_dict[i] = {}
                     repr_dict[i]["enable"] = int(core.find_clock_enable(i))
+                    repr_dict[i]["srcsel"] = str(core.find_srcsel(i))
                     for j in range(2):
                         repr_dict[i][f"divisor{j}"] = core.find_clock_divisor(i, j)