diff --git a/src/Design.cc b/src/Design.cc index 852df483176..e37afe27947 100644 --- a/src/Design.cc +++ b/src/Design.cc @@ -190,7 +190,7 @@ bool Design::isSequential(odb::dbMaster* master) if (!lib_cell) { return false; } - return lib_cell->hasSequentials(); + return lib_cell->isSequential(); } bool Design::isInClock(odb::dbInst* inst) diff --git a/src/cts/src/LatencyBalancer.cpp b/src/cts/src/LatencyBalancer.cpp index fefe6aaa4ea..c422ce7521b 100644 --- a/src/cts/src/LatencyBalancer.cpp +++ b/src/cts/src/LatencyBalancer.cpp @@ -582,7 +582,7 @@ bool LatencyBalancer::propagateClock(odb::dbITerm* input) return true; } // Combinational components - if (!libertyCell->hasSequentials()) { + if (!libertyCell->isSequential()) { return true; } sta::LibertyPort* inputPort diff --git a/src/cut/src/abc_library_factory.cpp b/src/cut/src/abc_library_factory.cpp index 149dc2428c7..3ac10774aef 100644 --- a/src/cut/src/abc_library_factory.cpp +++ b/src/cut/src/abc_library_factory.cpp @@ -78,7 +78,7 @@ static bool IsCombinational(sta::LibertyCell* cell) return false; } return (!cell->isClockGate() && !cell->isPad() && !cell->isMacro() - && !cell->hasSequentials() && !cell->isLevelShifter() + && !cell->isSequential() && !cell->isLevelShifter() && !cell->isIsolationCell() && !cell->isMemory()); } diff --git a/src/cut/src/blif.cpp b/src/cut/src/blif.cpp index 9d08ee4ff31..4935fbcc6f9 100644 --- a/src/cut/src/blif.cpp +++ b/src/cut/src/blif.cpp @@ -95,7 +95,7 @@ bool Blif::writeBlif(const char* file_name, bool write_arrival_requireds) auto master_name = master->getName(); std::string current_gate - = ((cell->hasSequentials()) ? ".mlatch " : ".gate ") + master_name; + = ((cell->isSequential()) ? ".mlatch " : ".gate ") + master_name; std::string current_connections, current_clock; std::set current_clocks; @@ -250,10 +250,10 @@ bool Blif::writeBlif(const char* file_name, bool write_arrival_requireds) current_gate += current_connections; - if (cell->hasSequentials() && current_clocks.size() != 1) { + if (cell->isSequential() && current_clocks.size() != 1) { continue; } - if (cell->hasSequentials()) { + if (cell->isSequential()) { current_gate += " " + current_clock; } diff --git a/src/cut/src/logic_cut.cpp b/src/cut/src/logic_cut.cpp index fba6a9896f1..3c8c6c40c27 100644 --- a/src/cut/src/logic_cut.cpp +++ b/src/cut/src/logic_cut.cpp @@ -212,7 +212,7 @@ void ConnectPinToDriver( abc::Abc_Obj_t* abc_net = abc::Abc_NtkCreateNet(&abc_network); if (network->isTopInstance(driver_instance) - || network->libertyCell(driver_instance)->hasSequentials()) { + || network->libertyCell(driver_instance)->isSequential()) { abc::Abc_Obj_t* abc_input = abc::Abc_NtkCreatePi(&abc_network); abc::Abc_ObjAddFanin(abc_net, abc_input); std::string driver_name = network->name(driver); diff --git a/src/dbSta/src/dbNetwork.cc b/src/dbSta/src/dbNetwork.cc index d5bcd6a0a2a..6f42e34adec 100644 --- a/src/dbSta/src/dbNetwork.cc +++ b/src/dbSta/src/dbNetwork.cc @@ -5603,7 +5603,7 @@ bool dbNetwork::isValidFlop(odb::dbInst* FF) const return false; } const LibertyCell* lib_cell = testCell(cell); - if (lib_cell == nullptr || !lib_cell->hasSequentials()) { + if (lib_cell == nullptr || !lib_cell->isSequential()) { return false; } diff --git a/src/dbSta/src/dbSta.cc b/src/dbSta/src/dbSta.cc index 2d98c3b2ab3..f0a051abe7e 100644 --- a/src/dbSta/src/dbSta.cc +++ b/src/dbSta/src/dbSta.cc @@ -614,7 +614,7 @@ dbSta::InstType dbSta::getInstanceType(odb::dbInst* inst) if (lib_cell->isLevelShifter()) { return STD_LEVEL_SHIFT; } - if (lib_cell->hasSequentials()) { + if (lib_cell->isSequential()) { return STD_SEQUENTIAL; } if (lib_cell->portCount() == 0) { diff --git a/src/dft/src/cells/ScanCellFactory.cpp b/src/dft/src/cells/ScanCellFactory.cpp index d38b308bc79..f71de201958 100644 --- a/src/dft/src/cells/ScanCellFactory.cpp +++ b/src/dft/src/cells/ScanCellFactory.cpp @@ -66,7 +66,7 @@ TypeOfCell IdentifyCell(odb::dbInst* inst, sta::dbSta* sta) sta::dbNetwork* db_network = sta->getDbNetwork(); sta::LibertyCell* liberty_cell = GetLibertyCell(inst->getMaster(), db_network); - if (liberty_cell != nullptr && liberty_cell->hasSequentials() + if (liberty_cell != nullptr && liberty_cell->isSequential() && !inst->getMaster()->isBlock()) { // we assume that we are only dealing with one bit cells, but in the future // we could deal with multibit cells too diff --git a/src/dft/src/replace/ScanReplace.cpp b/src/dft/src/replace/ScanReplace.cpp index 62a037b738d..88501f4d697 100644 --- a/src/dft/src/replace/ScanReplace.cpp +++ b/src/dft/src/replace/ScanReplace.cpp @@ -278,7 +278,7 @@ void ScanReplace::collectScanCellAvailable() } // We only care about sequential cells in DFT - if (!liberty_cell->hasSequentials()) { + if (!liberty_cell->isSequential()) { continue; } @@ -389,7 +389,7 @@ void ScanReplace::scanReplace(odb::dbBlock* block) continue; } - if (!from_liberty_cell->hasSequentials() + if (!from_liberty_cell->isSequential() || from_liberty_cell->isClockGate()) { // If the cell is not sequential, then there is nothing to replace continue; diff --git a/src/dft/src/utils/Utils.cpp b/src/dft/src/utils/Utils.cpp index 99339c513d9..626b915a31b 100644 --- a/src/dft/src/utils/Utils.cpp +++ b/src/dft/src/utils/Utils.cpp @@ -54,7 +54,7 @@ bool IsSequentialCell(sta::dbNetwork* db_network, odb::dbInst* instance) odb::dbMaster* master = instance->getMaster(); sta::Cell* master_cell = db_network->dbToSta(master); sta::LibertyCell* liberty_cell = db_network->libertyCell(master_cell); - return liberty_cell->hasSequentials(); + return liberty_cell->isSequential(); } odb::dbInst* ReplaceCell( diff --git a/src/est/src/EstimateParasitics.tcl b/src/est/src/EstimateParasitics.tcl index a7386a19164..0af39a918d2 100644 --- a/src/est/src/EstimateParasitics.tcl +++ b/src/est/src/EstimateParasitics.tcl @@ -405,7 +405,7 @@ proc check_corner_wire_caps { } { set have_rc 1 foreach corner [sta::scenes] { if { [est::wire_signal_capacitance $corner] == 0.0 } { - utl::warn EST 18 "wire capacitance for corner $corner is zero.\ + utl::warn EST 18 "wire capacitance for corner [get_name $corner] is zero.\ Use the set_wire_rc command to set wire resistance and capacitance." set have_rc 0 } diff --git a/src/gpl/src/mbff.cpp b/src/gpl/src/mbff.cpp index de0aeeb3721..802fb67ee71 100644 --- a/src/gpl/src/mbff.cpp +++ b/src/gpl/src/mbff.cpp @@ -2183,7 +2183,7 @@ bool MBFF::IsValidTray(dbInst* tray) return false; } const sta::LibertyCell* lib_cell = network_->testCell(cell); - if (lib_cell == nullptr || !lib_cell->hasSequentials()) { + if (lib_cell == nullptr || !lib_cell->isSequential()) { return false; } diff --git a/src/gui/src/gui.tcl b/src/gui/src/gui.tcl index cbf604ed315..3ba6132e712 100644 --- a/src/gui/src/gui.tcl +++ b/src/gui/src/gui.tcl @@ -173,7 +173,7 @@ proc save_clocktree_image { args } { utl::error GUI 88 "-clock is required" } - gui::save_clocktree_image $path $clock $scene $width $height + gui::save_clocktree_image $path $clock [get_name $scene] $width $height } sta::define_cmd_args "save_histogram_image" { diff --git a/src/gui/src/staDescriptors.cpp b/src/gui/src/staDescriptors.cpp index 0d7832cef52..8f5f8b23fec 100644 --- a/src/gui/src/staDescriptors.cpp +++ b/src/gui/src/staDescriptors.cpp @@ -292,7 +292,7 @@ Descriptor::Properties LibertyCellDescriptor::getProperties( } add_if_true(props, "Dont Use", cell->dontUse()); props.push_back({"Filename", cell->filename()}); - add_if_true(props, "Has Sequentials", cell->hasSequentials()); + add_if_true(props, "Has Sequentials", cell->isSequential()); add_if_true(props, "Is Always On", cell->alwaysOn()); add_if_true(props, "Is Buffer", cell->isBuffer()); add_if_true(props, "Is Clock Cell", cell->isClockCell()); diff --git a/src/par/src/ArtNetSpec.cpp b/src/par/src/ArtNetSpec.cpp index 2bb53c7ffcc..2b8cd06cd3b 100644 --- a/src/par/src/ArtNetSpec.cpp +++ b/src/par/src/ArtNetSpec.cpp @@ -157,7 +157,7 @@ void PartitionMgr::getFromODB( if (!lib_cell) { logger_->error(PAR, 56, "Liberty cell not found: {}", inst->getName()); } - if (lib_cell->hasSequentials()) { + if (lib_cell->isSequential()) { num_seq++; } auto [it, inserted] diff --git a/src/par/src/TritonPart.cpp b/src/par/src/TritonPart.cpp index dcb06c33217..0269e5f7a72 100644 --- a/src/par/src/TritonPart.cpp +++ b/src/par/src/TritonPart.cpp @@ -1292,7 +1292,7 @@ void TritonPart::ReadNetlist(const std::string& fixed_file, vertex_weights_.emplace_back(vwts); if (master->isBlock()) { vertex_types_.emplace_back(kMacro); - } else if (liberty_cell->hasSequentials()) { + } else if (liberty_cell->isSequential()) { vertex_types_.emplace_back(kSeqStdCell); } else { vertex_types_.emplace_back(kCombStdCell); @@ -1336,7 +1336,7 @@ void TritonPart::ReadNetlist(const std::string& fixed_file, vertex_weights_.emplace_back(vwts); if (master->isBlock()) { vertex_types_.emplace_back(kMacro); - } else if (liberty_cell->hasSequentials()) { + } else if (liberty_cell->isSequential()) { vertex_types_.emplace_back(kSeqStdCell); } else { vertex_types_.emplace_back(kCombStdCell); diff --git a/src/psm/test/zerosoc_pads.ok b/src/psm/test/zerosoc_pads.ok index 96c51469da6..1ab0af059f1 100644 --- a/src/psm/test/zerosoc_pads.ok +++ b/src/psm/test/zerosoc_pads.ok @@ -14,11 +14,11 @@ The NOWIREEXTENSIONATPIN statement will be ignored. See file sky130hd_data/io/sk ########## IR report ################# Net : vdd Corner : default -Total power : 8.97e-03 W +Total power : 8.80e-03 W Supply voltage : 1.80e+00 V Worstcase voltage: 1.80e+00 V Average voltage : 1.80e+00 V -Average IR drop : 1.62e-03 V -Worstcase IR drop: 2.34e-03 V +Average IR drop : 1.58e-03 V +Worstcase IR drop: 2.29e-03 V Percentage drop : 0.13 % ###################################### diff --git a/src/ram/src/ram.cpp b/src/ram/src/ram.cpp index 43536449bde..2d2c5378007 100644 --- a/src/ram/src/ram.cpp +++ b/src/ram/src/ram.cpp @@ -748,7 +748,7 @@ void RamGen::findMasters() return false; } auto cell = port->libertyCell(); - if (!cell->hasSequentials()) { + if (!cell->isSequential()) { return false; } bool has_latch_data = false; diff --git a/src/rmp/src/Restructure.cpp b/src/rmp/src/Restructure.cpp index 32c8b74566c..33dd1f210a2 100644 --- a/src/rmp/src/Restructure.cpp +++ b/src/rmp/src/Restructure.cpp @@ -450,7 +450,7 @@ void Restructure::removeConstCells() auto master = inst->getMaster(); sta::LibertyCell* cell = open_sta_->getDbNetwork()->libertyCell( open_sta_->getDbNetwork()->dbToSta(master)); - if (cell->hasSequentials()) { + if (cell->isSequential()) { continue; } diff --git a/src/rsz/src/MoveTracker.cc b/src/rsz/src/MoveTracker.cc index 500fd2108d0..3e8d3d05c85 100644 --- a/src/rsz/src/MoveTracker.cc +++ b/src/rsz/src/MoveTracker.cc @@ -2020,7 +2020,7 @@ void MoveTracker::printTopBinEndpoints(const std::string& title, sta::Instance* inst = sta_->network()->instance(pin); if (inst) { sta::LibertyCell* cell = sta_->network()->libertyCell(inst); - if (cell && cell->hasSequentials()) { + if (cell && cell->isSequential()) { // This is a sequential cell - check if pin is an output if (sta_->network()->direction(pin)->isOutput()) { startpoint_pin = pin; diff --git a/src/rsz/src/Resizer.cc b/src/rsz/src/Resizer.cc index 89fd259788d..38d7af4cdb7 100644 --- a/src/rsz/src/Resizer.cc +++ b/src/rsz/src/Resizer.cc @@ -202,7 +202,7 @@ void equivCellPinsForSwapReport(utl::Logger* logger, sta::LibertyPort* input_port, LibertyPortVec& ports) { - if (cell->hasSequentials() || cell->isIsolationCell()) { + if (cell->isSequential() || cell->isIsolationCell()) { ports.clear(); return; } @@ -1573,7 +1573,7 @@ bool Resizer::isCombinational(sta::LibertyCell* cell) const return false; } return (!cell->isClockGate() && !cell->isPad() && !cell->isMacro() - && !cell->hasSequentials()); + && !cell->isSequential()); } std::vector Resizer::libraryOutputPins( @@ -3334,7 +3334,7 @@ bool Resizer::isRegister(sta::Vertex* vertex) sta::LibertyPort* port = network_->libertyPort(vertex->pin()); if (port) { sta::LibertyCell* cell = port->libertyCell(); - return cell && cell->hasSequentials(); + return cell && cell->isSequential(); } return false; } diff --git a/src/rsz/src/move/SizeDownFanoutGenerator.cc b/src/rsz/src/move/SizeDownFanoutGenerator.cc index 81eb230300a..d5e6d3c60b1 100644 --- a/src/rsz/src/move/SizeDownFanoutGenerator.cc +++ b/src/rsz/src/move/SizeDownFanoutGenerator.cc @@ -423,7 +423,7 @@ SizeDownFanoutOutputProfile buildOutputProfile( sta::Slack computeDelayBudget(const SizeDownFanoutContext& ctx, const SizeDownFanoutLoadContext& load_ctx) { - if (load_ctx.load_cell->hasSequentials()) { + if (load_ctx.load_cell->isSequential()) { const sta::Slack worst_output_slack = getWorstOutputSlack(ctx, load_ctx.load_inst); debugPrint( @@ -514,7 +514,7 @@ float computeWorstDelayChange(const SizeDownFanoutContext& ctx, const float new_load_delay = ctx.resizer.gateDelay( output_port, profile.output_caps[output_index], ctx.scene, ctx.min_max); const float delay_change - = load_ctx.load_cell->hasSequentials() + = load_ctx.load_cell->isSequential() ? new_load_delay - profile.output_delays[output_index] : new_load_delay + drvr_delta_delay - profile.output_delays[output_index]; diff --git a/src/rsz/src/move/SwapPinsGenerator.cc b/src/rsz/src/move/SwapPinsGenerator.cc index 3d3e47b3b65..97e768a7761 100644 --- a/src/rsz/src/move/SwapPinsGenerator.cc +++ b/src/rsz/src/move/SwapPinsGenerator.cc @@ -210,7 +210,7 @@ void SwapPinsGenerator::equivCellPins(const sta::LibertyCell* cell, sta::LibertyPort* input_port, LibertyPortVec& ports) const { - if (cell->hasSequentials() || cell->isIsolationCell()) { + if (cell->isSequential() || cell->isIsolationCell()) { ports.clear(); return; } diff --git a/src/sta b/src/sta index 8572175ac45..3ab3337d1b8 160000 --- a/src/sta +++ b/src/sta @@ -1 +1 @@ -Subproject commit 8572175ac45c42ce8d3d772f73bbb059786b9c66 +Subproject commit 3ab3337d1b8f13bd15d80786ec771e1c6388d24a diff --git a/src/syn/src/flow/combinational_mapper.cc b/src/syn/src/flow/combinational_mapper.cc index 13d8986a68a..798feccd4f4 100644 --- a/src/syn/src/flow/combinational_mapper.cc +++ b/src/syn/src/flow/combinational_mapper.cc @@ -190,7 +190,7 @@ static void buildIndex(sta::Network* network, sta::LibertyCellIterator cell_iter(lib); while (cell_iter.hasNext()) { sta::LibertyCell* cell = cell_iter.next(); - if (cell->hasSequentials()) { + if (cell->isSequential()) { debugPrint(logger, utl::SYN, "cm", diff --git a/src/syn/src/flow/liveness.cc b/src/syn/src/flow/liveness.cc index 4e666ad56ea..7f1c8622d5b 100644 --- a/src/syn/src/flow/liveness.cc +++ b/src/syn/src/flow/liveness.cc @@ -353,7 +353,7 @@ void livenessOpt(Graph& g, utl::Logger* logger, bool replace_combinational) bool is_register = inst->is(); if (auto* t = inst->try_as()) { - if (t->cell() && t->cell()->hasSequentials()) { + if (t->cell() && t->cell()->isSequential()) { is_register = true; } } diff --git a/src/syn/src/flow/opt_gatefusion.cc b/src/syn/src/flow/opt_gatefusion.cc index dad91119d2b..e477b1d7fc1 100644 --- a/src/syn/src/flow/opt_gatefusion.cc +++ b/src/syn/src/flow/opt_gatefusion.cc @@ -373,7 +373,7 @@ static CellIndex buildIndex(sta::Network* network, sta::LibertyCellIterator cell_iter(lib); while (cell_iter.hasNext()) { sta::LibertyCell* cell = cell_iter.next(); - if (syn.dontUse(cell) || cell->hasSequentials()) { + if (syn.dontUse(cell) || cell->isSequential()) { continue; } diff --git a/src/syn/src/flow/sequential_mapper.cc b/src/syn/src/flow/sequential_mapper.cc index ff28edd40ba..daf345ab69f 100644 --- a/src/syn/src/flow/sequential_mapper.cc +++ b/src/syn/src/flow/sequential_mapper.cc @@ -165,7 +165,7 @@ static int inputPortPosition(sta::LibertyCell* cell, sta::LibertyPort* target) static bool detectCell(sta::LibertyCell* cell, MapTarget& result) { - if (!cell->hasSequentials()) { + if (!cell->isSequential()) { return false; } auto& seqs = cell->sequentials(); diff --git a/src/syn/src/ir/Instance.cc b/src/syn/src/ir/Instance.cc index 470401787a7..76e00840638 100644 --- a/src/syn/src/ir/Instance.cc +++ b/src/syn/src/ir/Instance.cc @@ -674,7 +674,7 @@ bool Instance::hasState() const case EntryType::kOther: return true; case EntryType::kTarget: - return static_cast(this)->cell()->hasSequentials(); + return static_cast(this)->cell()->isSequential(); default: return false; } diff --git a/src/syn/src/ir/TritModel.cc b/src/syn/src/ir/TritModel.cc index 465dcb2b16f..8cdf3f77d15 100644 --- a/src/syn/src/ir/TritModel.cc +++ b/src/syn/src/ir/TritModel.cc @@ -692,7 +692,7 @@ void TritModel::encodeInstance(const Instance* inst) } else if (inst->is()) { auto* op = inst->as(); sta::LibertyCell* cell = op->cell(); - if (!cell->hasSequentials()) { + if (!cell->isSequential()) { // Build port→index map for inputs, collect output ports. std::vector in_ports; std::vector out_ports; diff --git a/src/web/src/request_handler.cpp b/src/web/src/request_handler.cpp index 39665ada4c5..0f95e00a074 100644 --- a/src/web/src/request_handler.cpp +++ b/src/web/src/request_handler.cpp @@ -1263,7 +1263,7 @@ static GateClass classifyGate(sta::dbNetwork* network, odb::dbInst* inst) return result; } sta::LibertyCell* cell = network->libertyCell(inst); - if (cell == nullptr || cell->hasSequentials() || cell->isClockGate() + if (cell == nullptr || cell->isSequential() || cell->isClockGate() || cell->isMacro()) { return result; }