riscv-multicycle-cpu/decoder.v at main · Karaammm/riscv-multicycle-cpu · GitHub

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/* Generated by Yosys 0.59+134 (git sha1 9871e9b17, aarch64-apple-darwin23.5-clang++ 18.1.8 -fPIC -O3) */

module decoder (
    addr_i,
    en_ram_o,
    en_leds_o,
    en_7_seg_lcd_o,
    en_buttons_o
);
  input [31:0] addr_i;
  wire [31:0] addr_i;
  output en_ram_o;
  wire en_ram_o;
  output en_leds_o;
  wire en_leds_o;
  output en_7_seg_lcd_o;
  wire en_7_seg_lcd_o;
  output en_buttons_o;
  wire en_buttons_o;
  wire _00_;
  wire _01_;
  wire _02_;
  wire _03_;
  wire _04_;
  wire _05_;
  assign en_ram_o = addr_i >= 32'd2147483648;
  assign _00_ = addr_i >= 32'd1879048192;
  assign _01_ = addr_i >= 32'd1610612736;
  assign _02_ = addr_i >= 32'd1342177280;
  assign en_buttons_o = _00_ && _03_;
  assign en_7_seg_lcd_o = _01_ && _04_;
  assign en_leds_o = _02_ && _05_;
  assign _03_ = addr_i < 32'd1879052288;
  assign _04_ = addr_i < 32'd1610616832;
  assign _05_ = addr_i < 32'd1342181376;
endmodule